reset.c 7.1 KB

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  1. /*
  2. *
  3. * BRIEF MODULE DESCRIPTION
  4. * Au1000 reset routines.
  5. *
  6. * Copyright 2001 MontaVista Software Inc.
  7. * Author: MontaVista Software, Inc.
  8. * ppopov@mvista.com or source@mvista.com
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  21. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. *
  26. * You should have received a copy of the GNU General Public License along
  27. * with this program; if not, write to the Free Software Foundation, Inc.,
  28. * 675 Mass Ave, Cambridge, MA 02139, USA.
  29. */
  30. #include <linux/config.h>
  31. #include <linux/sched.h>
  32. #include <linux/mm.h>
  33. #include <asm/io.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/processor.h>
  36. #include <asm/reboot.h>
  37. #include <asm/system.h>
  38. #include <asm/mach-au1x00/au1000.h>
  39. extern int au_sleep(void);
  40. extern void (*flush_cache_all)(void);
  41. void au1000_restart(char *command)
  42. {
  43. /* Set all integrated peripherals to disabled states */
  44. extern void board_reset (void);
  45. u32 prid = read_c0_prid();
  46. printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
  47. switch (prid & 0xFF000000)
  48. {
  49. case 0x00000000: /* Au1000 */
  50. au_writel(0x02, 0xb0000010); /* ac97_enable */
  51. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  52. asm("sync");
  53. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  54. au_writel(0x00, 0xb0200058); /* usbd_enable */
  55. au_writel(0x00, 0xb0300040); /* ir_enable */
  56. au_writel(0x00, 0xb4004104); /* mac dma */
  57. au_writel(0x00, 0xb4004114); /* mac dma */
  58. au_writel(0x00, 0xb4004124); /* mac dma */
  59. au_writel(0x00, 0xb4004134); /* mac dma */
  60. au_writel(0x00, 0xb0520000); /* macen0 */
  61. au_writel(0x00, 0xb0520004); /* macen1 */
  62. au_writel(0x00, 0xb1000008); /* i2s_enable */
  63. au_writel(0x00, 0xb1100100); /* uart0_enable */
  64. au_writel(0x00, 0xb1200100); /* uart1_enable */
  65. au_writel(0x00, 0xb1300100); /* uart2_enable */
  66. au_writel(0x00, 0xb1400100); /* uart3_enable */
  67. au_writel(0x02, 0xb1600100); /* ssi0_enable */
  68. au_writel(0x02, 0xb1680100); /* ssi1_enable */
  69. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  70. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  71. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  72. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  73. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  74. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  75. break;
  76. case 0x01000000: /* Au1500 */
  77. au_writel(0x02, 0xb0000010); /* ac97_enable */
  78. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  79. asm("sync");
  80. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  81. au_writel(0x00, 0xb0200058); /* usbd_enable */
  82. au_writel(0x00, 0xb4004104); /* mac dma */
  83. au_writel(0x00, 0xb4004114); /* mac dma */
  84. au_writel(0x00, 0xb4004124); /* mac dma */
  85. au_writel(0x00, 0xb4004134); /* mac dma */
  86. au_writel(0x00, 0xb1520000); /* macen0 */
  87. au_writel(0x00, 0xb1520004); /* macen1 */
  88. au_writel(0x00, 0xb1100100); /* uart0_enable */
  89. au_writel(0x00, 0xb1400100); /* uart3_enable */
  90. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  91. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  92. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  93. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  94. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  95. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  96. break;
  97. case 0x02000000: /* Au1100 */
  98. au_writel(0x02, 0xb0000010); /* ac97_enable */
  99. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  100. asm("sync");
  101. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  102. au_writel(0x00, 0xb0200058); /* usbd_enable */
  103. au_writel(0x00, 0xb0300040); /* ir_enable */
  104. au_writel(0x00, 0xb4004104); /* mac dma */
  105. au_writel(0x00, 0xb4004114); /* mac dma */
  106. au_writel(0x00, 0xb4004124); /* mac dma */
  107. au_writel(0x00, 0xb4004134); /* mac dma */
  108. au_writel(0x00, 0xb0520000); /* macen0 */
  109. au_writel(0x00, 0xb1000008); /* i2s_enable */
  110. au_writel(0x00, 0xb1100100); /* uart0_enable */
  111. au_writel(0x00, 0xb1200100); /* uart1_enable */
  112. au_writel(0x00, 0xb1400100); /* uart3_enable */
  113. au_writel(0x02, 0xb1600100); /* ssi0_enable */
  114. au_writel(0x02, 0xb1680100); /* ssi1_enable */
  115. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  116. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  117. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  118. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  119. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  120. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  121. break;
  122. case 0x03000000: /* Au1550 */
  123. au_writel(0x00, 0xb1a00004); /* psc 0 */
  124. au_writel(0x00, 0xb1b00004); /* psc 1 */
  125. au_writel(0x00, 0xb0a00004); /* psc 2 */
  126. au_writel(0x00, 0xb0b00004); /* psc 3 */
  127. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  128. au_writel(0x00, 0xb0200058); /* usbd_enable */
  129. au_writel(0x00, 0xb4004104); /* mac dma */
  130. au_writel(0x00, 0xb4004114); /* mac dma */
  131. au_writel(0x00, 0xb4004124); /* mac dma */
  132. au_writel(0x00, 0xb4004134); /* mac dma */
  133. au_writel(0x00, 0xb1520000); /* macen0 */
  134. au_writel(0x00, 0xb1520004); /* macen1 */
  135. au_writel(0x00, 0xb1100100); /* uart0_enable */
  136. au_writel(0x00, 0xb1200100); /* uart1_enable */
  137. au_writel(0x00, 0xb1400100); /* uart3_enable */
  138. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  139. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  140. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  141. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  142. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  143. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  144. break;
  145. default:
  146. break;
  147. }
  148. set_c0_status(ST0_BEV | ST0_ERL);
  149. set_c0_config(CONF_CM_UNCACHED);
  150. flush_cache_all();
  151. write_c0_wired(0);
  152. /* Give board a chance to do a hardware reset */
  153. board_reset();
  154. /* Jump to the beggining in case board_reset() is empty */
  155. __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
  156. }
  157. void au1000_halt(void)
  158. {
  159. #if defined(CONFIG_MIPS_PB1550)
  160. /* power off system */
  161. printk("\n** Powering off Pb1550\n");
  162. au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
  163. au_sync();
  164. while(1); /* should not get here */
  165. #endif
  166. printk(KERN_NOTICE "\n** You can safely turn off the power\n");
  167. #ifdef CONFIG_MIPS_MIRAGE
  168. au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
  169. #endif
  170. #ifdef CONFIG_PM
  171. au_sleep();
  172. /* should not get here */
  173. printk(KERN_ERR "Unable to put cpu in sleep mode\n");
  174. while(1);
  175. #else
  176. while (1)
  177. __asm__(".set\tmips3\n\t"
  178. "wait\n\t"
  179. ".set\tmips0");
  180. #endif
  181. }
  182. void au1000_power_off(void)
  183. {
  184. au1000_halt();
  185. }