config.c 7.0 KB

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  1. #include <linux/config.h>
  2. #include <linux/types.h>
  3. #include <linux/kernel.h>
  4. #include <linux/mm.h>
  5. #include <linux/tty.h>
  6. #include <linux/console.h>
  7. #include <linux/rtc.h>
  8. #include <linux/vt_kern.h>
  9. #include <linux/interrupt.h>
  10. #include <asm/setup.h>
  11. #include <asm/bootinfo.h>
  12. #include <asm/system.h>
  13. #include <asm/pgtable.h>
  14. #include <asm/apollohw.h>
  15. #include <asm/irq.h>
  16. #include <asm/rtc.h>
  17. #include <asm/machdep.h>
  18. u_long sio01_physaddr;
  19. u_long sio23_physaddr;
  20. u_long rtc_physaddr;
  21. u_long pica_physaddr;
  22. u_long picb_physaddr;
  23. u_long cpuctrl_physaddr;
  24. u_long timer_physaddr;
  25. u_long apollo_model;
  26. extern void dn_sched_init(irqreturn_t (*handler)(int,void *,struct pt_regs *));
  27. extern void dn_init_IRQ(void);
  28. extern int dn_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id);
  29. extern void dn_free_irq(unsigned int irq, void *dev_id);
  30. extern void dn_enable_irq(unsigned int);
  31. extern void dn_disable_irq(unsigned int);
  32. extern int show_dn_interrupts(struct seq_file *, void *);
  33. extern unsigned long dn_gettimeoffset(void);
  34. extern int dn_dummy_hwclk(int, struct rtc_time *);
  35. extern int dn_dummy_set_clock_mmss(unsigned long);
  36. extern void dn_dummy_reset(void);
  37. extern void dn_dummy_waitbut(void);
  38. extern struct fb_info *dn_fb_init(long *);
  39. extern void dn_dummy_debug_init(void);
  40. extern void dn_dummy_video_setup(char *,int *);
  41. extern irqreturn_t dn_process_int(int irq, struct pt_regs *fp);
  42. #ifdef CONFIG_HEARTBEAT
  43. static void dn_heartbeat(int on);
  44. #endif
  45. static irqreturn_t dn_timer_int(int irq,void *, struct pt_regs *);
  46. static irqreturn_t (*sched_timer_handler)(int, void *, struct pt_regs *)=NULL;
  47. static void dn_get_model(char *model);
  48. static const char *apollo_models[] = {
  49. [APOLLO_DN3000-APOLLO_DN3000] = "DN3000 (Otter)",
  50. [APOLLO_DN3010-APOLLO_DN3000] = "DN3010 (Otter)",
  51. [APOLLO_DN3500-APOLLO_DN3000] = "DN3500 (Cougar II)",
  52. [APOLLO_DN4000-APOLLO_DN3000] = "DN4000 (Mink)",
  53. [APOLLO_DN4500-APOLLO_DN3000] = "DN4500 (Roadrunner)"
  54. };
  55. int apollo_parse_bootinfo(const struct bi_record *record) {
  56. int unknown = 0;
  57. const unsigned long *data = record->data;
  58. switch(record->tag) {
  59. case BI_APOLLO_MODEL:
  60. apollo_model=*data;
  61. break;
  62. default:
  63. unknown=1;
  64. }
  65. return unknown;
  66. }
  67. void dn_setup_model(void) {
  68. printk("Apollo hardware found: ");
  69. printk("[%s]\n", apollo_models[apollo_model - APOLLO_DN3000]);
  70. switch(apollo_model) {
  71. case APOLLO_UNKNOWN:
  72. panic("Unknown apollo model");
  73. break;
  74. case APOLLO_DN3000:
  75. case APOLLO_DN3010:
  76. sio01_physaddr=SAU8_SIO01_PHYSADDR;
  77. rtc_physaddr=SAU8_RTC_PHYSADDR;
  78. pica_physaddr=SAU8_PICA;
  79. picb_physaddr=SAU8_PICB;
  80. cpuctrl_physaddr=SAU8_CPUCTRL;
  81. timer_physaddr=SAU8_TIMER;
  82. break;
  83. case APOLLO_DN4000:
  84. sio01_physaddr=SAU7_SIO01_PHYSADDR;
  85. sio23_physaddr=SAU7_SIO23_PHYSADDR;
  86. rtc_physaddr=SAU7_RTC_PHYSADDR;
  87. pica_physaddr=SAU7_PICA;
  88. picb_physaddr=SAU7_PICB;
  89. cpuctrl_physaddr=SAU7_CPUCTRL;
  90. timer_physaddr=SAU7_TIMER;
  91. break;
  92. case APOLLO_DN4500:
  93. panic("Apollo model not yet supported");
  94. break;
  95. case APOLLO_DN3500:
  96. sio01_physaddr=SAU7_SIO01_PHYSADDR;
  97. sio23_physaddr=SAU7_SIO23_PHYSADDR;
  98. rtc_physaddr=SAU7_RTC_PHYSADDR;
  99. pica_physaddr=SAU7_PICA;
  100. picb_physaddr=SAU7_PICB;
  101. cpuctrl_physaddr=SAU7_CPUCTRL;
  102. timer_physaddr=SAU7_TIMER;
  103. break;
  104. default:
  105. panic("Undefined apollo model");
  106. break;
  107. }
  108. }
  109. int dn_serial_console_wait_key(struct console *co) {
  110. while(!(sio01.srb_csrb & 1))
  111. barrier();
  112. return sio01.rhrb_thrb;
  113. }
  114. void dn_serial_console_write (struct console *co, const char *str,unsigned int count)
  115. {
  116. while(count--) {
  117. if (*str == '\n') {
  118. sio01.rhrb_thrb = (unsigned char)'\r';
  119. while (!(sio01.srb_csrb & 0x4))
  120. ;
  121. }
  122. sio01.rhrb_thrb = (unsigned char)*str++;
  123. while (!(sio01.srb_csrb & 0x4))
  124. ;
  125. }
  126. }
  127. void dn_serial_print (const char *str)
  128. {
  129. while (*str) {
  130. if (*str == '\n') {
  131. sio01.rhrb_thrb = (unsigned char)'\r';
  132. while (!(sio01.srb_csrb & 0x4))
  133. ;
  134. }
  135. sio01.rhrb_thrb = (unsigned char)*str++;
  136. while (!(sio01.srb_csrb & 0x4))
  137. ;
  138. }
  139. }
  140. void config_apollo(void) {
  141. int i;
  142. dn_setup_model();
  143. mach_sched_init=dn_sched_init; /* */
  144. mach_init_IRQ=dn_init_IRQ;
  145. mach_default_handler=NULL;
  146. mach_request_irq = dn_request_irq;
  147. mach_free_irq = dn_free_irq;
  148. enable_irq = dn_enable_irq;
  149. disable_irq = dn_disable_irq;
  150. mach_get_irq_list = show_dn_interrupts;
  151. mach_gettimeoffset = dn_gettimeoffset;
  152. mach_max_dma_address = 0xffffffff;
  153. mach_hwclk = dn_dummy_hwclk; /* */
  154. mach_set_clock_mmss = dn_dummy_set_clock_mmss; /* */
  155. mach_process_int = dn_process_int;
  156. mach_reset = dn_dummy_reset; /* */
  157. #ifdef CONFIG_DUMMY_CONSOLE
  158. conswitchp = &dummy_con;
  159. #endif
  160. #ifdef CONFIG_HEARTBEAT
  161. mach_heartbeat = dn_heartbeat;
  162. #endif
  163. mach_get_model = dn_get_model;
  164. cpuctrl=0xaa00;
  165. /* clear DMA translation table */
  166. for(i=0;i<0x400;i++)
  167. addr_xlat_map[i]=0;
  168. }
  169. irqreturn_t dn_timer_int(int irq, void *dev_id, struct pt_regs *fp) {
  170. volatile unsigned char x;
  171. sched_timer_handler(irq,dev_id,fp);
  172. x=*(volatile unsigned char *)(timer+3);
  173. x=*(volatile unsigned char *)(timer+5);
  174. return IRQ_HANDLED;
  175. }
  176. void dn_sched_init(irqreturn_t (*timer_routine)(int, void *, struct pt_regs *)) {
  177. /* program timer 1 */
  178. *(volatile unsigned char *)(timer+3)=0x01;
  179. *(volatile unsigned char *)(timer+1)=0x40;
  180. *(volatile unsigned char *)(timer+5)=0x09;
  181. *(volatile unsigned char *)(timer+7)=0xc4;
  182. /* enable IRQ of PIC B */
  183. *(volatile unsigned char *)(pica+1)&=(~8);
  184. #if 0
  185. printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3));
  186. printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3));
  187. #endif
  188. sched_timer_handler=timer_routine;
  189. request_irq(0,dn_timer_int,0,NULL,NULL);
  190. }
  191. unsigned long dn_gettimeoffset(void) {
  192. return 0xdeadbeef;
  193. }
  194. int dn_dummy_hwclk(int op, struct rtc_time *t) {
  195. if(!op) { /* read */
  196. t->tm_sec=rtc->second;
  197. t->tm_min=rtc->minute;
  198. t->tm_hour=rtc->hours;
  199. t->tm_mday=rtc->day_of_month;
  200. t->tm_wday=rtc->day_of_week;
  201. t->tm_mon=rtc->month;
  202. t->tm_year=rtc->year;
  203. } else {
  204. rtc->second=t->tm_sec;
  205. rtc->minute=t->tm_min;
  206. rtc->hours=t->tm_hour;
  207. rtc->day_of_month=t->tm_mday;
  208. if(t->tm_wday!=-1)
  209. rtc->day_of_week=t->tm_wday;
  210. rtc->month=t->tm_mon;
  211. rtc->year=t->tm_year;
  212. }
  213. return 0;
  214. }
  215. int dn_dummy_set_clock_mmss(unsigned long nowtime) {
  216. printk("set_clock_mmss\n");
  217. return 0;
  218. }
  219. void dn_dummy_reset(void) {
  220. dn_serial_print("The end !\n");
  221. for(;;);
  222. }
  223. void dn_dummy_waitbut(void) {
  224. dn_serial_print("waitbut\n");
  225. }
  226. static void dn_get_model(char *model)
  227. {
  228. strcpy(model, "Apollo ");
  229. if (apollo_model >= APOLLO_DN3000 && apollo_model <= APOLLO_DN4500)
  230. strcat(model, apollo_models[apollo_model - APOLLO_DN3000]);
  231. }
  232. #ifdef CONFIG_HEARTBEAT
  233. static int dn_cpuctrl=0xff00;
  234. static void dn_heartbeat(int on) {
  235. if(on) {
  236. dn_cpuctrl&=~0x100;
  237. cpuctrl=dn_cpuctrl;
  238. }
  239. else {
  240. dn_cpuctrl&=~0x100;
  241. dn_cpuctrl|=0x100;
  242. cpuctrl=dn_cpuctrl;
  243. }
  244. }
  245. #endif