ptc_deadlock.S 2.1 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. #include <asm/types.h>
  9. #include <asm/sn/shub_mmr.h>
  10. #define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
  11. #define WRITECOUNTMASK SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
  12. #define ALIAS_OFFSET 8
  13. .global sn2_ptc_deadlock_recovery_core
  14. .proc sn2_ptc_deadlock_recovery_core
  15. sn2_ptc_deadlock_recovery_core:
  16. .regstk 6,0,0,0
  17. ptc0 = in0
  18. data0 = in1
  19. ptc1 = in2
  20. data1 = in3
  21. piowc = in4
  22. zeroval = in5
  23. piowcphy = r30
  24. psrsave = r2
  25. scr1 = r16
  26. scr2 = r17
  27. mask = r18
  28. extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address
  29. dep piowcphy=-1,piowcphy,63,1
  30. movl mask=WRITECOUNTMASK
  31. mov r8=r0
  32. 1:
  33. add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register
  34. ;;
  35. ld8.acq scr1=[scr2];;
  36. 5: ld8.acq scr1=[piowc];; // Wait for PIOs to complete.
  37. hint @pause
  38. and scr2=scr1,mask;; // mask of writecount bits
  39. cmp.ne p6,p0=zeroval,scr2
  40. (p6) br.cond.sptk 5b
  41. ////////////// BEGIN PHYSICAL MODE ////////////////////
  42. mov psrsave=psr // Disable IC (no PMIs)
  43. rsm psr.i | psr.dt | psr.ic;;
  44. srlz.i;;
  45. st8.rel [ptc0]=data0 // Write PTC0 & wait for completion.
  46. 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
  47. hint @pause
  48. and scr2=scr1,mask;; // mask of writecount bits
  49. cmp.ne p6,p0=zeroval,scr2
  50. (p6) br.cond.sptk 5b;;
  51. tbit.nz p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
  52. (p7) cmp.ne p7,p0=r0,ptc1;; // Test for non-null ptc1
  53. (p7) st8.rel [ptc1]=data1;; // Now write PTC1.
  54. 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
  55. hint @pause
  56. and scr2=scr1,mask;; // mask of writecount bits
  57. cmp.ne p6,p0=zeroval,scr2
  58. (p6) br.cond.sptk 5b
  59. tbit.nz p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
  60. mov psr.l=psrsave;; // Reenable IC
  61. srlz.i;;
  62. ////////////// END PHYSICAL MODE ////////////////////
  63. (p8) add r8=1,r8
  64. (p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred.
  65. br.ret.sptk rp
  66. .endp sn2_ptc_deadlock_recovery_core