xbow.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
  7. */
  8. #ifndef _ASM_IA64_SN_XTALK_XBOW_H
  9. #define _ASM_IA64_SN_XTALK_XBOW_H
  10. #define XBOW_PORT_8 0x8
  11. #define XBOW_PORT_C 0xc
  12. #define XBOW_PORT_F 0xf
  13. #define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */
  14. #define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */
  15. #define XBOW_CREDIT 4
  16. #define MAX_XBOW_NAME 16
  17. /* Register set for each xbow link */
  18. typedef volatile struct xb_linkregs_s {
  19. /*
  20. * we access these through synergy unswizzled space, so the address
  21. * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
  22. * That's why we put the register first and filler second.
  23. */
  24. uint32_t link_ibf;
  25. uint32_t filler0; /* filler for proper alignment */
  26. uint32_t link_control;
  27. uint32_t filler1;
  28. uint32_t link_status;
  29. uint32_t filler2;
  30. uint32_t link_arb_upper;
  31. uint32_t filler3;
  32. uint32_t link_arb_lower;
  33. uint32_t filler4;
  34. uint32_t link_status_clr;
  35. uint32_t filler5;
  36. uint32_t link_reset;
  37. uint32_t filler6;
  38. uint32_t link_aux_status;
  39. uint32_t filler7;
  40. } xb_linkregs_t;
  41. typedef volatile struct xbow_s {
  42. /* standard widget configuration 0x000000-0x000057 */
  43. struct widget_cfg xb_widget; /* 0x000000 */
  44. /* helper fieldnames for accessing bridge widget */
  45. #define xb_wid_id xb_widget.w_id
  46. #define xb_wid_stat xb_widget.w_status
  47. #define xb_wid_err_upper xb_widget.w_err_upper_addr
  48. #define xb_wid_err_lower xb_widget.w_err_lower_addr
  49. #define xb_wid_control xb_widget.w_control
  50. #define xb_wid_req_timeout xb_widget.w_req_timeout
  51. #define xb_wid_int_upper xb_widget.w_intdest_upper_addr
  52. #define xb_wid_int_lower xb_widget.w_intdest_lower_addr
  53. #define xb_wid_err_cmdword xb_widget.w_err_cmd_word
  54. #define xb_wid_llp xb_widget.w_llp_cfg
  55. #define xb_wid_stat_clr xb_widget.w_tflush
  56. /*
  57. * we access these through synergy unswizzled space, so the address
  58. * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
  59. * That's why we put the register first and filler second.
  60. */
  61. /* xbow-specific widget configuration 0x000058-0x0000FF */
  62. uint32_t xb_wid_arb_reload; /* 0x00005C */
  63. uint32_t _pad_000058;
  64. uint32_t xb_perf_ctr_a; /* 0x000064 */
  65. uint32_t _pad_000060;
  66. uint32_t xb_perf_ctr_b; /* 0x00006c */
  67. uint32_t _pad_000068;
  68. uint32_t xb_nic; /* 0x000074 */
  69. uint32_t _pad_000070;
  70. /* Xbridge only */
  71. uint32_t xb_w0_rst_fnc; /* 0x00007C */
  72. uint32_t _pad_000078;
  73. uint32_t xb_l8_rst_fnc; /* 0x000084 */
  74. uint32_t _pad_000080;
  75. uint32_t xb_l9_rst_fnc; /* 0x00008c */
  76. uint32_t _pad_000088;
  77. uint32_t xb_la_rst_fnc; /* 0x000094 */
  78. uint32_t _pad_000090;
  79. uint32_t xb_lb_rst_fnc; /* 0x00009c */
  80. uint32_t _pad_000098;
  81. uint32_t xb_lc_rst_fnc; /* 0x0000a4 */
  82. uint32_t _pad_0000a0;
  83. uint32_t xb_ld_rst_fnc; /* 0x0000ac */
  84. uint32_t _pad_0000a8;
  85. uint32_t xb_le_rst_fnc; /* 0x0000b4 */
  86. uint32_t _pad_0000b0;
  87. uint32_t xb_lf_rst_fnc; /* 0x0000bc */
  88. uint32_t _pad_0000b8;
  89. uint32_t xb_lock; /* 0x0000c4 */
  90. uint32_t _pad_0000c0;
  91. uint32_t xb_lock_clr; /* 0x0000cc */
  92. uint32_t _pad_0000c8;
  93. /* end of Xbridge only */
  94. uint32_t _pad_0000d0[12];
  95. /* Link Specific Registers, port 8..15 0x000100-0x000300 */
  96. xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
  97. #define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
  98. } xbow_t;
  99. #define XB_FLAGS_EXISTS 0x1 /* device exists */
  100. #define XB_FLAGS_MASTER 0x2
  101. #define XB_FLAGS_SLAVE 0x0
  102. #define XB_FLAGS_GBR 0x4
  103. #define XB_FLAGS_16BIT 0x8
  104. #define XB_FLAGS_8BIT 0x0
  105. /* is widget port number valid? (based on version 7.0 of xbow spec) */
  106. #define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
  107. /* whether to use upper or lower arbitration register, given source widget id */
  108. #define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
  109. #define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
  110. /* offset of arbitration register, given source widget id */
  111. #define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
  112. #define XBOW_WID_ID WIDGET_ID
  113. #define XBOW_WID_STAT WIDGET_STATUS
  114. #define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
  115. #define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
  116. #define XBOW_WID_CONTROL WIDGET_CONTROL
  117. #define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT
  118. #define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
  119. #define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
  120. #define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
  121. #define XBOW_WID_LLP WIDGET_LLP_CFG
  122. #define XBOW_WID_STAT_CLR WIDGET_TFLUSH
  123. #define XBOW_WID_ARB_RELOAD 0x5c
  124. #define XBOW_WID_PERF_CTR_A 0x64
  125. #define XBOW_WID_PERF_CTR_B 0x6c
  126. #define XBOW_WID_NIC 0x74
  127. /* Xbridge only */
  128. #define XBOW_W0_RST_FNC 0x00007C
  129. #define XBOW_L8_RST_FNC 0x000084
  130. #define XBOW_L9_RST_FNC 0x00008c
  131. #define XBOW_LA_RST_FNC 0x000094
  132. #define XBOW_LB_RST_FNC 0x00009c
  133. #define XBOW_LC_RST_FNC 0x0000a4
  134. #define XBOW_LD_RST_FNC 0x0000ac
  135. #define XBOW_LE_RST_FNC 0x0000b4
  136. #define XBOW_LF_RST_FNC 0x0000bc
  137. #define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
  138. (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
  139. ((x) == 0) ? XBOW_W0_RST_FNC : 0
  140. #define XBOW_LOCK 0x0000c4
  141. #define XBOW_LOCK_CLR 0x0000cc
  142. /* End of Xbridge only */
  143. /* used only in ide, but defined here within the reserved portion */
  144. /* of the widget0 address space (before 0xf4) */
  145. #define XBOW_WID_UNDEF 0xe4
  146. /* xbow link register set base, legal value for x is 0x8..0xf */
  147. #define XB_LINK_BASE 0x100
  148. #define XB_LINK_OFFSET 0x40
  149. #define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
  150. #define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4)
  151. #define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc)
  152. #define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14)
  153. #define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c)
  154. #define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24)
  155. #define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c)
  156. #define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34)
  157. #define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c)
  158. /* link_control(x) */
  159. #define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
  160. /* reserved: 0x40000000 */
  161. #define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
  162. #define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */
  163. #define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */
  164. #define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */
  165. #define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */
  166. #define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */
  167. #define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */
  168. #define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */
  169. /* reserved: 0x0000fe00 */
  170. #define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
  171. #define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
  172. #define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
  173. #define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
  174. #define XB_CTRL_RCV_IE 0x00000010 /* receive */
  175. #define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
  176. /* reserved: 0x00000004 */
  177. #define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */
  178. #define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
  179. /* link_status(x) */
  180. #define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
  181. /* reserved: 0x7ff80000 */
  182. #define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
  183. #define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
  184. #define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
  185. #define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */
  186. #define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE
  187. #define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE
  188. #define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
  189. #define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
  190. #define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
  191. /* reserved: 0x00000004 */
  192. #define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
  193. #define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
  194. /* link_aux_status(x) */
  195. #define XB_AUX_STAT_RCV_CNT 0xff000000
  196. #define XB_AUX_STAT_XMT_CNT 0x00ff0000
  197. #define XB_AUX_STAT_TOUT_DST 0x0000ff00
  198. #define XB_AUX_LINKFAIL_RST_BAD 0x00000040
  199. #define XB_AUX_STAT_PRESENT 0x00000020
  200. #define XB_AUX_STAT_PORT_WIDTH 0x00000010
  201. /* reserved: 0x0000000f */
  202. /*
  203. * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
  204. * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
  205. */
  206. #define XB_ARB_GBR_MSK 0x1f
  207. #define XB_ARB_RR_MSK 0x7
  208. #define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8)
  209. #define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5)
  210. #define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
  211. #define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
  212. /* XBOW_WID_STAT */
  213. #define XB_WID_STAT_LINK_INTR_SHFT (24)
  214. #define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
  215. #define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
  216. #define XB_WID_STAT_WIDGET0_INTR 0x00800000
  217. #define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
  218. #define XB_WID_STAT_REG_ACC_ERR 0x00000020
  219. #define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */
  220. #define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */
  221. #define XB_WID_STAT_XTALK_ERR 0x00000004
  222. #define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */
  223. #define XB_WID_STAT_MULTI_ERR 0x00000001
  224. #define XB_WID_STAT_SRCID_SHFT 6
  225. /* XBOW_WID_CONTROL */
  226. #define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR
  227. #define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT
  228. #define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT
  229. #define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR
  230. /* XBOW_WID_INT_UPPER */
  231. /* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
  232. /* XBOW WIDGET part number, in the ID register */
  233. #define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */
  234. #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
  235. #define XBOW_WIDGET_MFGR_NUM 0x0
  236. #define XXBOW_WIDGET_MFGR_NUM 0x0
  237. #define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */
  238. #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
  239. #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
  240. #define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */
  241. #define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */
  242. #define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */
  243. #define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
  244. #define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
  245. /* XBOW_WID_ARB_RELOAD */
  246. #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
  247. #define IS_XBRIDGE_XBOW(wid) \
  248. (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
  249. XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
  250. #define IS_PIC_XBOW(wid) \
  251. (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
  252. XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
  253. #define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
  254. #endif /* _ASM_IA64_SN_XTALK_XBOW_H */