state.c 2.0 KB

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  1. #include <linux/mm.h>
  2. #include <linux/init.h>
  3. #include <asm/io.h>
  4. #include <asm/mtrr.h>
  5. #include <asm/msr.h>
  6. #include "mtrr.h"
  7. /* Put the processor into a state where MTRRs can be safely set */
  8. void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
  9. {
  10. unsigned int cr0;
  11. /* Disable interrupts locally */
  12. local_irq_save(ctxt->flags);
  13. if (use_intel() || is_cpu(CYRIX)) {
  14. /* Save value of CR4 and clear Page Global Enable (bit 7) */
  15. if ( cpu_has_pge ) {
  16. ctxt->cr4val = read_cr4();
  17. write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7));
  18. }
  19. /* Disable and flush caches. Note that wbinvd flushes the TLBs as
  20. a side-effect */
  21. cr0 = read_cr0() | 0x40000000;
  22. wbinvd();
  23. write_cr0(cr0);
  24. wbinvd();
  25. if (use_intel())
  26. /* Save MTRR state */
  27. rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  28. else
  29. /* Cyrix ARRs - everything else were excluded at the top */
  30. ctxt->ccr3 = getCx86(CX86_CCR3);
  31. }
  32. }
  33. void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
  34. {
  35. if (use_intel())
  36. /* Disable MTRRs, and set the default type to uncached */
  37. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
  38. ctxt->deftype_hi);
  39. else if (is_cpu(CYRIX))
  40. /* Cyrix ARRs - everything else were excluded at the top */
  41. setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
  42. }
  43. /* Restore the processor after a set_mtrr_prepare */
  44. void set_mtrr_done(struct set_mtrr_context *ctxt)
  45. {
  46. if (use_intel() || is_cpu(CYRIX)) {
  47. /* Flush caches and TLBs */
  48. wbinvd();
  49. /* Restore MTRRdefType */
  50. if (use_intel())
  51. /* Intel (P6) standard MTRRs */
  52. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  53. else
  54. /* Cyrix ARRs - everything else was excluded at the top */
  55. setCx86(CX86_CCR3, ctxt->ccr3);
  56. /* Enable caches */
  57. write_cr0(read_cr0() & 0xbfffffff);
  58. /* Restore value of CR4 */
  59. if ( cpu_has_pge )
  60. write_cr4(ctxt->cr4val);
  61. }
  62. /* Re-enable interrupts locally (if enabled previously) */
  63. local_irq_restore(ctxt->flags);
  64. }