tlb-flush.S 4.3 KB

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  1. /* tlb-flush.S: TLB flushing routines
  2. *
  3. * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/sys.h>
  12. #include <linux/config.h>
  13. #include <linux/linkage.h>
  14. #include <asm/page.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/spr-regs.h>
  17. .macro DEBUG ch
  18. # sethi.p %hi(0xfeff9c00),gr4
  19. # setlo %lo(0xfeff9c00),gr4
  20. # setlos #\ch,gr5
  21. # stbi gr5,@(gr4,#0)
  22. # membar
  23. .endm
  24. .section .rodata
  25. # sizes corresponding to TPXR.LMAX
  26. .balign 1
  27. __tlb_lmax_sizes:
  28. .byte 0, 64, 0, 0
  29. .byte 0, 0, 0, 0
  30. .byte 0, 0, 0, 0
  31. .byte 0, 0, 0, 0
  32. .section .text
  33. .balign 4
  34. ###############################################################################
  35. #
  36. # flush everything
  37. # - void __flush_tlb_all(void)
  38. #
  39. ###############################################################################
  40. .globl __flush_tlb_all
  41. .type __flush_tlb_all,@function
  42. __flush_tlb_all:
  43. DEBUG 'A'
  44. # kill cached PGE value
  45. setlos #0xffffffff,gr4
  46. movgs gr4,scr0
  47. movgs gr4,scr1
  48. # kill AMPR-cached TLB values
  49. movgs gr0,iamlr1
  50. movgs gr0,iampr1
  51. movgs gr0,damlr1
  52. movgs gr0,dampr1
  53. # find out how many lines there are
  54. movsg tpxr,gr5
  55. sethi.p %hi(__tlb_lmax_sizes),gr4
  56. srli gr5,#TPXR_LMAX_SHIFT,gr5
  57. setlo.p %lo(__tlb_lmax_sizes),gr4
  58. andi gr5,#TPXR_LMAX_SMASK,gr5
  59. ldub @(gr4,gr5),gr4
  60. # now, we assume that the TLB line step is page size in size
  61. setlos.p #PAGE_SIZE,gr5
  62. setlos #0,gr6
  63. 1:
  64. tlbpr gr6,gr0,#6,#0
  65. subicc.p gr4,#1,gr4,icc0
  66. add gr6,gr5,gr6
  67. bne icc0,#2,1b
  68. DEBUG 'B'
  69. bralr
  70. .size __flush_tlb_all, .-__flush_tlb_all
  71. ###############################################################################
  72. #
  73. # flush everything to do with one context
  74. # - void __flush_tlb_mm(unsigned long contextid [GR8])
  75. #
  76. ###############################################################################
  77. .globl __flush_tlb_mm
  78. .type __flush_tlb_mm,@function
  79. __flush_tlb_mm:
  80. DEBUG 'M'
  81. # kill cached PGE value
  82. setlos #0xffffffff,gr4
  83. movgs gr4,scr0
  84. movgs gr4,scr1
  85. # specify the context we want to flush
  86. movgs gr8,tplr
  87. # find out how many lines there are
  88. movsg tpxr,gr5
  89. sethi.p %hi(__tlb_lmax_sizes),gr4
  90. srli gr5,#TPXR_LMAX_SHIFT,gr5
  91. setlo.p %lo(__tlb_lmax_sizes),gr4
  92. andi gr5,#TPXR_LMAX_SMASK,gr5
  93. ldub @(gr4,gr5),gr4
  94. # now, we assume that the TLB line step is page size in size
  95. setlos.p #PAGE_SIZE,gr5
  96. setlos #0,gr6
  97. 0:
  98. tlbpr gr6,gr0,#5,#0
  99. subicc.p gr4,#1,gr4,icc0
  100. add gr6,gr5,gr6
  101. bne icc0,#2,0b
  102. DEBUG 'N'
  103. bralr
  104. .size __flush_tlb_mm, .-__flush_tlb_mm
  105. ###############################################################################
  106. #
  107. # flush a range of addresses from the TLB
  108. # - void __flush_tlb_page(unsigned long contextid [GR8],
  109. # unsigned long start [GR9])
  110. #
  111. ###############################################################################
  112. .globl __flush_tlb_page
  113. .type __flush_tlb_page,@function
  114. __flush_tlb_page:
  115. # kill cached PGE value
  116. setlos #0xffffffff,gr4
  117. movgs gr4,scr0
  118. movgs gr4,scr1
  119. # specify the context we want to flush
  120. movgs gr8,tplr
  121. # zap the matching TLB line and AMR values
  122. setlos #~(PAGE_SIZE-1),gr5
  123. and gr9,gr5,gr9
  124. tlbpr gr9,gr0,#5,#0
  125. bralr
  126. .size __flush_tlb_page, .-__flush_tlb_page
  127. ###############################################################################
  128. #
  129. # flush a range of addresses from the TLB
  130. # - void __flush_tlb_range(unsigned long contextid [GR8],
  131. # unsigned long start [GR9],
  132. # unsigned long end [GR10])
  133. #
  134. ###############################################################################
  135. .globl __flush_tlb_range
  136. .type __flush_tlb_range,@function
  137. __flush_tlb_range:
  138. # kill cached PGE value
  139. setlos #0xffffffff,gr4
  140. movgs gr4,scr0
  141. movgs gr4,scr1
  142. # specify the context we want to flush
  143. movgs gr8,tplr
  144. # round the start down to beginning of TLB line and end up to beginning of next TLB line
  145. setlos.p #~(PAGE_SIZE-1),gr5
  146. setlos #PAGE_SIZE,gr6
  147. subi.p gr10,#1,gr10
  148. and gr9,gr5,gr9
  149. and gr10,gr5,gr10
  150. 2:
  151. tlbpr gr9,gr0,#5,#0
  152. subcc.p gr9,gr10,gr0,icc0
  153. add gr9,gr6,gr9
  154. bne icc0,#0,2b ; most likely a 1-page flush
  155. bralr
  156. .size __flush_tlb_range, .-__flush_tlb_range