s3c2440.c 6.4 KB

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  1. /* linux/arch/arm/mach-s3c2410/s3c2440.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Samsung S3C2440 Mobile CPU support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Modifications:
  13. * 24-Aug-2004 BJD Start of s3c2440 support
  14. * 12-Oct-2004 BJD Moved clock info out to clock.c
  15. * 01-Nov-2004 BJD Fixed clock build code
  16. * 09-Nov-2004 BJD Added sysdev for power management
  17. * 04-Nov-2004 BJD New serial registration
  18. * 15-Nov-2004 BJD Rename the i2c device for the s3c2440
  19. * 14-Jan-2005 BJD Moved clock init code into seperate function
  20. * 14-Jan-2005 BJD Removed un-used clock bits
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/list.h>
  26. #include <linux/timer.h>
  27. #include <linux/init.h>
  28. #include <linux/device.h>
  29. #include <linux/sysdev.h>
  30. #include <asm/mach/arch.h>
  31. #include <asm/mach/map.h>
  32. #include <asm/mach/irq.h>
  33. #include <asm/hardware.h>
  34. #include <asm/io.h>
  35. #include <asm/irq.h>
  36. #include <asm/hardware/clock.h>
  37. #include <asm/arch/regs-clock.h>
  38. #include <asm/arch/regs-serial.h>
  39. #include <asm/arch/regs-gpio.h>
  40. #include <asm/arch/regs-gpioj.h>
  41. #include <asm/arch/regs-dsc.h>
  42. #include "s3c2440.h"
  43. #include "clock.h"
  44. #include "devs.h"
  45. #include "cpu.h"
  46. #include "pm.h"
  47. static struct map_desc s3c2440_iodesc[] __initdata = {
  48. IODESC_ENT(USBHOST),
  49. IODESC_ENT(CLKPWR),
  50. IODESC_ENT(LCD),
  51. IODESC_ENT(TIMER),
  52. IODESC_ENT(ADC),
  53. IODESC_ENT(WATCHDOG),
  54. };
  55. static struct resource s3c_uart0_resource[] = {
  56. [0] = {
  57. .start = S3C2410_PA_UART0,
  58. .end = S3C2410_PA_UART0 + 0x3fff,
  59. .flags = IORESOURCE_MEM,
  60. },
  61. [1] = {
  62. .start = IRQ_S3CUART_RX0,
  63. .end = IRQ_S3CUART_ERR0,
  64. .flags = IORESOURCE_IRQ,
  65. }
  66. };
  67. static struct resource s3c_uart1_resource[] = {
  68. [0] = {
  69. .start = S3C2410_PA_UART1,
  70. .end = S3C2410_PA_UART1 + 0x3fff,
  71. .flags = IORESOURCE_MEM,
  72. },
  73. [1] = {
  74. .start = IRQ_S3CUART_RX1,
  75. .end = IRQ_S3CUART_ERR1,
  76. .flags = IORESOURCE_IRQ,
  77. }
  78. };
  79. static struct resource s3c_uart2_resource[] = {
  80. [0] = {
  81. .start = S3C2410_PA_UART2,
  82. .end = S3C2410_PA_UART2 + 0x3fff,
  83. .flags = IORESOURCE_MEM,
  84. },
  85. [1] = {
  86. .start = IRQ_S3CUART_RX2,
  87. .end = IRQ_S3CUART_ERR2,
  88. .flags = IORESOURCE_IRQ,
  89. }
  90. };
  91. /* our uart devices */
  92. static struct platform_device s3c_uart0 = {
  93. .name = "s3c2440-uart",
  94. .id = 0,
  95. .num_resources = ARRAY_SIZE(s3c_uart0_resource),
  96. .resource = s3c_uart0_resource,
  97. };
  98. static struct platform_device s3c_uart1 = {
  99. .name = "s3c2440-uart",
  100. .id = 1,
  101. .num_resources = ARRAY_SIZE(s3c_uart1_resource),
  102. .resource = s3c_uart1_resource,
  103. };
  104. static struct platform_device s3c_uart2 = {
  105. .name = "s3c2440-uart",
  106. .id = 2,
  107. .num_resources = ARRAY_SIZE(s3c_uart2_resource),
  108. .resource = s3c_uart2_resource,
  109. };
  110. static struct platform_device *uart_devices[] __initdata = {
  111. &s3c_uart0,
  112. &s3c_uart1,
  113. &s3c_uart2
  114. };
  115. /* uart initialisation */
  116. static int __initdata s3c2440_uart_count;
  117. void __init s3c2440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  118. {
  119. struct platform_device *platdev;
  120. int uart;
  121. for (uart = 0; uart < no; uart++, cfg++) {
  122. platdev = uart_devices[cfg->hwport];
  123. s3c24xx_uart_devs[uart] = platdev;
  124. platdev->dev.platform_data = cfg;
  125. }
  126. s3c2440_uart_count = uart;
  127. }
  128. #ifdef CONFIG_PM
  129. struct sleep_save s3c2440_sleep[] = {
  130. SAVE_ITEM(S3C2440_DSC0),
  131. SAVE_ITEM(S3C2440_DSC1),
  132. SAVE_ITEM(S3C2440_GPJDAT),
  133. SAVE_ITEM(S3C2440_GPJCON),
  134. SAVE_ITEM(S3C2440_GPJUP)
  135. };
  136. static int s3c2440_suspend(struct sys_device *dev, pm_message_t state)
  137. {
  138. s3c2410_pm_do_save(s3c2440_sleep, ARRAY_SIZE(s3c2440_sleep));
  139. return 0;
  140. }
  141. static int s3c2440_resume(struct sys_device *dev)
  142. {
  143. s3c2410_pm_do_restore(s3c2440_sleep, ARRAY_SIZE(s3c2440_sleep));
  144. return 0;
  145. }
  146. #else
  147. #define s3c2440_suspend NULL
  148. #define s3c2440_resume NULL
  149. #endif
  150. struct sysdev_class s3c2440_sysclass = {
  151. set_kset_name("s3c2440-core"),
  152. .suspend = s3c2440_suspend,
  153. .resume = s3c2440_resume
  154. };
  155. static struct sys_device s3c2440_sysdev = {
  156. .cls = &s3c2440_sysclass,
  157. };
  158. void __init s3c2440_map_io(struct map_desc *mach_desc, int size)
  159. {
  160. /* register our io-tables */
  161. iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc));
  162. iotable_init(mach_desc, size);
  163. /* rename any peripherals used differing from the s3c2410 */
  164. s3c_device_i2c.name = "s3c2440-i2c";
  165. s3c_device_nand.name = "s3c2440-nand";
  166. /* change irq for watchdog */
  167. s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
  168. s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
  169. }
  170. void __init s3c2440_init_clocks(int xtal)
  171. {
  172. unsigned long clkdiv;
  173. unsigned long camdiv;
  174. unsigned long hclk, fclk, pclk;
  175. int hdiv = 1;
  176. /* now we've got our machine bits initialised, work out what
  177. * clocks we've got */
  178. fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
  179. clkdiv = __raw_readl(S3C2410_CLKDIVN);
  180. camdiv = __raw_readl(S3C2440_CAMDIVN);
  181. /* work out clock scalings */
  182. switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
  183. case S3C2440_CLKDIVN_HDIVN_1:
  184. hdiv = 1;
  185. break;
  186. case S3C2440_CLKDIVN_HDIVN_2:
  187. hdiv = 2;
  188. break;
  189. case S3C2440_CLKDIVN_HDIVN_4_8:
  190. hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
  191. break;
  192. case S3C2440_CLKDIVN_HDIVN_3_6:
  193. hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
  194. break;
  195. }
  196. hclk = fclk / hdiv;
  197. pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
  198. /* print brief summary of clocks, etc */
  199. printk("S3C2440: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
  200. print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
  201. /* initialise the clocks here, to allow other things like the
  202. * console to use them, and to add new ones after the initialisation
  203. */
  204. s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
  205. }
  206. /* need to register class before we actually register the device, and
  207. * we also need to ensure that it has been initialised before any of the
  208. * drivers even try to use it (even if not on an s3c2440 based system)
  209. * as a driver which may support both 2410 and 2440 may try and use it.
  210. */
  211. int __init s3c2440_core_init(void)
  212. {
  213. return sysdev_class_register(&s3c2440_sysclass);
  214. }
  215. core_initcall(s3c2440_core_init);
  216. int __init s3c2440_init(void)
  217. {
  218. int ret;
  219. printk("S3C2440: Initialising architecture\n");
  220. ret = sysdev_register(&s3c2440_sysdev);
  221. if (ret != 0)
  222. printk(KERN_ERR "failed to register sysdev for s3c2440\n");
  223. else
  224. ret = platform_add_devices(s3c24xx_uart_devs, s3c2440_uart_count);
  225. return ret;
  226. }