irq.c 3.2 KB

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  1. #include <linux/init.h>
  2. #include <linux/list.h>
  3. #include <asm/mach/irq.h>
  4. #include <asm/hardware/iomd.h>
  5. #include <asm/irq.h>
  6. #include <asm/io.h>
  7. static void iomd_ack_irq_a(unsigned int irq)
  8. {
  9. unsigned int val, mask;
  10. mask = 1 << irq;
  11. val = iomd_readb(IOMD_IRQMASKA);
  12. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  13. iomd_writeb(mask, IOMD_IRQCLRA);
  14. }
  15. static void iomd_mask_irq_a(unsigned int irq)
  16. {
  17. unsigned int val, mask;
  18. mask = 1 << irq;
  19. val = iomd_readb(IOMD_IRQMASKA);
  20. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  21. }
  22. static void iomd_unmask_irq_a(unsigned int irq)
  23. {
  24. unsigned int val, mask;
  25. mask = 1 << irq;
  26. val = iomd_readb(IOMD_IRQMASKA);
  27. iomd_writeb(val | mask, IOMD_IRQMASKA);
  28. }
  29. static struct irqchip iomd_a_chip = {
  30. .ack = iomd_ack_irq_a,
  31. .mask = iomd_mask_irq_a,
  32. .unmask = iomd_unmask_irq_a,
  33. };
  34. static void iomd_mask_irq_b(unsigned int irq)
  35. {
  36. unsigned int val, mask;
  37. mask = 1 << (irq & 7);
  38. val = iomd_readb(IOMD_IRQMASKB);
  39. iomd_writeb(val & ~mask, IOMD_IRQMASKB);
  40. }
  41. static void iomd_unmask_irq_b(unsigned int irq)
  42. {
  43. unsigned int val, mask;
  44. mask = 1 << (irq & 7);
  45. val = iomd_readb(IOMD_IRQMASKB);
  46. iomd_writeb(val | mask, IOMD_IRQMASKB);
  47. }
  48. static struct irqchip iomd_b_chip = {
  49. .ack = iomd_mask_irq_b,
  50. .mask = iomd_mask_irq_b,
  51. .unmask = iomd_unmask_irq_b,
  52. };
  53. static void iomd_mask_irq_dma(unsigned int irq)
  54. {
  55. unsigned int val, mask;
  56. mask = 1 << (irq & 7);
  57. val = iomd_readb(IOMD_DMAMASK);
  58. iomd_writeb(val & ~mask, IOMD_DMAMASK);
  59. }
  60. static void iomd_unmask_irq_dma(unsigned int irq)
  61. {
  62. unsigned int val, mask;
  63. mask = 1 << (irq & 7);
  64. val = iomd_readb(IOMD_DMAMASK);
  65. iomd_writeb(val | mask, IOMD_DMAMASK);
  66. }
  67. static struct irqchip iomd_dma_chip = {
  68. .ack = iomd_mask_irq_dma,
  69. .mask = iomd_mask_irq_dma,
  70. .unmask = iomd_unmask_irq_dma,
  71. };
  72. static void iomd_mask_irq_fiq(unsigned int irq)
  73. {
  74. unsigned int val, mask;
  75. mask = 1 << (irq & 7);
  76. val = iomd_readb(IOMD_FIQMASK);
  77. iomd_writeb(val & ~mask, IOMD_FIQMASK);
  78. }
  79. static void iomd_unmask_irq_fiq(unsigned int irq)
  80. {
  81. unsigned int val, mask;
  82. mask = 1 << (irq & 7);
  83. val = iomd_readb(IOMD_FIQMASK);
  84. iomd_writeb(val | mask, IOMD_FIQMASK);
  85. }
  86. static struct irqchip iomd_fiq_chip = {
  87. .ack = iomd_mask_irq_fiq,
  88. .mask = iomd_mask_irq_fiq,
  89. .unmask = iomd_unmask_irq_fiq,
  90. };
  91. void __init rpc_init_irq(void)
  92. {
  93. unsigned int irq, flags;
  94. iomd_writeb(0, IOMD_IRQMASKA);
  95. iomd_writeb(0, IOMD_IRQMASKB);
  96. iomd_writeb(0, IOMD_FIQMASK);
  97. iomd_writeb(0, IOMD_DMAMASK);
  98. for (irq = 0; irq < NR_IRQS; irq++) {
  99. flags = IRQF_VALID;
  100. if (irq <= 6 || (irq >= 9 && irq <= 15))
  101. flags |= IRQF_PROBE;
  102. if (irq == 21 || (irq >= 16 && irq <= 19) ||
  103. irq == IRQ_KEYBOARDTX)
  104. flags |= IRQF_NOAUTOEN;
  105. switch (irq) {
  106. case 0 ... 7:
  107. set_irq_chip(irq, &iomd_a_chip);
  108. set_irq_handler(irq, do_level_IRQ);
  109. set_irq_flags(irq, flags);
  110. break;
  111. case 8 ... 15:
  112. set_irq_chip(irq, &iomd_b_chip);
  113. set_irq_handler(irq, do_level_IRQ);
  114. set_irq_flags(irq, flags);
  115. break;
  116. case 16 ... 21:
  117. set_irq_chip(irq, &iomd_dma_chip);
  118. set_irq_handler(irq, do_level_IRQ);
  119. set_irq_flags(irq, flags);
  120. break;
  121. case 64 ... 71:
  122. set_irq_chip(irq, &iomd_fiq_chip);
  123. set_irq_flags(irq, IRQF_VALID);
  124. break;
  125. }
  126. }
  127. init_FIQ();
  128. }