pxa27x.c 4.5 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/pxa27x.c
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: Nov 05, 2002
  6. * Copyright: MontaVista Software Inc.
  7. *
  8. * Code specific to PXA27x aka Bulverde.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/config.h>
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/pm.h>
  19. #include <linux/device.h>
  20. #include <asm/hardware.h>
  21. #include <asm/irq.h>
  22. #include <asm/arch/pxa-regs.h>
  23. #include "generic.h"
  24. /* Crystal clock: 13MHz */
  25. #define BASE_CLK 13000000
  26. /*
  27. * Get the clock frequency as reflected by CCSR and the turbo flag.
  28. * We assume these values have been applied via a fcs.
  29. * If info is not 0 we also display the current settings.
  30. */
  31. unsigned int get_clk_frequency_khz( int info)
  32. {
  33. unsigned long ccsr, clkcfg;
  34. unsigned int l, L, m, M, n2, N, S;
  35. int cccr_a, t, ht, b;
  36. ccsr = CCSR;
  37. cccr_a = CCCR & (1 << 25);
  38. /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  39. asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  40. t = clkcfg & (1 << 1);
  41. ht = clkcfg & (1 << 2);
  42. b = clkcfg & (1 << 3);
  43. l = ccsr & 0x1f;
  44. n2 = (ccsr>>7) & 0xf;
  45. m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  46. L = l * BASE_CLK;
  47. N = (L * n2) / 2;
  48. M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  49. S = (b) ? L : (L/2);
  50. if (info) {
  51. printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  52. L / 1000000, (L % 1000000) / 10000, l );
  53. printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  54. N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
  55. (t) ? "" : "in" );
  56. printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
  57. M / 1000000, (M % 1000000) / 10000, m );
  58. printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
  59. S / 1000000, (S % 1000000) / 10000 );
  60. }
  61. return (t) ? (N/1000) : (L/1000);
  62. }
  63. /*
  64. * Return the current mem clock frequency in units of 10kHz as
  65. * reflected by CCCR[A], B, and L
  66. */
  67. unsigned int get_memclk_frequency_10khz(void)
  68. {
  69. unsigned long ccsr, clkcfg;
  70. unsigned int l, L, m, M;
  71. int cccr_a, b;
  72. ccsr = CCSR;
  73. cccr_a = CCCR & (1 << 25);
  74. /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  75. asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  76. b = clkcfg & (1 << 3);
  77. l = ccsr & 0x1f;
  78. m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  79. L = l * BASE_CLK;
  80. M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  81. return (M / 10000);
  82. }
  83. /*
  84. * Return the current LCD clock frequency in units of 10kHz as
  85. */
  86. unsigned int get_lcdclk_frequency_10khz(void)
  87. {
  88. unsigned long ccsr;
  89. unsigned int l, L, k, K;
  90. ccsr = CCSR;
  91. l = ccsr & 0x1f;
  92. k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
  93. L = l * BASE_CLK;
  94. K = L / k;
  95. return (K / 10000);
  96. }
  97. EXPORT_SYMBOL(get_clk_frequency_khz);
  98. EXPORT_SYMBOL(get_memclk_frequency_10khz);
  99. EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
  100. #ifdef CONFIG_PM
  101. int pxa_cpu_pm_prepare(suspend_state_t state)
  102. {
  103. switch (state) {
  104. case PM_SUSPEND_MEM:
  105. case PM_SUSPEND_STANDBY:
  106. return 0;
  107. default:
  108. return -EINVAL;
  109. }
  110. }
  111. void pxa_cpu_pm_enter(suspend_state_t state)
  112. {
  113. extern void pxa_cpu_standby(void);
  114. extern void pxa_cpu_suspend(unsigned int);
  115. extern void pxa_cpu_resume(void);
  116. if (state == PM_SUSPEND_STANDBY)
  117. CKEN = CKEN22_MEMC | CKEN9_OSTIMER | CKEN16_LCD |CKEN0_PWM0;
  118. else
  119. CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
  120. /* ensure voltage-change sequencer not initiated, which hangs */
  121. PCFR &= ~PCFR_FVC;
  122. /* Clear edge-detect status register. */
  123. PEDR = 0xDF12FE1B;
  124. switch (state) {
  125. case PM_SUSPEND_STANDBY:
  126. pxa_cpu_standby();
  127. break;
  128. case PM_SUSPEND_MEM:
  129. /* set resume return address */
  130. PSPR = virt_to_phys(pxa_cpu_resume);
  131. pxa_cpu_suspend(3);
  132. break;
  133. }
  134. }
  135. #endif
  136. /*
  137. * device registration specific to PXA27x.
  138. */
  139. static u64 pxa27x_dmamask = 0xffffffffUL;
  140. static struct resource pxa27x_ohci_resources[] = {
  141. [0] = {
  142. .start = 0x4C000000,
  143. .end = 0x4C00ff6f,
  144. .flags = IORESOURCE_MEM,
  145. },
  146. [1] = {
  147. .start = IRQ_USBH1,
  148. .end = IRQ_USBH1,
  149. .flags = IORESOURCE_IRQ,
  150. },
  151. };
  152. static struct platform_device ohci_device = {
  153. .name = "pxa27x-ohci",
  154. .id = -1,
  155. .dev = {
  156. .dma_mask = &pxa27x_dmamask,
  157. .coherent_dma_mask = 0xffffffff,
  158. },
  159. .num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
  160. .resource = pxa27x_ohci_resources,
  161. };
  162. static struct platform_device *devices[] __initdata = {
  163. &ohci_device,
  164. };
  165. static int __init pxa27x_init(void)
  166. {
  167. return platform_add_devices(devices, ARRAY_SIZE(devices));
  168. }
  169. subsys_initcall(pxa27x_init);