qla_mbx.c 126 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval;
  34. unsigned long flags = 0;
  35. device_reg_t __iomem *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. unsigned long wait_time;
  44. struct qla_hw_data *ha = vha->hw;
  45. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  46. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  47. if (ha->pdev->error_state > pci_channel_io_frozen) {
  48. ql_log(ql_log_warn, vha, 0x1001,
  49. "error_state is greater than pci_channel_io_frozen, "
  50. "exiting.\n");
  51. return QLA_FUNCTION_TIMEOUT;
  52. }
  53. if (vha->device_flags & DFLG_DEV_FAILED) {
  54. ql_log(ql_log_warn, vha, 0x1002,
  55. "Device in failed state, exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. reg = ha->iobase;
  59. io_lock_on = base_vha->flags.init_done;
  60. rval = QLA_SUCCESS;
  61. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  62. if (ha->flags.pci_channel_io_perm_failure) {
  63. ql_log(ql_log_warn, vha, 0x1003,
  64. "Perm failure on EEH timeout MBX, exiting.\n");
  65. return QLA_FUNCTION_TIMEOUT;
  66. }
  67. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  68. /* Setting Link-Down error */
  69. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  70. ql_log(ql_log_warn, vha, 0x1004,
  71. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  72. return QLA_FUNCTION_TIMEOUT;
  73. }
  74. /*
  75. * Wait for active mailbox commands to finish by waiting at most tov
  76. * seconds. This is to serialize actual issuing of mailbox cmds during
  77. * non ISP abort time.
  78. */
  79. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  80. /* Timeout occurred. Return error. */
  81. ql_log(ql_log_warn, vha, 0x1005,
  82. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  83. mcp->mb[0]);
  84. return QLA_FUNCTION_TIMEOUT;
  85. }
  86. ha->flags.mbox_busy = 1;
  87. /* Save mailbox command for debug */
  88. ha->mcp = mcp;
  89. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  90. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  91. spin_lock_irqsave(&ha->hardware_lock, flags);
  92. /* Load mailbox registers. */
  93. if (IS_P3P_TYPE(ha))
  94. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  95. else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
  96. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  97. else
  98. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (IS_QLA2200(ha) && cnt == 8)
  104. optr =
  105. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  106. if (mboxes & BIT_0)
  107. WRT_REG_WORD(optr, *iptr);
  108. mboxes >>= 1;
  109. optr++;
  110. iptr++;
  111. }
  112. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  113. "Loaded MBX registers (displayed in bytes) =.\n");
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  115. (uint8_t *)mcp->mb, 16);
  116. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  117. ".\n");
  118. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  119. ((uint8_t *)mcp->mb + 0x10), 16);
  120. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  121. ".\n");
  122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  123. ((uint8_t *)mcp->mb + 0x20), 8);
  124. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  125. "I/O Address = %p.\n", optr);
  126. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  127. /* Issue set host interrupt command to send cmd out. */
  128. ha->flags.mbox_int = 0;
  129. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  130. /* Unlock mbx registers and wait for interrupt */
  131. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  132. "Going to unlock irq & waiting for interrupts. "
  133. "jiffies=%lx.\n", jiffies);
  134. /* Wait for mbx cmd completion until timeout */
  135. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  136. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  137. if (IS_P3P_TYPE(ha)) {
  138. if (RD_REG_DWORD(&reg->isp82.hint) &
  139. HINT_MBX_INT_PENDING) {
  140. spin_unlock_irqrestore(&ha->hardware_lock,
  141. flags);
  142. ha->flags.mbox_busy = 0;
  143. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  144. "Pending mailbox timeout, exiting.\n");
  145. rval = QLA_FUNCTION_TIMEOUT;
  146. goto premature_exit;
  147. }
  148. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  149. } else if (IS_FWI2_CAPABLE(ha))
  150. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  151. else
  152. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
  155. mcp->tov * HZ)) {
  156. ql_dbg(ql_dbg_mbx, vha, 0x117a,
  157. "cmd=%x Timeout.\n", command);
  158. spin_lock_irqsave(&ha->hardware_lock, flags);
  159. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  160. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  161. }
  162. } else {
  163. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  164. "Cmd=%x Polling Mode.\n", command);
  165. if (IS_P3P_TYPE(ha)) {
  166. if (RD_REG_DWORD(&reg->isp82.hint) &
  167. HINT_MBX_INT_PENDING) {
  168. spin_unlock_irqrestore(&ha->hardware_lock,
  169. flags);
  170. ha->flags.mbox_busy = 0;
  171. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  172. "Pending mailbox timeout, exiting.\n");
  173. rval = QLA_FUNCTION_TIMEOUT;
  174. goto premature_exit;
  175. }
  176. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  177. } else if (IS_FWI2_CAPABLE(ha))
  178. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  179. else
  180. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  181. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  182. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  183. while (!ha->flags.mbox_int) {
  184. if (time_after(jiffies, wait_time))
  185. break;
  186. /* Check for pending interrupts. */
  187. qla2x00_poll(ha->rsp_q_map[0]);
  188. if (!ha->flags.mbox_int &&
  189. !(IS_QLA2200(ha) &&
  190. command == MBC_LOAD_RISC_RAM_EXTENDED))
  191. msleep(10);
  192. } /* while */
  193. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  194. "Waited %d sec.\n",
  195. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  196. }
  197. /* Check whether we timed out */
  198. if (ha->flags.mbox_int) {
  199. uint16_t *iptr2;
  200. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  201. "Cmd=%x completed.\n", command);
  202. /* Got interrupt. Clear the flag. */
  203. ha->flags.mbox_int = 0;
  204. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  205. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  206. ha->flags.mbox_busy = 0;
  207. /* Setting Link-Down error */
  208. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  209. ha->mcp = NULL;
  210. rval = QLA_FUNCTION_FAILED;
  211. ql_log(ql_log_warn, vha, 0x1015,
  212. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  213. goto premature_exit;
  214. }
  215. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  216. rval = QLA_FUNCTION_FAILED;
  217. /* Load return mailbox registers. */
  218. iptr2 = mcp->mb;
  219. iptr = (uint16_t *)&ha->mailbox_out[0];
  220. mboxes = mcp->in_mb;
  221. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  222. if (mboxes & BIT_0)
  223. *iptr2 = *iptr;
  224. mboxes >>= 1;
  225. iptr2++;
  226. iptr++;
  227. }
  228. } else {
  229. uint16_t mb0;
  230. uint32_t ictrl;
  231. if (IS_FWI2_CAPABLE(ha)) {
  232. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  233. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  234. } else {
  235. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  236. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  237. }
  238. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  239. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  240. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  241. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  242. /*
  243. * Attempt to capture a firmware dump for further analysis
  244. * of the current firmware state. We do not need to do this
  245. * if we are intentionally generating a dump.
  246. */
  247. if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
  248. ha->isp_ops->fw_dump(vha, 0);
  249. rval = QLA_FUNCTION_TIMEOUT;
  250. }
  251. ha->flags.mbox_busy = 0;
  252. /* Clean up */
  253. ha->mcp = NULL;
  254. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  255. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  256. "Checking for additional resp interrupt.\n");
  257. /* polling mode for non isp_abort commands. */
  258. qla2x00_poll(ha->rsp_q_map[0]);
  259. }
  260. if (rval == QLA_FUNCTION_TIMEOUT &&
  261. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  262. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  263. ha->flags.eeh_busy) {
  264. /* not in dpc. schedule it for dpc to take over. */
  265. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  266. "Timeout, schedule isp_abort_needed.\n");
  267. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  268. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  269. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  270. if (IS_QLA82XX(ha)) {
  271. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  272. "disabling pause transmit on port "
  273. "0 & 1.\n");
  274. qla82xx_wr_32(ha,
  275. QLA82XX_CRB_NIU + 0x98,
  276. CRB_NIU_XG_PAUSE_CTL_P0|
  277. CRB_NIU_XG_PAUSE_CTL_P1);
  278. }
  279. ql_log(ql_log_info, base_vha, 0x101c,
  280. "Mailbox cmd timeout occurred, cmd=0x%x, "
  281. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  282. "abort.\n", command, mcp->mb[0],
  283. ha->flags.eeh_busy);
  284. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  285. qla2xxx_wake_dpc(vha);
  286. }
  287. } else if (!abort_active) {
  288. /* call abort directly since we are in the DPC thread */
  289. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  290. "Timeout, calling abort_isp.\n");
  291. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  292. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  293. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  294. if (IS_QLA82XX(ha)) {
  295. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  296. "disabling pause transmit on port "
  297. "0 & 1.\n");
  298. qla82xx_wr_32(ha,
  299. QLA82XX_CRB_NIU + 0x98,
  300. CRB_NIU_XG_PAUSE_CTL_P0|
  301. CRB_NIU_XG_PAUSE_CTL_P1);
  302. }
  303. ql_log(ql_log_info, base_vha, 0x101e,
  304. "Mailbox cmd timeout occurred, cmd=0x%x, "
  305. "mb[0]=0x%x. Scheduling ISP abort ",
  306. command, mcp->mb[0]);
  307. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  308. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  309. /* Allow next mbx cmd to come in. */
  310. complete(&ha->mbx_cmd_comp);
  311. if (ha->isp_ops->abort_isp(vha)) {
  312. /* Failed. retry later. */
  313. set_bit(ISP_ABORT_NEEDED,
  314. &vha->dpc_flags);
  315. }
  316. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  317. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  318. "Finished abort_isp.\n");
  319. goto mbx_done;
  320. }
  321. }
  322. }
  323. premature_exit:
  324. /* Allow next mbx cmd to come in. */
  325. complete(&ha->mbx_cmd_comp);
  326. mbx_done:
  327. if (rval) {
  328. ql_log(ql_log_warn, base_vha, 0x1020,
  329. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  330. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  331. } else {
  332. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  333. }
  334. return rval;
  335. }
  336. int
  337. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  338. uint32_t risc_code_size)
  339. {
  340. int rval;
  341. struct qla_hw_data *ha = vha->hw;
  342. mbx_cmd_t mc;
  343. mbx_cmd_t *mcp = &mc;
  344. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  345. "Entered %s.\n", __func__);
  346. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  347. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  348. mcp->mb[8] = MSW(risc_addr);
  349. mcp->out_mb = MBX_8|MBX_0;
  350. } else {
  351. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  352. mcp->out_mb = MBX_0;
  353. }
  354. mcp->mb[1] = LSW(risc_addr);
  355. mcp->mb[2] = MSW(req_dma);
  356. mcp->mb[3] = LSW(req_dma);
  357. mcp->mb[6] = MSW(MSD(req_dma));
  358. mcp->mb[7] = LSW(MSD(req_dma));
  359. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  360. if (IS_FWI2_CAPABLE(ha)) {
  361. mcp->mb[4] = MSW(risc_code_size);
  362. mcp->mb[5] = LSW(risc_code_size);
  363. mcp->out_mb |= MBX_5|MBX_4;
  364. } else {
  365. mcp->mb[4] = LSW(risc_code_size);
  366. mcp->out_mb |= MBX_4;
  367. }
  368. mcp->in_mb = MBX_0;
  369. mcp->tov = MBX_TOV_SECONDS;
  370. mcp->flags = 0;
  371. rval = qla2x00_mailbox_command(vha, mcp);
  372. if (rval != QLA_SUCCESS) {
  373. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  374. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  375. } else {
  376. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  377. "Done %s.\n", __func__);
  378. }
  379. return rval;
  380. }
  381. #define EXTENDED_BB_CREDITS BIT_0
  382. /*
  383. * qla2x00_execute_fw
  384. * Start adapter firmware.
  385. *
  386. * Input:
  387. * ha = adapter block pointer.
  388. * TARGET_QUEUE_LOCK must be released.
  389. * ADAPTER_STATE_LOCK must be released.
  390. *
  391. * Returns:
  392. * qla2x00 local function return status code.
  393. *
  394. * Context:
  395. * Kernel context.
  396. */
  397. int
  398. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  399. {
  400. int rval;
  401. struct qla_hw_data *ha = vha->hw;
  402. mbx_cmd_t mc;
  403. mbx_cmd_t *mcp = &mc;
  404. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  405. "Entered %s.\n", __func__);
  406. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  407. mcp->out_mb = MBX_0;
  408. mcp->in_mb = MBX_0;
  409. if (IS_FWI2_CAPABLE(ha)) {
  410. mcp->mb[1] = MSW(risc_addr);
  411. mcp->mb[2] = LSW(risc_addr);
  412. mcp->mb[3] = 0;
  413. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  414. struct nvram_81xx *nv = ha->nvram;
  415. mcp->mb[4] = (nv->enhanced_features &
  416. EXTENDED_BB_CREDITS);
  417. } else
  418. mcp->mb[4] = 0;
  419. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  420. mcp->in_mb |= MBX_1;
  421. } else {
  422. mcp->mb[1] = LSW(risc_addr);
  423. mcp->out_mb |= MBX_1;
  424. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  425. mcp->mb[2] = 0;
  426. mcp->out_mb |= MBX_2;
  427. }
  428. }
  429. mcp->tov = MBX_TOV_SECONDS;
  430. mcp->flags = 0;
  431. rval = qla2x00_mailbox_command(vha, mcp);
  432. if (rval != QLA_SUCCESS) {
  433. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  434. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  435. } else {
  436. if (IS_FWI2_CAPABLE(ha)) {
  437. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  438. "Done exchanges=%x.\n", mcp->mb[1]);
  439. } else {
  440. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  441. "Done %s.\n", __func__);
  442. }
  443. }
  444. return rval;
  445. }
  446. /*
  447. * qla2x00_get_fw_version
  448. * Get firmware version.
  449. *
  450. * Input:
  451. * ha: adapter state pointer.
  452. * major: pointer for major number.
  453. * minor: pointer for minor number.
  454. * subminor: pointer for subminor number.
  455. *
  456. * Returns:
  457. * qla2x00 local function return status code.
  458. *
  459. * Context:
  460. * Kernel context.
  461. */
  462. int
  463. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  464. {
  465. int rval;
  466. mbx_cmd_t mc;
  467. mbx_cmd_t *mcp = &mc;
  468. struct qla_hw_data *ha = vha->hw;
  469. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  470. "Entered %s.\n", __func__);
  471. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  472. mcp->out_mb = MBX_0;
  473. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  474. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
  475. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  476. if (IS_FWI2_CAPABLE(ha))
  477. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  478. mcp->flags = 0;
  479. mcp->tov = MBX_TOV_SECONDS;
  480. rval = qla2x00_mailbox_command(vha, mcp);
  481. if (rval != QLA_SUCCESS)
  482. goto failed;
  483. /* Return mailbox data. */
  484. ha->fw_major_version = mcp->mb[1];
  485. ha->fw_minor_version = mcp->mb[2];
  486. ha->fw_subminor_version = mcp->mb[3];
  487. ha->fw_attributes = mcp->mb[6];
  488. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  489. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  490. else
  491. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  492. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  493. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  494. ha->mpi_version[1] = mcp->mb[11] >> 8;
  495. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  496. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  497. ha->phy_version[0] = mcp->mb[8] & 0xff;
  498. ha->phy_version[1] = mcp->mb[9] >> 8;
  499. ha->phy_version[2] = mcp->mb[9] & 0xff;
  500. }
  501. if (IS_FWI2_CAPABLE(ha)) {
  502. ha->fw_attributes_h = mcp->mb[15];
  503. ha->fw_attributes_ext[0] = mcp->mb[16];
  504. ha->fw_attributes_ext[1] = mcp->mb[17];
  505. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  506. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  507. __func__, mcp->mb[15], mcp->mb[6]);
  508. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  509. "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
  510. __func__, mcp->mb[17], mcp->mb[16]);
  511. }
  512. failed:
  513. if (rval != QLA_SUCCESS) {
  514. /*EMPTY*/
  515. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  516. } else {
  517. /*EMPTY*/
  518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  519. "Done %s.\n", __func__);
  520. }
  521. return rval;
  522. }
  523. /*
  524. * qla2x00_get_fw_options
  525. * Set firmware options.
  526. *
  527. * Input:
  528. * ha = adapter block pointer.
  529. * fwopt = pointer for firmware options.
  530. *
  531. * Returns:
  532. * qla2x00 local function return status code.
  533. *
  534. * Context:
  535. * Kernel context.
  536. */
  537. int
  538. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  539. {
  540. int rval;
  541. mbx_cmd_t mc;
  542. mbx_cmd_t *mcp = &mc;
  543. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  544. "Entered %s.\n", __func__);
  545. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  546. mcp->out_mb = MBX_0;
  547. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  548. mcp->tov = MBX_TOV_SECONDS;
  549. mcp->flags = 0;
  550. rval = qla2x00_mailbox_command(vha, mcp);
  551. if (rval != QLA_SUCCESS) {
  552. /*EMPTY*/
  553. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  554. } else {
  555. fwopts[0] = mcp->mb[0];
  556. fwopts[1] = mcp->mb[1];
  557. fwopts[2] = mcp->mb[2];
  558. fwopts[3] = mcp->mb[3];
  559. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  560. "Done %s.\n", __func__);
  561. }
  562. return rval;
  563. }
  564. /*
  565. * qla2x00_set_fw_options
  566. * Set firmware options.
  567. *
  568. * Input:
  569. * ha = adapter block pointer.
  570. * fwopt = pointer for firmware options.
  571. *
  572. * Returns:
  573. * qla2x00 local function return status code.
  574. *
  575. * Context:
  576. * Kernel context.
  577. */
  578. int
  579. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  580. {
  581. int rval;
  582. mbx_cmd_t mc;
  583. mbx_cmd_t *mcp = &mc;
  584. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  585. "Entered %s.\n", __func__);
  586. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  587. mcp->mb[1] = fwopts[1];
  588. mcp->mb[2] = fwopts[2];
  589. mcp->mb[3] = fwopts[3];
  590. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  591. mcp->in_mb = MBX_0;
  592. if (IS_FWI2_CAPABLE(vha->hw)) {
  593. mcp->in_mb |= MBX_1;
  594. } else {
  595. mcp->mb[10] = fwopts[10];
  596. mcp->mb[11] = fwopts[11];
  597. mcp->mb[12] = 0; /* Undocumented, but used */
  598. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  599. }
  600. mcp->tov = MBX_TOV_SECONDS;
  601. mcp->flags = 0;
  602. rval = qla2x00_mailbox_command(vha, mcp);
  603. fwopts[0] = mcp->mb[0];
  604. if (rval != QLA_SUCCESS) {
  605. /*EMPTY*/
  606. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  607. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  608. } else {
  609. /*EMPTY*/
  610. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  611. "Done %s.\n", __func__);
  612. }
  613. return rval;
  614. }
  615. /*
  616. * qla2x00_mbx_reg_test
  617. * Mailbox register wrap test.
  618. *
  619. * Input:
  620. * ha = adapter block pointer.
  621. * TARGET_QUEUE_LOCK must be released.
  622. * ADAPTER_STATE_LOCK must be released.
  623. *
  624. * Returns:
  625. * qla2x00 local function return status code.
  626. *
  627. * Context:
  628. * Kernel context.
  629. */
  630. int
  631. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  632. {
  633. int rval;
  634. mbx_cmd_t mc;
  635. mbx_cmd_t *mcp = &mc;
  636. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  637. "Entered %s.\n", __func__);
  638. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  639. mcp->mb[1] = 0xAAAA;
  640. mcp->mb[2] = 0x5555;
  641. mcp->mb[3] = 0xAA55;
  642. mcp->mb[4] = 0x55AA;
  643. mcp->mb[5] = 0xA5A5;
  644. mcp->mb[6] = 0x5A5A;
  645. mcp->mb[7] = 0x2525;
  646. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  647. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  648. mcp->tov = MBX_TOV_SECONDS;
  649. mcp->flags = 0;
  650. rval = qla2x00_mailbox_command(vha, mcp);
  651. if (rval == QLA_SUCCESS) {
  652. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  653. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  654. rval = QLA_FUNCTION_FAILED;
  655. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  656. mcp->mb[7] != 0x2525)
  657. rval = QLA_FUNCTION_FAILED;
  658. }
  659. if (rval != QLA_SUCCESS) {
  660. /*EMPTY*/
  661. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  662. } else {
  663. /*EMPTY*/
  664. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  665. "Done %s.\n", __func__);
  666. }
  667. return rval;
  668. }
  669. /*
  670. * qla2x00_verify_checksum
  671. * Verify firmware checksum.
  672. *
  673. * Input:
  674. * ha = adapter block pointer.
  675. * TARGET_QUEUE_LOCK must be released.
  676. * ADAPTER_STATE_LOCK must be released.
  677. *
  678. * Returns:
  679. * qla2x00 local function return status code.
  680. *
  681. * Context:
  682. * Kernel context.
  683. */
  684. int
  685. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  686. {
  687. int rval;
  688. mbx_cmd_t mc;
  689. mbx_cmd_t *mcp = &mc;
  690. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  691. "Entered %s.\n", __func__);
  692. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  693. mcp->out_mb = MBX_0;
  694. mcp->in_mb = MBX_0;
  695. if (IS_FWI2_CAPABLE(vha->hw)) {
  696. mcp->mb[1] = MSW(risc_addr);
  697. mcp->mb[2] = LSW(risc_addr);
  698. mcp->out_mb |= MBX_2|MBX_1;
  699. mcp->in_mb |= MBX_2|MBX_1;
  700. } else {
  701. mcp->mb[1] = LSW(risc_addr);
  702. mcp->out_mb |= MBX_1;
  703. mcp->in_mb |= MBX_1;
  704. }
  705. mcp->tov = MBX_TOV_SECONDS;
  706. mcp->flags = 0;
  707. rval = qla2x00_mailbox_command(vha, mcp);
  708. if (rval != QLA_SUCCESS) {
  709. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  710. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  711. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  712. } else {
  713. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  714. "Done %s.\n", __func__);
  715. }
  716. return rval;
  717. }
  718. /*
  719. * qla2x00_issue_iocb
  720. * Issue IOCB using mailbox command
  721. *
  722. * Input:
  723. * ha = adapter state pointer.
  724. * buffer = buffer pointer.
  725. * phys_addr = physical address of buffer.
  726. * size = size of buffer.
  727. * TARGET_QUEUE_LOCK must be released.
  728. * ADAPTER_STATE_LOCK must be released.
  729. *
  730. * Returns:
  731. * qla2x00 local function return status code.
  732. *
  733. * Context:
  734. * Kernel context.
  735. */
  736. int
  737. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  738. dma_addr_t phys_addr, size_t size, uint32_t tov)
  739. {
  740. int rval;
  741. mbx_cmd_t mc;
  742. mbx_cmd_t *mcp = &mc;
  743. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  744. "Entered %s.\n", __func__);
  745. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  746. mcp->mb[1] = 0;
  747. mcp->mb[2] = MSW(phys_addr);
  748. mcp->mb[3] = LSW(phys_addr);
  749. mcp->mb[6] = MSW(MSD(phys_addr));
  750. mcp->mb[7] = LSW(MSD(phys_addr));
  751. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  752. mcp->in_mb = MBX_2|MBX_0;
  753. mcp->tov = tov;
  754. mcp->flags = 0;
  755. rval = qla2x00_mailbox_command(vha, mcp);
  756. if (rval != QLA_SUCCESS) {
  757. /*EMPTY*/
  758. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  759. } else {
  760. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  761. /* Mask reserved bits. */
  762. sts_entry->entry_status &=
  763. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  764. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  765. "Done %s.\n", __func__);
  766. }
  767. return rval;
  768. }
  769. int
  770. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  771. size_t size)
  772. {
  773. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  774. MBX_TOV_SECONDS);
  775. }
  776. /*
  777. * qla2x00_abort_command
  778. * Abort command aborts a specified IOCB.
  779. *
  780. * Input:
  781. * ha = adapter block pointer.
  782. * sp = SB structure pointer.
  783. *
  784. * Returns:
  785. * qla2x00 local function return status code.
  786. *
  787. * Context:
  788. * Kernel context.
  789. */
  790. int
  791. qla2x00_abort_command(srb_t *sp)
  792. {
  793. unsigned long flags = 0;
  794. int rval;
  795. uint32_t handle = 0;
  796. mbx_cmd_t mc;
  797. mbx_cmd_t *mcp = &mc;
  798. fc_port_t *fcport = sp->fcport;
  799. scsi_qla_host_t *vha = fcport->vha;
  800. struct qla_hw_data *ha = vha->hw;
  801. struct req_que *req = vha->req;
  802. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  803. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  804. "Entered %s.\n", __func__);
  805. spin_lock_irqsave(&ha->hardware_lock, flags);
  806. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  807. if (req->outstanding_cmds[handle] == sp)
  808. break;
  809. }
  810. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  811. if (handle == req->num_outstanding_cmds) {
  812. /* command not found */
  813. return QLA_FUNCTION_FAILED;
  814. }
  815. mcp->mb[0] = MBC_ABORT_COMMAND;
  816. if (HAS_EXTENDED_IDS(ha))
  817. mcp->mb[1] = fcport->loop_id;
  818. else
  819. mcp->mb[1] = fcport->loop_id << 8;
  820. mcp->mb[2] = (uint16_t)handle;
  821. mcp->mb[3] = (uint16_t)(handle >> 16);
  822. mcp->mb[6] = (uint16_t)cmd->device->lun;
  823. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  824. mcp->in_mb = MBX_0;
  825. mcp->tov = MBX_TOV_SECONDS;
  826. mcp->flags = 0;
  827. rval = qla2x00_mailbox_command(vha, mcp);
  828. if (rval != QLA_SUCCESS) {
  829. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  830. } else {
  831. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  832. "Done %s.\n", __func__);
  833. }
  834. return rval;
  835. }
  836. int
  837. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  838. {
  839. int rval, rval2;
  840. mbx_cmd_t mc;
  841. mbx_cmd_t *mcp = &mc;
  842. scsi_qla_host_t *vha;
  843. struct req_que *req;
  844. struct rsp_que *rsp;
  845. l = l;
  846. vha = fcport->vha;
  847. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  848. "Entered %s.\n", __func__);
  849. req = vha->hw->req_q_map[0];
  850. rsp = req->rsp;
  851. mcp->mb[0] = MBC_ABORT_TARGET;
  852. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  853. if (HAS_EXTENDED_IDS(vha->hw)) {
  854. mcp->mb[1] = fcport->loop_id;
  855. mcp->mb[10] = 0;
  856. mcp->out_mb |= MBX_10;
  857. } else {
  858. mcp->mb[1] = fcport->loop_id << 8;
  859. }
  860. mcp->mb[2] = vha->hw->loop_reset_delay;
  861. mcp->mb[9] = vha->vp_idx;
  862. mcp->in_mb = MBX_0;
  863. mcp->tov = MBX_TOV_SECONDS;
  864. mcp->flags = 0;
  865. rval = qla2x00_mailbox_command(vha, mcp);
  866. if (rval != QLA_SUCCESS) {
  867. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  868. "Failed=%x.\n", rval);
  869. }
  870. /* Issue marker IOCB. */
  871. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  872. MK_SYNC_ID);
  873. if (rval2 != QLA_SUCCESS) {
  874. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  875. "Failed to issue marker IOCB (%x).\n", rval2);
  876. } else {
  877. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  878. "Done %s.\n", __func__);
  879. }
  880. return rval;
  881. }
  882. int
  883. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  884. {
  885. int rval, rval2;
  886. mbx_cmd_t mc;
  887. mbx_cmd_t *mcp = &mc;
  888. scsi_qla_host_t *vha;
  889. struct req_que *req;
  890. struct rsp_que *rsp;
  891. vha = fcport->vha;
  892. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  893. "Entered %s.\n", __func__);
  894. req = vha->hw->req_q_map[0];
  895. rsp = req->rsp;
  896. mcp->mb[0] = MBC_LUN_RESET;
  897. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  898. if (HAS_EXTENDED_IDS(vha->hw))
  899. mcp->mb[1] = fcport->loop_id;
  900. else
  901. mcp->mb[1] = fcport->loop_id << 8;
  902. mcp->mb[2] = l;
  903. mcp->mb[3] = 0;
  904. mcp->mb[9] = vha->vp_idx;
  905. mcp->in_mb = MBX_0;
  906. mcp->tov = MBX_TOV_SECONDS;
  907. mcp->flags = 0;
  908. rval = qla2x00_mailbox_command(vha, mcp);
  909. if (rval != QLA_SUCCESS) {
  910. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  911. }
  912. /* Issue marker IOCB. */
  913. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  914. MK_SYNC_ID_LUN);
  915. if (rval2 != QLA_SUCCESS) {
  916. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  917. "Failed to issue marker IOCB (%x).\n", rval2);
  918. } else {
  919. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  920. "Done %s.\n", __func__);
  921. }
  922. return rval;
  923. }
  924. /*
  925. * qla2x00_get_adapter_id
  926. * Get adapter ID and topology.
  927. *
  928. * Input:
  929. * ha = adapter block pointer.
  930. * id = pointer for loop ID.
  931. * al_pa = pointer for AL_PA.
  932. * area = pointer for area.
  933. * domain = pointer for domain.
  934. * top = pointer for topology.
  935. * TARGET_QUEUE_LOCK must be released.
  936. * ADAPTER_STATE_LOCK must be released.
  937. *
  938. * Returns:
  939. * qla2x00 local function return status code.
  940. *
  941. * Context:
  942. * Kernel context.
  943. */
  944. int
  945. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  946. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  947. {
  948. int rval;
  949. mbx_cmd_t mc;
  950. mbx_cmd_t *mcp = &mc;
  951. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  952. "Entered %s.\n", __func__);
  953. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  954. mcp->mb[9] = vha->vp_idx;
  955. mcp->out_mb = MBX_9|MBX_0;
  956. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  957. if (IS_CNA_CAPABLE(vha->hw))
  958. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  959. mcp->tov = MBX_TOV_SECONDS;
  960. mcp->flags = 0;
  961. rval = qla2x00_mailbox_command(vha, mcp);
  962. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  963. rval = QLA_COMMAND_ERROR;
  964. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  965. rval = QLA_INVALID_COMMAND;
  966. /* Return data. */
  967. *id = mcp->mb[1];
  968. *al_pa = LSB(mcp->mb[2]);
  969. *area = MSB(mcp->mb[2]);
  970. *domain = LSB(mcp->mb[3]);
  971. *top = mcp->mb[6];
  972. *sw_cap = mcp->mb[7];
  973. if (rval != QLA_SUCCESS) {
  974. /*EMPTY*/
  975. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  976. } else {
  977. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  978. "Done %s.\n", __func__);
  979. if (IS_CNA_CAPABLE(vha->hw)) {
  980. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  981. vha->fcoe_fcf_idx = mcp->mb[10];
  982. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  983. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  984. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  985. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  986. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  987. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  988. }
  989. }
  990. return rval;
  991. }
  992. /*
  993. * qla2x00_get_retry_cnt
  994. * Get current firmware login retry count and delay.
  995. *
  996. * Input:
  997. * ha = adapter block pointer.
  998. * retry_cnt = pointer to login retry count.
  999. * tov = pointer to login timeout value.
  1000. *
  1001. * Returns:
  1002. * qla2x00 local function return status code.
  1003. *
  1004. * Context:
  1005. * Kernel context.
  1006. */
  1007. int
  1008. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1009. uint16_t *r_a_tov)
  1010. {
  1011. int rval;
  1012. uint16_t ratov;
  1013. mbx_cmd_t mc;
  1014. mbx_cmd_t *mcp = &mc;
  1015. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1016. "Entered %s.\n", __func__);
  1017. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1018. mcp->out_mb = MBX_0;
  1019. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1020. mcp->tov = MBX_TOV_SECONDS;
  1021. mcp->flags = 0;
  1022. rval = qla2x00_mailbox_command(vha, mcp);
  1023. if (rval != QLA_SUCCESS) {
  1024. /*EMPTY*/
  1025. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1026. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1027. } else {
  1028. /* Convert returned data and check our values. */
  1029. *r_a_tov = mcp->mb[3] / 2;
  1030. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1031. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1032. /* Update to the larger values */
  1033. *retry_cnt = (uint8_t)mcp->mb[1];
  1034. *tov = ratov;
  1035. }
  1036. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1037. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1038. }
  1039. return rval;
  1040. }
  1041. /*
  1042. * qla2x00_init_firmware
  1043. * Initialize adapter firmware.
  1044. *
  1045. * Input:
  1046. * ha = adapter block pointer.
  1047. * dptr = Initialization control block pointer.
  1048. * size = size of initialization control block.
  1049. * TARGET_QUEUE_LOCK must be released.
  1050. * ADAPTER_STATE_LOCK must be released.
  1051. *
  1052. * Returns:
  1053. * qla2x00 local function return status code.
  1054. *
  1055. * Context:
  1056. * Kernel context.
  1057. */
  1058. int
  1059. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1060. {
  1061. int rval;
  1062. mbx_cmd_t mc;
  1063. mbx_cmd_t *mcp = &mc;
  1064. struct qla_hw_data *ha = vha->hw;
  1065. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1066. "Entered %s.\n", __func__);
  1067. if (IS_P3P_TYPE(ha) && ql2xdbwr)
  1068. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1069. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1070. if (ha->flags.npiv_supported)
  1071. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1072. else
  1073. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1074. mcp->mb[1] = 0;
  1075. mcp->mb[2] = MSW(ha->init_cb_dma);
  1076. mcp->mb[3] = LSW(ha->init_cb_dma);
  1077. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1078. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1079. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1080. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1081. mcp->mb[1] = BIT_0;
  1082. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1083. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1084. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1085. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1086. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1087. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1088. }
  1089. /* 1 and 2 should normally be captured. */
  1090. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1091. if (IS_QLA83XX(ha))
  1092. /* mb3 is additional info about the installed SFP. */
  1093. mcp->in_mb |= MBX_3;
  1094. mcp->buf_size = size;
  1095. mcp->flags = MBX_DMA_OUT;
  1096. mcp->tov = MBX_TOV_SECONDS;
  1097. rval = qla2x00_mailbox_command(vha, mcp);
  1098. if (rval != QLA_SUCCESS) {
  1099. /*EMPTY*/
  1100. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1101. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1102. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1103. } else {
  1104. /*EMPTY*/
  1105. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1106. "Done %s.\n", __func__);
  1107. }
  1108. return rval;
  1109. }
  1110. /*
  1111. * qla2x00_get_node_name_list
  1112. * Issue get node name list mailbox command, kmalloc()
  1113. * and return the resulting list. Caller must kfree() it!
  1114. *
  1115. * Input:
  1116. * ha = adapter state pointer.
  1117. * out_data = resulting list
  1118. * out_len = length of the resulting list
  1119. *
  1120. * Returns:
  1121. * qla2x00 local function return status code.
  1122. *
  1123. * Context:
  1124. * Kernel context.
  1125. */
  1126. int
  1127. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1128. {
  1129. struct qla_hw_data *ha = vha->hw;
  1130. struct qla_port_24xx_data *list = NULL;
  1131. void *pmap;
  1132. mbx_cmd_t mc;
  1133. dma_addr_t pmap_dma;
  1134. ulong dma_size;
  1135. int rval, left;
  1136. left = 1;
  1137. while (left > 0) {
  1138. dma_size = left * sizeof(*list);
  1139. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1140. &pmap_dma, GFP_KERNEL);
  1141. if (!pmap) {
  1142. ql_log(ql_log_warn, vha, 0x113f,
  1143. "%s(%ld): DMA Alloc failed of %ld\n",
  1144. __func__, vha->host_no, dma_size);
  1145. rval = QLA_MEMORY_ALLOC_FAILED;
  1146. goto out;
  1147. }
  1148. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1149. mc.mb[1] = BIT_1 | BIT_3;
  1150. mc.mb[2] = MSW(pmap_dma);
  1151. mc.mb[3] = LSW(pmap_dma);
  1152. mc.mb[6] = MSW(MSD(pmap_dma));
  1153. mc.mb[7] = LSW(MSD(pmap_dma));
  1154. mc.mb[8] = dma_size;
  1155. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1156. mc.in_mb = MBX_0|MBX_1;
  1157. mc.tov = 30;
  1158. mc.flags = MBX_DMA_IN;
  1159. rval = qla2x00_mailbox_command(vha, &mc);
  1160. if (rval != QLA_SUCCESS) {
  1161. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1162. (mc.mb[1] == 0xA)) {
  1163. left += le16_to_cpu(mc.mb[2]) /
  1164. sizeof(struct qla_port_24xx_data);
  1165. goto restart;
  1166. }
  1167. goto out_free;
  1168. }
  1169. left = 0;
  1170. list = kzalloc(dma_size, GFP_KERNEL);
  1171. if (!list) {
  1172. ql_log(ql_log_warn, vha, 0x1140,
  1173. "%s(%ld): failed to allocate node names list "
  1174. "structure.\n", __func__, vha->host_no);
  1175. rval = QLA_MEMORY_ALLOC_FAILED;
  1176. goto out_free;
  1177. }
  1178. memcpy(list, pmap, dma_size);
  1179. restart:
  1180. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1181. }
  1182. *out_data = list;
  1183. *out_len = dma_size;
  1184. out:
  1185. return rval;
  1186. out_free:
  1187. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1188. return rval;
  1189. }
  1190. /*
  1191. * qla2x00_get_port_database
  1192. * Issue normal/enhanced get port database mailbox command
  1193. * and copy device name as necessary.
  1194. *
  1195. * Input:
  1196. * ha = adapter state pointer.
  1197. * dev = structure pointer.
  1198. * opt = enhanced cmd option byte.
  1199. *
  1200. * Returns:
  1201. * qla2x00 local function return status code.
  1202. *
  1203. * Context:
  1204. * Kernel context.
  1205. */
  1206. int
  1207. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1208. {
  1209. int rval;
  1210. mbx_cmd_t mc;
  1211. mbx_cmd_t *mcp = &mc;
  1212. port_database_t *pd;
  1213. struct port_database_24xx *pd24;
  1214. dma_addr_t pd_dma;
  1215. struct qla_hw_data *ha = vha->hw;
  1216. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1217. "Entered %s.\n", __func__);
  1218. pd24 = NULL;
  1219. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1220. if (pd == NULL) {
  1221. ql_log(ql_log_warn, vha, 0x1050,
  1222. "Failed to allocate port database structure.\n");
  1223. return QLA_MEMORY_ALLOC_FAILED;
  1224. }
  1225. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1226. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1227. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1228. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1229. mcp->mb[2] = MSW(pd_dma);
  1230. mcp->mb[3] = LSW(pd_dma);
  1231. mcp->mb[6] = MSW(MSD(pd_dma));
  1232. mcp->mb[7] = LSW(MSD(pd_dma));
  1233. mcp->mb[9] = vha->vp_idx;
  1234. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1235. mcp->in_mb = MBX_0;
  1236. if (IS_FWI2_CAPABLE(ha)) {
  1237. mcp->mb[1] = fcport->loop_id;
  1238. mcp->mb[10] = opt;
  1239. mcp->out_mb |= MBX_10|MBX_1;
  1240. mcp->in_mb |= MBX_1;
  1241. } else if (HAS_EXTENDED_IDS(ha)) {
  1242. mcp->mb[1] = fcport->loop_id;
  1243. mcp->mb[10] = opt;
  1244. mcp->out_mb |= MBX_10|MBX_1;
  1245. } else {
  1246. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1247. mcp->out_mb |= MBX_1;
  1248. }
  1249. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1250. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1251. mcp->flags = MBX_DMA_IN;
  1252. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1253. rval = qla2x00_mailbox_command(vha, mcp);
  1254. if (rval != QLA_SUCCESS)
  1255. goto gpd_error_out;
  1256. if (IS_FWI2_CAPABLE(ha)) {
  1257. uint64_t zero = 0;
  1258. pd24 = (struct port_database_24xx *) pd;
  1259. /* Check for logged in state. */
  1260. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1261. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1262. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1263. "Unable to verify login-state (%x/%x) for "
  1264. "loop_id %x.\n", pd24->current_login_state,
  1265. pd24->last_login_state, fcport->loop_id);
  1266. rval = QLA_FUNCTION_FAILED;
  1267. goto gpd_error_out;
  1268. }
  1269. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1270. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1271. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1272. /* We lost the device mid way. */
  1273. rval = QLA_NOT_LOGGED_IN;
  1274. goto gpd_error_out;
  1275. }
  1276. /* Names are little-endian. */
  1277. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1278. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1279. /* Get port_id of device. */
  1280. fcport->d_id.b.domain = pd24->port_id[0];
  1281. fcport->d_id.b.area = pd24->port_id[1];
  1282. fcport->d_id.b.al_pa = pd24->port_id[2];
  1283. fcport->d_id.b.rsvd_1 = 0;
  1284. /* If not target must be initiator or unknown type. */
  1285. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1286. fcport->port_type = FCT_INITIATOR;
  1287. else
  1288. fcport->port_type = FCT_TARGET;
  1289. /* Passback COS information. */
  1290. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1291. FC_COS_CLASS2 : FC_COS_CLASS3;
  1292. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1293. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1294. } else {
  1295. uint64_t zero = 0;
  1296. /* Check for logged in state. */
  1297. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1298. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1299. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1300. "Unable to verify login-state (%x/%x) - "
  1301. "portid=%02x%02x%02x.\n", pd->master_state,
  1302. pd->slave_state, fcport->d_id.b.domain,
  1303. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1304. rval = QLA_FUNCTION_FAILED;
  1305. goto gpd_error_out;
  1306. }
  1307. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1308. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1309. memcmp(fcport->port_name, pd->port_name, 8))) {
  1310. /* We lost the device mid way. */
  1311. rval = QLA_NOT_LOGGED_IN;
  1312. goto gpd_error_out;
  1313. }
  1314. /* Names are little-endian. */
  1315. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1316. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1317. /* Get port_id of device. */
  1318. fcport->d_id.b.domain = pd->port_id[0];
  1319. fcport->d_id.b.area = pd->port_id[3];
  1320. fcport->d_id.b.al_pa = pd->port_id[2];
  1321. fcport->d_id.b.rsvd_1 = 0;
  1322. /* If not target must be initiator or unknown type. */
  1323. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1324. fcport->port_type = FCT_INITIATOR;
  1325. else
  1326. fcport->port_type = FCT_TARGET;
  1327. /* Passback COS information. */
  1328. fcport->supported_classes = (pd->options & BIT_4) ?
  1329. FC_COS_CLASS2: FC_COS_CLASS3;
  1330. }
  1331. gpd_error_out:
  1332. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1333. if (rval != QLA_SUCCESS) {
  1334. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1335. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1336. mcp->mb[0], mcp->mb[1]);
  1337. } else {
  1338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1339. "Done %s.\n", __func__);
  1340. }
  1341. return rval;
  1342. }
  1343. /*
  1344. * qla2x00_get_firmware_state
  1345. * Get adapter firmware state.
  1346. *
  1347. * Input:
  1348. * ha = adapter block pointer.
  1349. * dptr = pointer for firmware state.
  1350. * TARGET_QUEUE_LOCK must be released.
  1351. * ADAPTER_STATE_LOCK must be released.
  1352. *
  1353. * Returns:
  1354. * qla2x00 local function return status code.
  1355. *
  1356. * Context:
  1357. * Kernel context.
  1358. */
  1359. int
  1360. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1361. {
  1362. int rval;
  1363. mbx_cmd_t mc;
  1364. mbx_cmd_t *mcp = &mc;
  1365. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1366. "Entered %s.\n", __func__);
  1367. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1368. mcp->out_mb = MBX_0;
  1369. if (IS_FWI2_CAPABLE(vha->hw))
  1370. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1371. else
  1372. mcp->in_mb = MBX_1|MBX_0;
  1373. mcp->tov = MBX_TOV_SECONDS;
  1374. mcp->flags = 0;
  1375. rval = qla2x00_mailbox_command(vha, mcp);
  1376. /* Return firmware states. */
  1377. states[0] = mcp->mb[1];
  1378. if (IS_FWI2_CAPABLE(vha->hw)) {
  1379. states[1] = mcp->mb[2];
  1380. states[2] = mcp->mb[3];
  1381. states[3] = mcp->mb[4];
  1382. states[4] = mcp->mb[5];
  1383. }
  1384. if (rval != QLA_SUCCESS) {
  1385. /*EMPTY*/
  1386. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1387. } else {
  1388. /*EMPTY*/
  1389. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1390. "Done %s.\n", __func__);
  1391. }
  1392. return rval;
  1393. }
  1394. /*
  1395. * qla2x00_get_port_name
  1396. * Issue get port name mailbox command.
  1397. * Returned name is in big endian format.
  1398. *
  1399. * Input:
  1400. * ha = adapter block pointer.
  1401. * loop_id = loop ID of device.
  1402. * name = pointer for name.
  1403. * TARGET_QUEUE_LOCK must be released.
  1404. * ADAPTER_STATE_LOCK must be released.
  1405. *
  1406. * Returns:
  1407. * qla2x00 local function return status code.
  1408. *
  1409. * Context:
  1410. * Kernel context.
  1411. */
  1412. int
  1413. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1414. uint8_t opt)
  1415. {
  1416. int rval;
  1417. mbx_cmd_t mc;
  1418. mbx_cmd_t *mcp = &mc;
  1419. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1420. "Entered %s.\n", __func__);
  1421. mcp->mb[0] = MBC_GET_PORT_NAME;
  1422. mcp->mb[9] = vha->vp_idx;
  1423. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1424. if (HAS_EXTENDED_IDS(vha->hw)) {
  1425. mcp->mb[1] = loop_id;
  1426. mcp->mb[10] = opt;
  1427. mcp->out_mb |= MBX_10;
  1428. } else {
  1429. mcp->mb[1] = loop_id << 8 | opt;
  1430. }
  1431. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1432. mcp->tov = MBX_TOV_SECONDS;
  1433. mcp->flags = 0;
  1434. rval = qla2x00_mailbox_command(vha, mcp);
  1435. if (rval != QLA_SUCCESS) {
  1436. /*EMPTY*/
  1437. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1438. } else {
  1439. if (name != NULL) {
  1440. /* This function returns name in big endian. */
  1441. name[0] = MSB(mcp->mb[2]);
  1442. name[1] = LSB(mcp->mb[2]);
  1443. name[2] = MSB(mcp->mb[3]);
  1444. name[3] = LSB(mcp->mb[3]);
  1445. name[4] = MSB(mcp->mb[6]);
  1446. name[5] = LSB(mcp->mb[6]);
  1447. name[6] = MSB(mcp->mb[7]);
  1448. name[7] = LSB(mcp->mb[7]);
  1449. }
  1450. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1451. "Done %s.\n", __func__);
  1452. }
  1453. return rval;
  1454. }
  1455. /*
  1456. * qla24xx_link_initialization
  1457. * Issue link initialization mailbox command.
  1458. *
  1459. * Input:
  1460. * ha = adapter block pointer.
  1461. * TARGET_QUEUE_LOCK must be released.
  1462. * ADAPTER_STATE_LOCK must be released.
  1463. *
  1464. * Returns:
  1465. * qla2x00 local function return status code.
  1466. *
  1467. * Context:
  1468. * Kernel context.
  1469. */
  1470. int
  1471. qla24xx_link_initialize(scsi_qla_host_t *vha)
  1472. {
  1473. int rval;
  1474. mbx_cmd_t mc;
  1475. mbx_cmd_t *mcp = &mc;
  1476. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
  1477. "Entered %s.\n", __func__);
  1478. if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
  1479. return QLA_FUNCTION_FAILED;
  1480. mcp->mb[0] = MBC_LINK_INITIALIZATION;
  1481. mcp->mb[1] = BIT_6|BIT_4;
  1482. mcp->mb[2] = 0;
  1483. mcp->mb[3] = 0;
  1484. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1485. mcp->in_mb = MBX_0;
  1486. mcp->tov = MBX_TOV_SECONDS;
  1487. mcp->flags = 0;
  1488. rval = qla2x00_mailbox_command(vha, mcp);
  1489. if (rval != QLA_SUCCESS) {
  1490. ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
  1491. } else {
  1492. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
  1493. "Done %s.\n", __func__);
  1494. }
  1495. return rval;
  1496. }
  1497. /*
  1498. * qla2x00_lip_reset
  1499. * Issue LIP reset mailbox command.
  1500. *
  1501. * Input:
  1502. * ha = adapter block pointer.
  1503. * TARGET_QUEUE_LOCK must be released.
  1504. * ADAPTER_STATE_LOCK must be released.
  1505. *
  1506. * Returns:
  1507. * qla2x00 local function return status code.
  1508. *
  1509. * Context:
  1510. * Kernel context.
  1511. */
  1512. int
  1513. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1514. {
  1515. int rval;
  1516. mbx_cmd_t mc;
  1517. mbx_cmd_t *mcp = &mc;
  1518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1519. "Entered %s.\n", __func__);
  1520. if (IS_CNA_CAPABLE(vha->hw)) {
  1521. /* Logout across all FCFs. */
  1522. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1523. mcp->mb[1] = BIT_1;
  1524. mcp->mb[2] = 0;
  1525. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1526. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1527. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1528. mcp->mb[1] = BIT_6;
  1529. mcp->mb[2] = 0;
  1530. mcp->mb[3] = vha->hw->loop_reset_delay;
  1531. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1532. } else {
  1533. mcp->mb[0] = MBC_LIP_RESET;
  1534. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1535. if (HAS_EXTENDED_IDS(vha->hw)) {
  1536. mcp->mb[1] = 0x00ff;
  1537. mcp->mb[10] = 0;
  1538. mcp->out_mb |= MBX_10;
  1539. } else {
  1540. mcp->mb[1] = 0xff00;
  1541. }
  1542. mcp->mb[2] = vha->hw->loop_reset_delay;
  1543. mcp->mb[3] = 0;
  1544. }
  1545. mcp->in_mb = MBX_0;
  1546. mcp->tov = MBX_TOV_SECONDS;
  1547. mcp->flags = 0;
  1548. rval = qla2x00_mailbox_command(vha, mcp);
  1549. if (rval != QLA_SUCCESS) {
  1550. /*EMPTY*/
  1551. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1552. } else {
  1553. /*EMPTY*/
  1554. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1555. "Done %s.\n", __func__);
  1556. }
  1557. return rval;
  1558. }
  1559. /*
  1560. * qla2x00_send_sns
  1561. * Send SNS command.
  1562. *
  1563. * Input:
  1564. * ha = adapter block pointer.
  1565. * sns = pointer for command.
  1566. * cmd_size = command size.
  1567. * buf_size = response/command size.
  1568. * TARGET_QUEUE_LOCK must be released.
  1569. * ADAPTER_STATE_LOCK must be released.
  1570. *
  1571. * Returns:
  1572. * qla2x00 local function return status code.
  1573. *
  1574. * Context:
  1575. * Kernel context.
  1576. */
  1577. int
  1578. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1579. uint16_t cmd_size, size_t buf_size)
  1580. {
  1581. int rval;
  1582. mbx_cmd_t mc;
  1583. mbx_cmd_t *mcp = &mc;
  1584. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1585. "Entered %s.\n", __func__);
  1586. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1587. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1588. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1589. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1590. mcp->mb[1] = cmd_size;
  1591. mcp->mb[2] = MSW(sns_phys_address);
  1592. mcp->mb[3] = LSW(sns_phys_address);
  1593. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1594. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1595. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1596. mcp->in_mb = MBX_0|MBX_1;
  1597. mcp->buf_size = buf_size;
  1598. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1599. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1600. rval = qla2x00_mailbox_command(vha, mcp);
  1601. if (rval != QLA_SUCCESS) {
  1602. /*EMPTY*/
  1603. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1604. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1605. rval, mcp->mb[0], mcp->mb[1]);
  1606. } else {
  1607. /*EMPTY*/
  1608. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1609. "Done %s.\n", __func__);
  1610. }
  1611. return rval;
  1612. }
  1613. int
  1614. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1615. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1616. {
  1617. int rval;
  1618. struct logio_entry_24xx *lg;
  1619. dma_addr_t lg_dma;
  1620. uint32_t iop[2];
  1621. struct qla_hw_data *ha = vha->hw;
  1622. struct req_que *req;
  1623. struct rsp_que *rsp;
  1624. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1625. "Entered %s.\n", __func__);
  1626. if (ha->flags.cpu_affinity_enabled)
  1627. req = ha->req_q_map[0];
  1628. else
  1629. req = vha->req;
  1630. rsp = req->rsp;
  1631. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1632. if (lg == NULL) {
  1633. ql_log(ql_log_warn, vha, 0x1062,
  1634. "Failed to allocate login IOCB.\n");
  1635. return QLA_MEMORY_ALLOC_FAILED;
  1636. }
  1637. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1638. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1639. lg->entry_count = 1;
  1640. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1641. lg->nport_handle = cpu_to_le16(loop_id);
  1642. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1643. if (opt & BIT_0)
  1644. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1645. if (opt & BIT_1)
  1646. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1647. lg->port_id[0] = al_pa;
  1648. lg->port_id[1] = area;
  1649. lg->port_id[2] = domain;
  1650. lg->vp_index = vha->vp_idx;
  1651. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1652. (ha->r_a_tov / 10 * 2) + 2);
  1653. if (rval != QLA_SUCCESS) {
  1654. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1655. "Failed to issue login IOCB (%x).\n", rval);
  1656. } else if (lg->entry_status != 0) {
  1657. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1658. "Failed to complete IOCB -- error status (%x).\n",
  1659. lg->entry_status);
  1660. rval = QLA_FUNCTION_FAILED;
  1661. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1662. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1663. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1664. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1665. "Failed to complete IOCB -- completion status (%x) "
  1666. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1667. iop[0], iop[1]);
  1668. switch (iop[0]) {
  1669. case LSC_SCODE_PORTID_USED:
  1670. mb[0] = MBS_PORT_ID_USED;
  1671. mb[1] = LSW(iop[1]);
  1672. break;
  1673. case LSC_SCODE_NPORT_USED:
  1674. mb[0] = MBS_LOOP_ID_USED;
  1675. break;
  1676. case LSC_SCODE_NOLINK:
  1677. case LSC_SCODE_NOIOCB:
  1678. case LSC_SCODE_NOXCB:
  1679. case LSC_SCODE_CMD_FAILED:
  1680. case LSC_SCODE_NOFABRIC:
  1681. case LSC_SCODE_FW_NOT_READY:
  1682. case LSC_SCODE_NOT_LOGGED_IN:
  1683. case LSC_SCODE_NOPCB:
  1684. case LSC_SCODE_ELS_REJECT:
  1685. case LSC_SCODE_CMD_PARAM_ERR:
  1686. case LSC_SCODE_NONPORT:
  1687. case LSC_SCODE_LOGGED_IN:
  1688. case LSC_SCODE_NOFLOGI_ACC:
  1689. default:
  1690. mb[0] = MBS_COMMAND_ERROR;
  1691. break;
  1692. }
  1693. } else {
  1694. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1695. "Done %s.\n", __func__);
  1696. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1697. mb[0] = MBS_COMMAND_COMPLETE;
  1698. mb[1] = 0;
  1699. if (iop[0] & BIT_4) {
  1700. if (iop[0] & BIT_8)
  1701. mb[1] |= BIT_1;
  1702. } else
  1703. mb[1] = BIT_0;
  1704. /* Passback COS information. */
  1705. mb[10] = 0;
  1706. if (lg->io_parameter[7] || lg->io_parameter[8])
  1707. mb[10] |= BIT_0; /* Class 2. */
  1708. if (lg->io_parameter[9] || lg->io_parameter[10])
  1709. mb[10] |= BIT_1; /* Class 3. */
  1710. if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
  1711. mb[10] |= BIT_7; /* Confirmed Completion
  1712. * Allowed
  1713. */
  1714. }
  1715. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1716. return rval;
  1717. }
  1718. /*
  1719. * qla2x00_login_fabric
  1720. * Issue login fabric port mailbox command.
  1721. *
  1722. * Input:
  1723. * ha = adapter block pointer.
  1724. * loop_id = device loop ID.
  1725. * domain = device domain.
  1726. * area = device area.
  1727. * al_pa = device AL_PA.
  1728. * status = pointer for return status.
  1729. * opt = command options.
  1730. * TARGET_QUEUE_LOCK must be released.
  1731. * ADAPTER_STATE_LOCK must be released.
  1732. *
  1733. * Returns:
  1734. * qla2x00 local function return status code.
  1735. *
  1736. * Context:
  1737. * Kernel context.
  1738. */
  1739. int
  1740. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1741. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1742. {
  1743. int rval;
  1744. mbx_cmd_t mc;
  1745. mbx_cmd_t *mcp = &mc;
  1746. struct qla_hw_data *ha = vha->hw;
  1747. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1748. "Entered %s.\n", __func__);
  1749. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1750. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1751. if (HAS_EXTENDED_IDS(ha)) {
  1752. mcp->mb[1] = loop_id;
  1753. mcp->mb[10] = opt;
  1754. mcp->out_mb |= MBX_10;
  1755. } else {
  1756. mcp->mb[1] = (loop_id << 8) | opt;
  1757. }
  1758. mcp->mb[2] = domain;
  1759. mcp->mb[3] = area << 8 | al_pa;
  1760. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1761. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1762. mcp->flags = 0;
  1763. rval = qla2x00_mailbox_command(vha, mcp);
  1764. /* Return mailbox statuses. */
  1765. if (mb != NULL) {
  1766. mb[0] = mcp->mb[0];
  1767. mb[1] = mcp->mb[1];
  1768. mb[2] = mcp->mb[2];
  1769. mb[6] = mcp->mb[6];
  1770. mb[7] = mcp->mb[7];
  1771. /* COS retrieved from Get-Port-Database mailbox command. */
  1772. mb[10] = 0;
  1773. }
  1774. if (rval != QLA_SUCCESS) {
  1775. /* RLU tmp code: need to change main mailbox_command function to
  1776. * return ok even when the mailbox completion value is not
  1777. * SUCCESS. The caller needs to be responsible to interpret
  1778. * the return values of this mailbox command if we're not
  1779. * to change too much of the existing code.
  1780. */
  1781. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1782. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1783. mcp->mb[0] == 0x4006)
  1784. rval = QLA_SUCCESS;
  1785. /*EMPTY*/
  1786. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1787. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1788. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1789. } else {
  1790. /*EMPTY*/
  1791. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1792. "Done %s.\n", __func__);
  1793. }
  1794. return rval;
  1795. }
  1796. /*
  1797. * qla2x00_login_local_device
  1798. * Issue login loop port mailbox command.
  1799. *
  1800. * Input:
  1801. * ha = adapter block pointer.
  1802. * loop_id = device loop ID.
  1803. * opt = command options.
  1804. *
  1805. * Returns:
  1806. * Return status code.
  1807. *
  1808. * Context:
  1809. * Kernel context.
  1810. *
  1811. */
  1812. int
  1813. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1814. uint16_t *mb_ret, uint8_t opt)
  1815. {
  1816. int rval;
  1817. mbx_cmd_t mc;
  1818. mbx_cmd_t *mcp = &mc;
  1819. struct qla_hw_data *ha = vha->hw;
  1820. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1821. "Entered %s.\n", __func__);
  1822. if (IS_FWI2_CAPABLE(ha))
  1823. return qla24xx_login_fabric(vha, fcport->loop_id,
  1824. fcport->d_id.b.domain, fcport->d_id.b.area,
  1825. fcport->d_id.b.al_pa, mb_ret, opt);
  1826. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1827. if (HAS_EXTENDED_IDS(ha))
  1828. mcp->mb[1] = fcport->loop_id;
  1829. else
  1830. mcp->mb[1] = fcport->loop_id << 8;
  1831. mcp->mb[2] = opt;
  1832. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1833. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1834. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1835. mcp->flags = 0;
  1836. rval = qla2x00_mailbox_command(vha, mcp);
  1837. /* Return mailbox statuses. */
  1838. if (mb_ret != NULL) {
  1839. mb_ret[0] = mcp->mb[0];
  1840. mb_ret[1] = mcp->mb[1];
  1841. mb_ret[6] = mcp->mb[6];
  1842. mb_ret[7] = mcp->mb[7];
  1843. }
  1844. if (rval != QLA_SUCCESS) {
  1845. /* AV tmp code: need to change main mailbox_command function to
  1846. * return ok even when the mailbox completion value is not
  1847. * SUCCESS. The caller needs to be responsible to interpret
  1848. * the return values of this mailbox command if we're not
  1849. * to change too much of the existing code.
  1850. */
  1851. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1852. rval = QLA_SUCCESS;
  1853. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1854. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1855. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1856. } else {
  1857. /*EMPTY*/
  1858. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1859. "Done %s.\n", __func__);
  1860. }
  1861. return (rval);
  1862. }
  1863. int
  1864. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1865. uint8_t area, uint8_t al_pa)
  1866. {
  1867. int rval;
  1868. struct logio_entry_24xx *lg;
  1869. dma_addr_t lg_dma;
  1870. struct qla_hw_data *ha = vha->hw;
  1871. struct req_que *req;
  1872. struct rsp_que *rsp;
  1873. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1874. "Entered %s.\n", __func__);
  1875. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1876. if (lg == NULL) {
  1877. ql_log(ql_log_warn, vha, 0x106e,
  1878. "Failed to allocate logout IOCB.\n");
  1879. return QLA_MEMORY_ALLOC_FAILED;
  1880. }
  1881. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1882. if (ql2xmaxqueues > 1)
  1883. req = ha->req_q_map[0];
  1884. else
  1885. req = vha->req;
  1886. rsp = req->rsp;
  1887. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1888. lg->entry_count = 1;
  1889. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1890. lg->nport_handle = cpu_to_le16(loop_id);
  1891. lg->control_flags =
  1892. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1893. LCF_FREE_NPORT);
  1894. lg->port_id[0] = al_pa;
  1895. lg->port_id[1] = area;
  1896. lg->port_id[2] = domain;
  1897. lg->vp_index = vha->vp_idx;
  1898. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1899. (ha->r_a_tov / 10 * 2) + 2);
  1900. if (rval != QLA_SUCCESS) {
  1901. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1902. "Failed to issue logout IOCB (%x).\n", rval);
  1903. } else if (lg->entry_status != 0) {
  1904. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1905. "Failed to complete IOCB -- error status (%x).\n",
  1906. lg->entry_status);
  1907. rval = QLA_FUNCTION_FAILED;
  1908. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1909. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1910. "Failed to complete IOCB -- completion status (%x) "
  1911. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1912. le32_to_cpu(lg->io_parameter[0]),
  1913. le32_to_cpu(lg->io_parameter[1]));
  1914. } else {
  1915. /*EMPTY*/
  1916. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1917. "Done %s.\n", __func__);
  1918. }
  1919. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1920. return rval;
  1921. }
  1922. /*
  1923. * qla2x00_fabric_logout
  1924. * Issue logout fabric port mailbox command.
  1925. *
  1926. * Input:
  1927. * ha = adapter block pointer.
  1928. * loop_id = device loop ID.
  1929. * TARGET_QUEUE_LOCK must be released.
  1930. * ADAPTER_STATE_LOCK must be released.
  1931. *
  1932. * Returns:
  1933. * qla2x00 local function return status code.
  1934. *
  1935. * Context:
  1936. * Kernel context.
  1937. */
  1938. int
  1939. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1940. uint8_t area, uint8_t al_pa)
  1941. {
  1942. int rval;
  1943. mbx_cmd_t mc;
  1944. mbx_cmd_t *mcp = &mc;
  1945. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1946. "Entered %s.\n", __func__);
  1947. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1948. mcp->out_mb = MBX_1|MBX_0;
  1949. if (HAS_EXTENDED_IDS(vha->hw)) {
  1950. mcp->mb[1] = loop_id;
  1951. mcp->mb[10] = 0;
  1952. mcp->out_mb |= MBX_10;
  1953. } else {
  1954. mcp->mb[1] = loop_id << 8;
  1955. }
  1956. mcp->in_mb = MBX_1|MBX_0;
  1957. mcp->tov = MBX_TOV_SECONDS;
  1958. mcp->flags = 0;
  1959. rval = qla2x00_mailbox_command(vha, mcp);
  1960. if (rval != QLA_SUCCESS) {
  1961. /*EMPTY*/
  1962. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1963. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1964. } else {
  1965. /*EMPTY*/
  1966. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1967. "Done %s.\n", __func__);
  1968. }
  1969. return rval;
  1970. }
  1971. /*
  1972. * qla2x00_full_login_lip
  1973. * Issue full login LIP mailbox command.
  1974. *
  1975. * Input:
  1976. * ha = adapter block pointer.
  1977. * TARGET_QUEUE_LOCK must be released.
  1978. * ADAPTER_STATE_LOCK must be released.
  1979. *
  1980. * Returns:
  1981. * qla2x00 local function return status code.
  1982. *
  1983. * Context:
  1984. * Kernel context.
  1985. */
  1986. int
  1987. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1988. {
  1989. int rval;
  1990. mbx_cmd_t mc;
  1991. mbx_cmd_t *mcp = &mc;
  1992. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1993. "Entered %s.\n", __func__);
  1994. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1995. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1996. mcp->mb[2] = 0;
  1997. mcp->mb[3] = 0;
  1998. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1999. mcp->in_mb = MBX_0;
  2000. mcp->tov = MBX_TOV_SECONDS;
  2001. mcp->flags = 0;
  2002. rval = qla2x00_mailbox_command(vha, mcp);
  2003. if (rval != QLA_SUCCESS) {
  2004. /*EMPTY*/
  2005. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  2006. } else {
  2007. /*EMPTY*/
  2008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  2009. "Done %s.\n", __func__);
  2010. }
  2011. return rval;
  2012. }
  2013. /*
  2014. * qla2x00_get_id_list
  2015. *
  2016. * Input:
  2017. * ha = adapter block pointer.
  2018. *
  2019. * Returns:
  2020. * qla2x00 local function return status code.
  2021. *
  2022. * Context:
  2023. * Kernel context.
  2024. */
  2025. int
  2026. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  2027. uint16_t *entries)
  2028. {
  2029. int rval;
  2030. mbx_cmd_t mc;
  2031. mbx_cmd_t *mcp = &mc;
  2032. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  2033. "Entered %s.\n", __func__);
  2034. if (id_list == NULL)
  2035. return QLA_FUNCTION_FAILED;
  2036. mcp->mb[0] = MBC_GET_ID_LIST;
  2037. mcp->out_mb = MBX_0;
  2038. if (IS_FWI2_CAPABLE(vha->hw)) {
  2039. mcp->mb[2] = MSW(id_list_dma);
  2040. mcp->mb[3] = LSW(id_list_dma);
  2041. mcp->mb[6] = MSW(MSD(id_list_dma));
  2042. mcp->mb[7] = LSW(MSD(id_list_dma));
  2043. mcp->mb[8] = 0;
  2044. mcp->mb[9] = vha->vp_idx;
  2045. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  2046. } else {
  2047. mcp->mb[1] = MSW(id_list_dma);
  2048. mcp->mb[2] = LSW(id_list_dma);
  2049. mcp->mb[3] = MSW(MSD(id_list_dma));
  2050. mcp->mb[6] = LSW(MSD(id_list_dma));
  2051. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2052. }
  2053. mcp->in_mb = MBX_1|MBX_0;
  2054. mcp->tov = MBX_TOV_SECONDS;
  2055. mcp->flags = 0;
  2056. rval = qla2x00_mailbox_command(vha, mcp);
  2057. if (rval != QLA_SUCCESS) {
  2058. /*EMPTY*/
  2059. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2060. } else {
  2061. *entries = mcp->mb[1];
  2062. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2063. "Done %s.\n", __func__);
  2064. }
  2065. return rval;
  2066. }
  2067. /*
  2068. * qla2x00_get_resource_cnts
  2069. * Get current firmware resource counts.
  2070. *
  2071. * Input:
  2072. * ha = adapter block pointer.
  2073. *
  2074. * Returns:
  2075. * qla2x00 local function return status code.
  2076. *
  2077. * Context:
  2078. * Kernel context.
  2079. */
  2080. int
  2081. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2082. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2083. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2084. {
  2085. int rval;
  2086. mbx_cmd_t mc;
  2087. mbx_cmd_t *mcp = &mc;
  2088. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2089. "Entered %s.\n", __func__);
  2090. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2091. mcp->out_mb = MBX_0;
  2092. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2093. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  2094. mcp->in_mb |= MBX_12;
  2095. mcp->tov = MBX_TOV_SECONDS;
  2096. mcp->flags = 0;
  2097. rval = qla2x00_mailbox_command(vha, mcp);
  2098. if (rval != QLA_SUCCESS) {
  2099. /*EMPTY*/
  2100. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2101. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2102. } else {
  2103. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2104. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2105. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2106. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2107. mcp->mb[11], mcp->mb[12]);
  2108. if (cur_xchg_cnt)
  2109. *cur_xchg_cnt = mcp->mb[3];
  2110. if (orig_xchg_cnt)
  2111. *orig_xchg_cnt = mcp->mb[6];
  2112. if (cur_iocb_cnt)
  2113. *cur_iocb_cnt = mcp->mb[7];
  2114. if (orig_iocb_cnt)
  2115. *orig_iocb_cnt = mcp->mb[10];
  2116. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2117. *max_npiv_vports = mcp->mb[11];
  2118. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  2119. *max_fcfs = mcp->mb[12];
  2120. }
  2121. return (rval);
  2122. }
  2123. /*
  2124. * qla2x00_get_fcal_position_map
  2125. * Get FCAL (LILP) position map using mailbox command
  2126. *
  2127. * Input:
  2128. * ha = adapter state pointer.
  2129. * pos_map = buffer pointer (can be NULL).
  2130. *
  2131. * Returns:
  2132. * qla2x00 local function return status code.
  2133. *
  2134. * Context:
  2135. * Kernel context.
  2136. */
  2137. int
  2138. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2139. {
  2140. int rval;
  2141. mbx_cmd_t mc;
  2142. mbx_cmd_t *mcp = &mc;
  2143. char *pmap;
  2144. dma_addr_t pmap_dma;
  2145. struct qla_hw_data *ha = vha->hw;
  2146. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2147. "Entered %s.\n", __func__);
  2148. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2149. if (pmap == NULL) {
  2150. ql_log(ql_log_warn, vha, 0x1080,
  2151. "Memory alloc failed.\n");
  2152. return QLA_MEMORY_ALLOC_FAILED;
  2153. }
  2154. memset(pmap, 0, FCAL_MAP_SIZE);
  2155. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2156. mcp->mb[2] = MSW(pmap_dma);
  2157. mcp->mb[3] = LSW(pmap_dma);
  2158. mcp->mb[6] = MSW(MSD(pmap_dma));
  2159. mcp->mb[7] = LSW(MSD(pmap_dma));
  2160. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2161. mcp->in_mb = MBX_1|MBX_0;
  2162. mcp->buf_size = FCAL_MAP_SIZE;
  2163. mcp->flags = MBX_DMA_IN;
  2164. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2165. rval = qla2x00_mailbox_command(vha, mcp);
  2166. if (rval == QLA_SUCCESS) {
  2167. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2168. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2169. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2170. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2171. pmap, pmap[0] + 1);
  2172. if (pos_map)
  2173. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2174. }
  2175. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2176. if (rval != QLA_SUCCESS) {
  2177. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2178. } else {
  2179. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2180. "Done %s.\n", __func__);
  2181. }
  2182. return rval;
  2183. }
  2184. /*
  2185. * qla2x00_get_link_status
  2186. *
  2187. * Input:
  2188. * ha = adapter block pointer.
  2189. * loop_id = device loop ID.
  2190. * ret_buf = pointer to link status return buffer.
  2191. *
  2192. * Returns:
  2193. * 0 = success.
  2194. * BIT_0 = mem alloc error.
  2195. * BIT_1 = mailbox error.
  2196. */
  2197. int
  2198. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2199. struct link_statistics *stats, dma_addr_t stats_dma)
  2200. {
  2201. int rval;
  2202. mbx_cmd_t mc;
  2203. mbx_cmd_t *mcp = &mc;
  2204. uint32_t *siter, *diter, dwords;
  2205. struct qla_hw_data *ha = vha->hw;
  2206. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2207. "Entered %s.\n", __func__);
  2208. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2209. mcp->mb[2] = MSW(stats_dma);
  2210. mcp->mb[3] = LSW(stats_dma);
  2211. mcp->mb[6] = MSW(MSD(stats_dma));
  2212. mcp->mb[7] = LSW(MSD(stats_dma));
  2213. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2214. mcp->in_mb = MBX_0;
  2215. if (IS_FWI2_CAPABLE(ha)) {
  2216. mcp->mb[1] = loop_id;
  2217. mcp->mb[4] = 0;
  2218. mcp->mb[10] = 0;
  2219. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2220. mcp->in_mb |= MBX_1;
  2221. } else if (HAS_EXTENDED_IDS(ha)) {
  2222. mcp->mb[1] = loop_id;
  2223. mcp->mb[10] = 0;
  2224. mcp->out_mb |= MBX_10|MBX_1;
  2225. } else {
  2226. mcp->mb[1] = loop_id << 8;
  2227. mcp->out_mb |= MBX_1;
  2228. }
  2229. mcp->tov = MBX_TOV_SECONDS;
  2230. mcp->flags = IOCTL_CMD;
  2231. rval = qla2x00_mailbox_command(vha, mcp);
  2232. if (rval == QLA_SUCCESS) {
  2233. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2234. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2235. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2236. rval = QLA_FUNCTION_FAILED;
  2237. } else {
  2238. /* Copy over data -- firmware data is LE. */
  2239. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2240. "Done %s.\n", __func__);
  2241. dwords = offsetof(struct link_statistics, unused1) / 4;
  2242. siter = diter = &stats->link_fail_cnt;
  2243. while (dwords--)
  2244. *diter++ = le32_to_cpu(*siter++);
  2245. }
  2246. } else {
  2247. /* Failed. */
  2248. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2249. }
  2250. return rval;
  2251. }
  2252. int
  2253. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2254. dma_addr_t stats_dma)
  2255. {
  2256. int rval;
  2257. mbx_cmd_t mc;
  2258. mbx_cmd_t *mcp = &mc;
  2259. uint32_t *siter, *diter, dwords;
  2260. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2261. "Entered %s.\n", __func__);
  2262. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2263. mcp->mb[2] = MSW(stats_dma);
  2264. mcp->mb[3] = LSW(stats_dma);
  2265. mcp->mb[6] = MSW(MSD(stats_dma));
  2266. mcp->mb[7] = LSW(MSD(stats_dma));
  2267. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2268. mcp->mb[9] = vha->vp_idx;
  2269. mcp->mb[10] = 0;
  2270. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2271. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2272. mcp->tov = MBX_TOV_SECONDS;
  2273. mcp->flags = IOCTL_CMD;
  2274. rval = qla2x00_mailbox_command(vha, mcp);
  2275. if (rval == QLA_SUCCESS) {
  2276. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2277. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2278. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2279. rval = QLA_FUNCTION_FAILED;
  2280. } else {
  2281. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2282. "Done %s.\n", __func__);
  2283. /* Copy over data -- firmware data is LE. */
  2284. dwords = sizeof(struct link_statistics) / 4;
  2285. siter = diter = &stats->link_fail_cnt;
  2286. while (dwords--)
  2287. *diter++ = le32_to_cpu(*siter++);
  2288. }
  2289. } else {
  2290. /* Failed. */
  2291. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2292. }
  2293. return rval;
  2294. }
  2295. int
  2296. qla24xx_abort_command(srb_t *sp)
  2297. {
  2298. int rval;
  2299. unsigned long flags = 0;
  2300. struct abort_entry_24xx *abt;
  2301. dma_addr_t abt_dma;
  2302. uint32_t handle;
  2303. fc_port_t *fcport = sp->fcport;
  2304. struct scsi_qla_host *vha = fcport->vha;
  2305. struct qla_hw_data *ha = vha->hw;
  2306. struct req_que *req = vha->req;
  2307. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2308. "Entered %s.\n", __func__);
  2309. spin_lock_irqsave(&ha->hardware_lock, flags);
  2310. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  2311. if (req->outstanding_cmds[handle] == sp)
  2312. break;
  2313. }
  2314. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2315. if (handle == req->num_outstanding_cmds) {
  2316. /* Command not found. */
  2317. return QLA_FUNCTION_FAILED;
  2318. }
  2319. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2320. if (abt == NULL) {
  2321. ql_log(ql_log_warn, vha, 0x108d,
  2322. "Failed to allocate abort IOCB.\n");
  2323. return QLA_MEMORY_ALLOC_FAILED;
  2324. }
  2325. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2326. abt->entry_type = ABORT_IOCB_TYPE;
  2327. abt->entry_count = 1;
  2328. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2329. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2330. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2331. abt->port_id[0] = fcport->d_id.b.al_pa;
  2332. abt->port_id[1] = fcport->d_id.b.area;
  2333. abt->port_id[2] = fcport->d_id.b.domain;
  2334. abt->vp_index = fcport->vha->vp_idx;
  2335. abt->req_que_no = cpu_to_le16(req->id);
  2336. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2337. if (rval != QLA_SUCCESS) {
  2338. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2339. "Failed to issue IOCB (%x).\n", rval);
  2340. } else if (abt->entry_status != 0) {
  2341. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2342. "Failed to complete IOCB -- error status (%x).\n",
  2343. abt->entry_status);
  2344. rval = QLA_FUNCTION_FAILED;
  2345. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2346. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2347. "Failed to complete IOCB -- completion status (%x).\n",
  2348. le16_to_cpu(abt->nport_handle));
  2349. rval = QLA_FUNCTION_FAILED;
  2350. } else {
  2351. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2352. "Done %s.\n", __func__);
  2353. }
  2354. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2355. return rval;
  2356. }
  2357. struct tsk_mgmt_cmd {
  2358. union {
  2359. struct tsk_mgmt_entry tsk;
  2360. struct sts_entry_24xx sts;
  2361. } p;
  2362. };
  2363. static int
  2364. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2365. unsigned int l, int tag)
  2366. {
  2367. int rval, rval2;
  2368. struct tsk_mgmt_cmd *tsk;
  2369. struct sts_entry_24xx *sts;
  2370. dma_addr_t tsk_dma;
  2371. scsi_qla_host_t *vha;
  2372. struct qla_hw_data *ha;
  2373. struct req_que *req;
  2374. struct rsp_que *rsp;
  2375. vha = fcport->vha;
  2376. ha = vha->hw;
  2377. req = vha->req;
  2378. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2379. "Entered %s.\n", __func__);
  2380. if (ha->flags.cpu_affinity_enabled)
  2381. rsp = ha->rsp_q_map[tag + 1];
  2382. else
  2383. rsp = req->rsp;
  2384. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2385. if (tsk == NULL) {
  2386. ql_log(ql_log_warn, vha, 0x1093,
  2387. "Failed to allocate task management IOCB.\n");
  2388. return QLA_MEMORY_ALLOC_FAILED;
  2389. }
  2390. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2391. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2392. tsk->p.tsk.entry_count = 1;
  2393. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2394. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2395. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2396. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2397. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2398. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2399. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2400. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2401. if (type == TCF_LUN_RESET) {
  2402. int_to_scsilun(l, &tsk->p.tsk.lun);
  2403. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2404. sizeof(tsk->p.tsk.lun));
  2405. }
  2406. sts = &tsk->p.sts;
  2407. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2408. if (rval != QLA_SUCCESS) {
  2409. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2410. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2411. } else if (sts->entry_status != 0) {
  2412. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2413. "Failed to complete IOCB -- error status (%x).\n",
  2414. sts->entry_status);
  2415. rval = QLA_FUNCTION_FAILED;
  2416. } else if (sts->comp_status !=
  2417. __constant_cpu_to_le16(CS_COMPLETE)) {
  2418. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2419. "Failed to complete IOCB -- completion status (%x).\n",
  2420. le16_to_cpu(sts->comp_status));
  2421. rval = QLA_FUNCTION_FAILED;
  2422. } else if (le16_to_cpu(sts->scsi_status) &
  2423. SS_RESPONSE_INFO_LEN_VALID) {
  2424. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2425. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2426. "Ignoring inconsistent data length -- not enough "
  2427. "response info (%d).\n",
  2428. le32_to_cpu(sts->rsp_data_len));
  2429. } else if (sts->data[3]) {
  2430. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2431. "Failed to complete IOCB -- response (%x).\n",
  2432. sts->data[3]);
  2433. rval = QLA_FUNCTION_FAILED;
  2434. }
  2435. }
  2436. /* Issue marker IOCB. */
  2437. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2438. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2439. if (rval2 != QLA_SUCCESS) {
  2440. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2441. "Failed to issue marker IOCB (%x).\n", rval2);
  2442. } else {
  2443. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2444. "Done %s.\n", __func__);
  2445. }
  2446. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2447. return rval;
  2448. }
  2449. int
  2450. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2451. {
  2452. struct qla_hw_data *ha = fcport->vha->hw;
  2453. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2454. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2455. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2456. }
  2457. int
  2458. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2459. {
  2460. struct qla_hw_data *ha = fcport->vha->hw;
  2461. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2462. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2463. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2464. }
  2465. int
  2466. qla2x00_system_error(scsi_qla_host_t *vha)
  2467. {
  2468. int rval;
  2469. mbx_cmd_t mc;
  2470. mbx_cmd_t *mcp = &mc;
  2471. struct qla_hw_data *ha = vha->hw;
  2472. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2473. return QLA_FUNCTION_FAILED;
  2474. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2475. "Entered %s.\n", __func__);
  2476. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2477. mcp->out_mb = MBX_0;
  2478. mcp->in_mb = MBX_0;
  2479. mcp->tov = 5;
  2480. mcp->flags = 0;
  2481. rval = qla2x00_mailbox_command(vha, mcp);
  2482. if (rval != QLA_SUCCESS) {
  2483. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2484. } else {
  2485. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2486. "Done %s.\n", __func__);
  2487. }
  2488. return rval;
  2489. }
  2490. /**
  2491. * qla2x00_set_serdes_params() -
  2492. * @ha: HA context
  2493. *
  2494. * Returns
  2495. */
  2496. int
  2497. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2498. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2499. {
  2500. int rval;
  2501. mbx_cmd_t mc;
  2502. mbx_cmd_t *mcp = &mc;
  2503. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2504. "Entered %s.\n", __func__);
  2505. mcp->mb[0] = MBC_SERDES_PARAMS;
  2506. mcp->mb[1] = BIT_0;
  2507. mcp->mb[2] = sw_em_1g | BIT_15;
  2508. mcp->mb[3] = sw_em_2g | BIT_15;
  2509. mcp->mb[4] = sw_em_4g | BIT_15;
  2510. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2511. mcp->in_mb = MBX_0;
  2512. mcp->tov = MBX_TOV_SECONDS;
  2513. mcp->flags = 0;
  2514. rval = qla2x00_mailbox_command(vha, mcp);
  2515. if (rval != QLA_SUCCESS) {
  2516. /*EMPTY*/
  2517. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2518. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2519. } else {
  2520. /*EMPTY*/
  2521. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2522. "Done %s.\n", __func__);
  2523. }
  2524. return rval;
  2525. }
  2526. int
  2527. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2528. {
  2529. int rval;
  2530. mbx_cmd_t mc;
  2531. mbx_cmd_t *mcp = &mc;
  2532. if (!IS_FWI2_CAPABLE(vha->hw))
  2533. return QLA_FUNCTION_FAILED;
  2534. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2535. "Entered %s.\n", __func__);
  2536. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2537. mcp->mb[1] = 0;
  2538. mcp->out_mb = MBX_1|MBX_0;
  2539. mcp->in_mb = MBX_0;
  2540. mcp->tov = 5;
  2541. mcp->flags = 0;
  2542. rval = qla2x00_mailbox_command(vha, mcp);
  2543. if (rval != QLA_SUCCESS) {
  2544. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2545. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2546. rval = QLA_INVALID_COMMAND;
  2547. } else {
  2548. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2549. "Done %s.\n", __func__);
  2550. }
  2551. return rval;
  2552. }
  2553. int
  2554. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2555. uint16_t buffers)
  2556. {
  2557. int rval;
  2558. mbx_cmd_t mc;
  2559. mbx_cmd_t *mcp = &mc;
  2560. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2561. "Entered %s.\n", __func__);
  2562. if (!IS_FWI2_CAPABLE(vha->hw))
  2563. return QLA_FUNCTION_FAILED;
  2564. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2565. return QLA_FUNCTION_FAILED;
  2566. mcp->mb[0] = MBC_TRACE_CONTROL;
  2567. mcp->mb[1] = TC_EFT_ENABLE;
  2568. mcp->mb[2] = LSW(eft_dma);
  2569. mcp->mb[3] = MSW(eft_dma);
  2570. mcp->mb[4] = LSW(MSD(eft_dma));
  2571. mcp->mb[5] = MSW(MSD(eft_dma));
  2572. mcp->mb[6] = buffers;
  2573. mcp->mb[7] = TC_AEN_DISABLE;
  2574. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2575. mcp->in_mb = MBX_1|MBX_0;
  2576. mcp->tov = MBX_TOV_SECONDS;
  2577. mcp->flags = 0;
  2578. rval = qla2x00_mailbox_command(vha, mcp);
  2579. if (rval != QLA_SUCCESS) {
  2580. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2581. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2582. rval, mcp->mb[0], mcp->mb[1]);
  2583. } else {
  2584. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2585. "Done %s.\n", __func__);
  2586. }
  2587. return rval;
  2588. }
  2589. int
  2590. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2591. {
  2592. int rval;
  2593. mbx_cmd_t mc;
  2594. mbx_cmd_t *mcp = &mc;
  2595. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2596. "Entered %s.\n", __func__);
  2597. if (!IS_FWI2_CAPABLE(vha->hw))
  2598. return QLA_FUNCTION_FAILED;
  2599. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2600. return QLA_FUNCTION_FAILED;
  2601. mcp->mb[0] = MBC_TRACE_CONTROL;
  2602. mcp->mb[1] = TC_EFT_DISABLE;
  2603. mcp->out_mb = MBX_1|MBX_0;
  2604. mcp->in_mb = MBX_1|MBX_0;
  2605. mcp->tov = MBX_TOV_SECONDS;
  2606. mcp->flags = 0;
  2607. rval = qla2x00_mailbox_command(vha, mcp);
  2608. if (rval != QLA_SUCCESS) {
  2609. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2610. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2611. rval, mcp->mb[0], mcp->mb[1]);
  2612. } else {
  2613. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2614. "Done %s.\n", __func__);
  2615. }
  2616. return rval;
  2617. }
  2618. int
  2619. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2620. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2621. {
  2622. int rval;
  2623. mbx_cmd_t mc;
  2624. mbx_cmd_t *mcp = &mc;
  2625. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2626. "Entered %s.\n", __func__);
  2627. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2628. !IS_QLA83XX(vha->hw))
  2629. return QLA_FUNCTION_FAILED;
  2630. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2631. return QLA_FUNCTION_FAILED;
  2632. mcp->mb[0] = MBC_TRACE_CONTROL;
  2633. mcp->mb[1] = TC_FCE_ENABLE;
  2634. mcp->mb[2] = LSW(fce_dma);
  2635. mcp->mb[3] = MSW(fce_dma);
  2636. mcp->mb[4] = LSW(MSD(fce_dma));
  2637. mcp->mb[5] = MSW(MSD(fce_dma));
  2638. mcp->mb[6] = buffers;
  2639. mcp->mb[7] = TC_AEN_DISABLE;
  2640. mcp->mb[8] = 0;
  2641. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2642. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2643. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2644. MBX_1|MBX_0;
  2645. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2646. mcp->tov = MBX_TOV_SECONDS;
  2647. mcp->flags = 0;
  2648. rval = qla2x00_mailbox_command(vha, mcp);
  2649. if (rval != QLA_SUCCESS) {
  2650. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2651. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2652. rval, mcp->mb[0], mcp->mb[1]);
  2653. } else {
  2654. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2655. "Done %s.\n", __func__);
  2656. if (mb)
  2657. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2658. if (dwords)
  2659. *dwords = buffers;
  2660. }
  2661. return rval;
  2662. }
  2663. int
  2664. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2665. {
  2666. int rval;
  2667. mbx_cmd_t mc;
  2668. mbx_cmd_t *mcp = &mc;
  2669. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2670. "Entered %s.\n", __func__);
  2671. if (!IS_FWI2_CAPABLE(vha->hw))
  2672. return QLA_FUNCTION_FAILED;
  2673. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2674. return QLA_FUNCTION_FAILED;
  2675. mcp->mb[0] = MBC_TRACE_CONTROL;
  2676. mcp->mb[1] = TC_FCE_DISABLE;
  2677. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2678. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2679. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2680. MBX_1|MBX_0;
  2681. mcp->tov = MBX_TOV_SECONDS;
  2682. mcp->flags = 0;
  2683. rval = qla2x00_mailbox_command(vha, mcp);
  2684. if (rval != QLA_SUCCESS) {
  2685. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2686. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2687. rval, mcp->mb[0], mcp->mb[1]);
  2688. } else {
  2689. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2690. "Done %s.\n", __func__);
  2691. if (wr)
  2692. *wr = (uint64_t) mcp->mb[5] << 48 |
  2693. (uint64_t) mcp->mb[4] << 32 |
  2694. (uint64_t) mcp->mb[3] << 16 |
  2695. (uint64_t) mcp->mb[2];
  2696. if (rd)
  2697. *rd = (uint64_t) mcp->mb[9] << 48 |
  2698. (uint64_t) mcp->mb[8] << 32 |
  2699. (uint64_t) mcp->mb[7] << 16 |
  2700. (uint64_t) mcp->mb[6];
  2701. }
  2702. return rval;
  2703. }
  2704. int
  2705. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2706. uint16_t *port_speed, uint16_t *mb)
  2707. {
  2708. int rval;
  2709. mbx_cmd_t mc;
  2710. mbx_cmd_t *mcp = &mc;
  2711. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2712. "Entered %s.\n", __func__);
  2713. if (!IS_IIDMA_CAPABLE(vha->hw))
  2714. return QLA_FUNCTION_FAILED;
  2715. mcp->mb[0] = MBC_PORT_PARAMS;
  2716. mcp->mb[1] = loop_id;
  2717. mcp->mb[2] = mcp->mb[3] = 0;
  2718. mcp->mb[9] = vha->vp_idx;
  2719. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2720. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2721. mcp->tov = MBX_TOV_SECONDS;
  2722. mcp->flags = 0;
  2723. rval = qla2x00_mailbox_command(vha, mcp);
  2724. /* Return mailbox statuses. */
  2725. if (mb != NULL) {
  2726. mb[0] = mcp->mb[0];
  2727. mb[1] = mcp->mb[1];
  2728. mb[3] = mcp->mb[3];
  2729. }
  2730. if (rval != QLA_SUCCESS) {
  2731. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2732. } else {
  2733. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2734. "Done %s.\n", __func__);
  2735. if (port_speed)
  2736. *port_speed = mcp->mb[3];
  2737. }
  2738. return rval;
  2739. }
  2740. int
  2741. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2742. uint16_t port_speed, uint16_t *mb)
  2743. {
  2744. int rval;
  2745. mbx_cmd_t mc;
  2746. mbx_cmd_t *mcp = &mc;
  2747. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2748. "Entered %s.\n", __func__);
  2749. if (!IS_IIDMA_CAPABLE(vha->hw))
  2750. return QLA_FUNCTION_FAILED;
  2751. mcp->mb[0] = MBC_PORT_PARAMS;
  2752. mcp->mb[1] = loop_id;
  2753. mcp->mb[2] = BIT_0;
  2754. if (IS_CNA_CAPABLE(vha->hw))
  2755. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2756. else
  2757. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2758. mcp->mb[9] = vha->vp_idx;
  2759. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2760. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2761. mcp->tov = MBX_TOV_SECONDS;
  2762. mcp->flags = 0;
  2763. rval = qla2x00_mailbox_command(vha, mcp);
  2764. /* Return mailbox statuses. */
  2765. if (mb != NULL) {
  2766. mb[0] = mcp->mb[0];
  2767. mb[1] = mcp->mb[1];
  2768. mb[3] = mcp->mb[3];
  2769. }
  2770. if (rval != QLA_SUCCESS) {
  2771. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2772. "Failed=%x.\n", rval);
  2773. } else {
  2774. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2775. "Done %s.\n", __func__);
  2776. }
  2777. return rval;
  2778. }
  2779. void
  2780. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2781. struct vp_rpt_id_entry_24xx *rptid_entry)
  2782. {
  2783. uint8_t vp_idx;
  2784. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2785. struct qla_hw_data *ha = vha->hw;
  2786. scsi_qla_host_t *vp;
  2787. unsigned long flags;
  2788. int found;
  2789. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2790. "Entered %s.\n", __func__);
  2791. if (rptid_entry->entry_status != 0)
  2792. return;
  2793. if (rptid_entry->format == 0) {
  2794. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2795. "Format 0 : Number of VPs setup %d, number of "
  2796. "VPs acquired %d.\n",
  2797. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2798. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2799. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2800. "Primary port id %02x%02x%02x.\n",
  2801. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2802. rptid_entry->port_id[0]);
  2803. } else if (rptid_entry->format == 1) {
  2804. vp_idx = LSB(stat);
  2805. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2806. "Format 1: VP[%d] enabled - status %d - with "
  2807. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2808. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2809. rptid_entry->port_id[0]);
  2810. vp = vha;
  2811. if (vp_idx == 0 && (MSB(stat) != 1))
  2812. goto reg_needed;
  2813. if (MSB(stat) != 0 && MSB(stat) != 2) {
  2814. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2815. "Could not acquire ID for VP[%d].\n", vp_idx);
  2816. return;
  2817. }
  2818. found = 0;
  2819. spin_lock_irqsave(&ha->vport_slock, flags);
  2820. list_for_each_entry(vp, &ha->vp_list, list) {
  2821. if (vp_idx == vp->vp_idx) {
  2822. found = 1;
  2823. break;
  2824. }
  2825. }
  2826. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2827. if (!found)
  2828. return;
  2829. vp->d_id.b.domain = rptid_entry->port_id[2];
  2830. vp->d_id.b.area = rptid_entry->port_id[1];
  2831. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2832. /*
  2833. * Cannot configure here as we are still sitting on the
  2834. * response queue. Handle it in dpc context.
  2835. */
  2836. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2837. reg_needed:
  2838. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2839. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2840. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2841. qla2xxx_wake_dpc(vha);
  2842. }
  2843. }
  2844. /*
  2845. * qla24xx_modify_vp_config
  2846. * Change VP configuration for vha
  2847. *
  2848. * Input:
  2849. * vha = adapter block pointer.
  2850. *
  2851. * Returns:
  2852. * qla2xxx local function return status code.
  2853. *
  2854. * Context:
  2855. * Kernel context.
  2856. */
  2857. int
  2858. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2859. {
  2860. int rval;
  2861. struct vp_config_entry_24xx *vpmod;
  2862. dma_addr_t vpmod_dma;
  2863. struct qla_hw_data *ha = vha->hw;
  2864. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2865. /* This can be called by the parent */
  2866. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2867. "Entered %s.\n", __func__);
  2868. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2869. if (!vpmod) {
  2870. ql_log(ql_log_warn, vha, 0x10bc,
  2871. "Failed to allocate modify VP IOCB.\n");
  2872. return QLA_MEMORY_ALLOC_FAILED;
  2873. }
  2874. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2875. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2876. vpmod->entry_count = 1;
  2877. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2878. vpmod->vp_count = 1;
  2879. vpmod->vp_index1 = vha->vp_idx;
  2880. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2881. qlt_modify_vp_config(vha, vpmod);
  2882. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2883. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2884. vpmod->entry_count = 1;
  2885. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2886. if (rval != QLA_SUCCESS) {
  2887. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2888. "Failed to issue VP config IOCB (%x).\n", rval);
  2889. } else if (vpmod->comp_status != 0) {
  2890. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2891. "Failed to complete IOCB -- error status (%x).\n",
  2892. vpmod->comp_status);
  2893. rval = QLA_FUNCTION_FAILED;
  2894. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2895. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2896. "Failed to complete IOCB -- completion status (%x).\n",
  2897. le16_to_cpu(vpmod->comp_status));
  2898. rval = QLA_FUNCTION_FAILED;
  2899. } else {
  2900. /* EMPTY */
  2901. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2902. "Done %s.\n", __func__);
  2903. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2904. }
  2905. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2906. return rval;
  2907. }
  2908. /*
  2909. * qla24xx_control_vp
  2910. * Enable a virtual port for given host
  2911. *
  2912. * Input:
  2913. * ha = adapter block pointer.
  2914. * vhba = virtual adapter (unused)
  2915. * index = index number for enabled VP
  2916. *
  2917. * Returns:
  2918. * qla2xxx local function return status code.
  2919. *
  2920. * Context:
  2921. * Kernel context.
  2922. */
  2923. int
  2924. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2925. {
  2926. int rval;
  2927. int map, pos;
  2928. struct vp_ctrl_entry_24xx *vce;
  2929. dma_addr_t vce_dma;
  2930. struct qla_hw_data *ha = vha->hw;
  2931. int vp_index = vha->vp_idx;
  2932. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2933. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2934. "Entered %s enabling index %d.\n", __func__, vp_index);
  2935. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2936. return QLA_PARAMETER_ERROR;
  2937. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2938. if (!vce) {
  2939. ql_log(ql_log_warn, vha, 0x10c2,
  2940. "Failed to allocate VP control IOCB.\n");
  2941. return QLA_MEMORY_ALLOC_FAILED;
  2942. }
  2943. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2944. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2945. vce->entry_count = 1;
  2946. vce->command = cpu_to_le16(cmd);
  2947. vce->vp_count = __constant_cpu_to_le16(1);
  2948. /* index map in firmware starts with 1; decrement index
  2949. * this is ok as we never use index 0
  2950. */
  2951. map = (vp_index - 1) / 8;
  2952. pos = (vp_index - 1) & 7;
  2953. mutex_lock(&ha->vport_lock);
  2954. vce->vp_idx_map[map] |= 1 << pos;
  2955. mutex_unlock(&ha->vport_lock);
  2956. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2957. if (rval != QLA_SUCCESS) {
  2958. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2959. "Failed to issue VP control IOCB (%x).\n", rval);
  2960. } else if (vce->entry_status != 0) {
  2961. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2962. "Failed to complete IOCB -- error status (%x).\n",
  2963. vce->entry_status);
  2964. rval = QLA_FUNCTION_FAILED;
  2965. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2966. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2967. "Failed to complet IOCB -- completion status (%x).\n",
  2968. le16_to_cpu(vce->comp_status));
  2969. rval = QLA_FUNCTION_FAILED;
  2970. } else {
  2971. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2972. "Done %s.\n", __func__);
  2973. }
  2974. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2975. return rval;
  2976. }
  2977. /*
  2978. * qla2x00_send_change_request
  2979. * Receive or disable RSCN request from fabric controller
  2980. *
  2981. * Input:
  2982. * ha = adapter block pointer
  2983. * format = registration format:
  2984. * 0 - Reserved
  2985. * 1 - Fabric detected registration
  2986. * 2 - N_port detected registration
  2987. * 3 - Full registration
  2988. * FF - clear registration
  2989. * vp_idx = Virtual port index
  2990. *
  2991. * Returns:
  2992. * qla2x00 local function return status code.
  2993. *
  2994. * Context:
  2995. * Kernel Context
  2996. */
  2997. int
  2998. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2999. uint16_t vp_idx)
  3000. {
  3001. int rval;
  3002. mbx_cmd_t mc;
  3003. mbx_cmd_t *mcp = &mc;
  3004. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  3005. "Entered %s.\n", __func__);
  3006. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  3007. mcp->mb[1] = format;
  3008. mcp->mb[9] = vp_idx;
  3009. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  3010. mcp->in_mb = MBX_0|MBX_1;
  3011. mcp->tov = MBX_TOV_SECONDS;
  3012. mcp->flags = 0;
  3013. rval = qla2x00_mailbox_command(vha, mcp);
  3014. if (rval == QLA_SUCCESS) {
  3015. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  3016. rval = BIT_1;
  3017. }
  3018. } else
  3019. rval = BIT_1;
  3020. return rval;
  3021. }
  3022. int
  3023. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  3024. uint32_t size)
  3025. {
  3026. int rval;
  3027. mbx_cmd_t mc;
  3028. mbx_cmd_t *mcp = &mc;
  3029. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  3030. "Entered %s.\n", __func__);
  3031. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  3032. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  3033. mcp->mb[8] = MSW(addr);
  3034. mcp->out_mb = MBX_8|MBX_0;
  3035. } else {
  3036. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  3037. mcp->out_mb = MBX_0;
  3038. }
  3039. mcp->mb[1] = LSW(addr);
  3040. mcp->mb[2] = MSW(req_dma);
  3041. mcp->mb[3] = LSW(req_dma);
  3042. mcp->mb[6] = MSW(MSD(req_dma));
  3043. mcp->mb[7] = LSW(MSD(req_dma));
  3044. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  3045. if (IS_FWI2_CAPABLE(vha->hw)) {
  3046. mcp->mb[4] = MSW(size);
  3047. mcp->mb[5] = LSW(size);
  3048. mcp->out_mb |= MBX_5|MBX_4;
  3049. } else {
  3050. mcp->mb[4] = LSW(size);
  3051. mcp->out_mb |= MBX_4;
  3052. }
  3053. mcp->in_mb = MBX_0;
  3054. mcp->tov = MBX_TOV_SECONDS;
  3055. mcp->flags = 0;
  3056. rval = qla2x00_mailbox_command(vha, mcp);
  3057. if (rval != QLA_SUCCESS) {
  3058. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3059. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3060. } else {
  3061. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3062. "Done %s.\n", __func__);
  3063. }
  3064. return rval;
  3065. }
  3066. /* 84XX Support **************************************************************/
  3067. struct cs84xx_mgmt_cmd {
  3068. union {
  3069. struct verify_chip_entry_84xx req;
  3070. struct verify_chip_rsp_84xx rsp;
  3071. } p;
  3072. };
  3073. int
  3074. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3075. {
  3076. int rval, retry;
  3077. struct cs84xx_mgmt_cmd *mn;
  3078. dma_addr_t mn_dma;
  3079. uint16_t options;
  3080. unsigned long flags;
  3081. struct qla_hw_data *ha = vha->hw;
  3082. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3083. "Entered %s.\n", __func__);
  3084. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3085. if (mn == NULL) {
  3086. return QLA_MEMORY_ALLOC_FAILED;
  3087. }
  3088. /* Force Update? */
  3089. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3090. /* Diagnostic firmware? */
  3091. /* options |= MENLO_DIAG_FW; */
  3092. /* We update the firmware with only one data sequence. */
  3093. options |= VCO_END_OF_DATA;
  3094. do {
  3095. retry = 0;
  3096. memset(mn, 0, sizeof(*mn));
  3097. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3098. mn->p.req.entry_count = 1;
  3099. mn->p.req.options = cpu_to_le16(options);
  3100. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3101. "Dump of Verify Request.\n");
  3102. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3103. (uint8_t *)mn, sizeof(*mn));
  3104. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3105. if (rval != QLA_SUCCESS) {
  3106. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3107. "Failed to issue verify IOCB (%x).\n", rval);
  3108. goto verify_done;
  3109. }
  3110. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3111. "Dump of Verify Response.\n");
  3112. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3113. (uint8_t *)mn, sizeof(*mn));
  3114. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3115. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3116. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3117. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3118. "cs=%x fc=%x.\n", status[0], status[1]);
  3119. if (status[0] != CS_COMPLETE) {
  3120. rval = QLA_FUNCTION_FAILED;
  3121. if (!(options & VCO_DONT_UPDATE_FW)) {
  3122. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3123. "Firmware update failed. Retrying "
  3124. "without update firmware.\n");
  3125. options |= VCO_DONT_UPDATE_FW;
  3126. options &= ~VCO_FORCE_UPDATE;
  3127. retry = 1;
  3128. }
  3129. } else {
  3130. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3131. "Firmware updated to %x.\n",
  3132. le32_to_cpu(mn->p.rsp.fw_ver));
  3133. /* NOTE: we only update OP firmware. */
  3134. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3135. ha->cs84xx->op_fw_version =
  3136. le32_to_cpu(mn->p.rsp.fw_ver);
  3137. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3138. flags);
  3139. }
  3140. } while (retry);
  3141. verify_done:
  3142. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3143. if (rval != QLA_SUCCESS) {
  3144. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3145. "Failed=%x.\n", rval);
  3146. } else {
  3147. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3148. "Done %s.\n", __func__);
  3149. }
  3150. return rval;
  3151. }
  3152. int
  3153. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3154. {
  3155. int rval;
  3156. unsigned long flags;
  3157. mbx_cmd_t mc;
  3158. mbx_cmd_t *mcp = &mc;
  3159. struct qla_hw_data *ha = vha->hw;
  3160. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3161. "Entered %s.\n", __func__);
  3162. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3163. mcp->mb[1] = req->options;
  3164. mcp->mb[2] = MSW(LSD(req->dma));
  3165. mcp->mb[3] = LSW(LSD(req->dma));
  3166. mcp->mb[6] = MSW(MSD(req->dma));
  3167. mcp->mb[7] = LSW(MSD(req->dma));
  3168. mcp->mb[5] = req->length;
  3169. if (req->rsp)
  3170. mcp->mb[10] = req->rsp->id;
  3171. mcp->mb[12] = req->qos;
  3172. mcp->mb[11] = req->vp_idx;
  3173. mcp->mb[13] = req->rid;
  3174. if (IS_QLA83XX(ha))
  3175. mcp->mb[15] = 0;
  3176. mcp->mb[4] = req->id;
  3177. /* que in ptr index */
  3178. mcp->mb[8] = 0;
  3179. /* que out ptr index */
  3180. mcp->mb[9] = 0;
  3181. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3182. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3183. mcp->in_mb = MBX_0;
  3184. mcp->flags = MBX_DMA_OUT;
  3185. mcp->tov = MBX_TOV_SECONDS * 2;
  3186. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3187. mcp->in_mb |= MBX_1;
  3188. if (IS_QLA83XX(ha)) {
  3189. mcp->out_mb |= MBX_15;
  3190. /* debug q create issue in SR-IOV */
  3191. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3192. }
  3193. spin_lock_irqsave(&ha->hardware_lock, flags);
  3194. if (!(req->options & BIT_0)) {
  3195. WRT_REG_DWORD(req->req_q_in, 0);
  3196. if (!IS_QLA83XX(ha))
  3197. WRT_REG_DWORD(req->req_q_out, 0);
  3198. }
  3199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3200. rval = qla2x00_mailbox_command(vha, mcp);
  3201. if (rval != QLA_SUCCESS) {
  3202. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3203. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3204. } else {
  3205. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3206. "Done %s.\n", __func__);
  3207. }
  3208. return rval;
  3209. }
  3210. int
  3211. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3212. {
  3213. int rval;
  3214. unsigned long flags;
  3215. mbx_cmd_t mc;
  3216. mbx_cmd_t *mcp = &mc;
  3217. struct qla_hw_data *ha = vha->hw;
  3218. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3219. "Entered %s.\n", __func__);
  3220. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3221. mcp->mb[1] = rsp->options;
  3222. mcp->mb[2] = MSW(LSD(rsp->dma));
  3223. mcp->mb[3] = LSW(LSD(rsp->dma));
  3224. mcp->mb[6] = MSW(MSD(rsp->dma));
  3225. mcp->mb[7] = LSW(MSD(rsp->dma));
  3226. mcp->mb[5] = rsp->length;
  3227. mcp->mb[14] = rsp->msix->entry;
  3228. mcp->mb[13] = rsp->rid;
  3229. if (IS_QLA83XX(ha))
  3230. mcp->mb[15] = 0;
  3231. mcp->mb[4] = rsp->id;
  3232. /* que in ptr index */
  3233. mcp->mb[8] = 0;
  3234. /* que out ptr index */
  3235. mcp->mb[9] = 0;
  3236. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3237. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3238. mcp->in_mb = MBX_0;
  3239. mcp->flags = MBX_DMA_OUT;
  3240. mcp->tov = MBX_TOV_SECONDS * 2;
  3241. if (IS_QLA81XX(ha)) {
  3242. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3243. mcp->in_mb |= MBX_1;
  3244. } else if (IS_QLA83XX(ha)) {
  3245. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3246. mcp->in_mb |= MBX_1;
  3247. /* debug q create issue in SR-IOV */
  3248. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3249. }
  3250. spin_lock_irqsave(&ha->hardware_lock, flags);
  3251. if (!(rsp->options & BIT_0)) {
  3252. WRT_REG_DWORD(rsp->rsp_q_out, 0);
  3253. if (!IS_QLA83XX(ha))
  3254. WRT_REG_DWORD(rsp->rsp_q_in, 0);
  3255. }
  3256. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3257. rval = qla2x00_mailbox_command(vha, mcp);
  3258. if (rval != QLA_SUCCESS) {
  3259. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3260. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3261. } else {
  3262. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3263. "Done %s.\n", __func__);
  3264. }
  3265. return rval;
  3266. }
  3267. int
  3268. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3269. {
  3270. int rval;
  3271. mbx_cmd_t mc;
  3272. mbx_cmd_t *mcp = &mc;
  3273. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3274. "Entered %s.\n", __func__);
  3275. mcp->mb[0] = MBC_IDC_ACK;
  3276. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3277. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3278. mcp->in_mb = MBX_0;
  3279. mcp->tov = MBX_TOV_SECONDS;
  3280. mcp->flags = 0;
  3281. rval = qla2x00_mailbox_command(vha, mcp);
  3282. if (rval != QLA_SUCCESS) {
  3283. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3284. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3285. } else {
  3286. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3287. "Done %s.\n", __func__);
  3288. }
  3289. return rval;
  3290. }
  3291. int
  3292. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3293. {
  3294. int rval;
  3295. mbx_cmd_t mc;
  3296. mbx_cmd_t *mcp = &mc;
  3297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3298. "Entered %s.\n", __func__);
  3299. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3300. return QLA_FUNCTION_FAILED;
  3301. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3302. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3303. mcp->out_mb = MBX_1|MBX_0;
  3304. mcp->in_mb = MBX_1|MBX_0;
  3305. mcp->tov = MBX_TOV_SECONDS;
  3306. mcp->flags = 0;
  3307. rval = qla2x00_mailbox_command(vha, mcp);
  3308. if (rval != QLA_SUCCESS) {
  3309. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3310. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3311. rval, mcp->mb[0], mcp->mb[1]);
  3312. } else {
  3313. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3314. "Done %s.\n", __func__);
  3315. *sector_size = mcp->mb[1];
  3316. }
  3317. return rval;
  3318. }
  3319. int
  3320. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3321. {
  3322. int rval;
  3323. mbx_cmd_t mc;
  3324. mbx_cmd_t *mcp = &mc;
  3325. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3326. return QLA_FUNCTION_FAILED;
  3327. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3328. "Entered %s.\n", __func__);
  3329. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3330. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3331. FAC_OPT_CMD_WRITE_PROTECT;
  3332. mcp->out_mb = MBX_1|MBX_0;
  3333. mcp->in_mb = MBX_1|MBX_0;
  3334. mcp->tov = MBX_TOV_SECONDS;
  3335. mcp->flags = 0;
  3336. rval = qla2x00_mailbox_command(vha, mcp);
  3337. if (rval != QLA_SUCCESS) {
  3338. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3339. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3340. rval, mcp->mb[0], mcp->mb[1]);
  3341. } else {
  3342. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3343. "Done %s.\n", __func__);
  3344. }
  3345. return rval;
  3346. }
  3347. int
  3348. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3349. {
  3350. int rval;
  3351. mbx_cmd_t mc;
  3352. mbx_cmd_t *mcp = &mc;
  3353. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3354. return QLA_FUNCTION_FAILED;
  3355. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3356. "Entered %s.\n", __func__);
  3357. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3358. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3359. mcp->mb[2] = LSW(start);
  3360. mcp->mb[3] = MSW(start);
  3361. mcp->mb[4] = LSW(finish);
  3362. mcp->mb[5] = MSW(finish);
  3363. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3364. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3365. mcp->tov = MBX_TOV_SECONDS;
  3366. mcp->flags = 0;
  3367. rval = qla2x00_mailbox_command(vha, mcp);
  3368. if (rval != QLA_SUCCESS) {
  3369. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3370. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3371. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3372. } else {
  3373. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3374. "Done %s.\n", __func__);
  3375. }
  3376. return rval;
  3377. }
  3378. int
  3379. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3380. {
  3381. int rval = 0;
  3382. mbx_cmd_t mc;
  3383. mbx_cmd_t *mcp = &mc;
  3384. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3385. "Entered %s.\n", __func__);
  3386. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3387. mcp->out_mb = MBX_0;
  3388. mcp->in_mb = MBX_0|MBX_1;
  3389. mcp->tov = MBX_TOV_SECONDS;
  3390. mcp->flags = 0;
  3391. rval = qla2x00_mailbox_command(vha, mcp);
  3392. if (rval != QLA_SUCCESS) {
  3393. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3394. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3395. rval, mcp->mb[0], mcp->mb[1]);
  3396. } else {
  3397. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3398. "Done %s.\n", __func__);
  3399. }
  3400. return rval;
  3401. }
  3402. static int
  3403. qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
  3404. {
  3405. int rval;
  3406. mbx_cmd_t mc;
  3407. mbx_cmd_t *mcp = &mc;
  3408. if (!IS_FWI2_CAPABLE(vha->hw))
  3409. return QLA_FUNCTION_FAILED;
  3410. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
  3411. "Entered %s.\n", __func__);
  3412. mcp->mb[0] = MBC_GET_RNID_PARAMS;
  3413. mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
  3414. mcp->out_mb = MBX_1|MBX_0;
  3415. mcp->in_mb = MBX_1|MBX_0;
  3416. mcp->tov = MBX_TOV_SECONDS;
  3417. mcp->flags = 0;
  3418. rval = qla2x00_mailbox_command(vha, mcp);
  3419. *temp = mcp->mb[1];
  3420. if (rval != QLA_SUCCESS) {
  3421. ql_dbg(ql_dbg_mbx, vha, 0x115a,
  3422. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3423. } else {
  3424. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
  3425. "Done %s.\n", __func__);
  3426. }
  3427. return rval;
  3428. }
  3429. int
  3430. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3431. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3432. {
  3433. int rval;
  3434. mbx_cmd_t mc;
  3435. mbx_cmd_t *mcp = &mc;
  3436. struct qla_hw_data *ha = vha->hw;
  3437. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3438. "Entered %s.\n", __func__);
  3439. if (!IS_FWI2_CAPABLE(ha))
  3440. return QLA_FUNCTION_FAILED;
  3441. if (len == 1)
  3442. opt |= BIT_0;
  3443. mcp->mb[0] = MBC_READ_SFP;
  3444. mcp->mb[1] = dev;
  3445. mcp->mb[2] = MSW(sfp_dma);
  3446. mcp->mb[3] = LSW(sfp_dma);
  3447. mcp->mb[6] = MSW(MSD(sfp_dma));
  3448. mcp->mb[7] = LSW(MSD(sfp_dma));
  3449. mcp->mb[8] = len;
  3450. mcp->mb[9] = off;
  3451. mcp->mb[10] = opt;
  3452. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3453. mcp->in_mb = MBX_1|MBX_0;
  3454. mcp->tov = MBX_TOV_SECONDS;
  3455. mcp->flags = 0;
  3456. rval = qla2x00_mailbox_command(vha, mcp);
  3457. if (opt & BIT_0)
  3458. *sfp = mcp->mb[1];
  3459. if (rval != QLA_SUCCESS) {
  3460. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3461. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3462. } else {
  3463. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3464. "Done %s.\n", __func__);
  3465. }
  3466. return rval;
  3467. }
  3468. int
  3469. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3470. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3471. {
  3472. int rval;
  3473. mbx_cmd_t mc;
  3474. mbx_cmd_t *mcp = &mc;
  3475. struct qla_hw_data *ha = vha->hw;
  3476. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3477. "Entered %s.\n", __func__);
  3478. if (!IS_FWI2_CAPABLE(ha))
  3479. return QLA_FUNCTION_FAILED;
  3480. if (len == 1)
  3481. opt |= BIT_0;
  3482. if (opt & BIT_0)
  3483. len = *sfp;
  3484. mcp->mb[0] = MBC_WRITE_SFP;
  3485. mcp->mb[1] = dev;
  3486. mcp->mb[2] = MSW(sfp_dma);
  3487. mcp->mb[3] = LSW(sfp_dma);
  3488. mcp->mb[6] = MSW(MSD(sfp_dma));
  3489. mcp->mb[7] = LSW(MSD(sfp_dma));
  3490. mcp->mb[8] = len;
  3491. mcp->mb[9] = off;
  3492. mcp->mb[10] = opt;
  3493. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3494. mcp->in_mb = MBX_1|MBX_0;
  3495. mcp->tov = MBX_TOV_SECONDS;
  3496. mcp->flags = 0;
  3497. rval = qla2x00_mailbox_command(vha, mcp);
  3498. if (rval != QLA_SUCCESS) {
  3499. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3500. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3501. } else {
  3502. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3503. "Done %s.\n", __func__);
  3504. }
  3505. return rval;
  3506. }
  3507. int
  3508. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3509. uint16_t size_in_bytes, uint16_t *actual_size)
  3510. {
  3511. int rval;
  3512. mbx_cmd_t mc;
  3513. mbx_cmd_t *mcp = &mc;
  3514. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3515. "Entered %s.\n", __func__);
  3516. if (!IS_CNA_CAPABLE(vha->hw))
  3517. return QLA_FUNCTION_FAILED;
  3518. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3519. mcp->mb[2] = MSW(stats_dma);
  3520. mcp->mb[3] = LSW(stats_dma);
  3521. mcp->mb[6] = MSW(MSD(stats_dma));
  3522. mcp->mb[7] = LSW(MSD(stats_dma));
  3523. mcp->mb[8] = size_in_bytes >> 2;
  3524. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3525. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3526. mcp->tov = MBX_TOV_SECONDS;
  3527. mcp->flags = 0;
  3528. rval = qla2x00_mailbox_command(vha, mcp);
  3529. if (rval != QLA_SUCCESS) {
  3530. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3531. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3532. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3533. } else {
  3534. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3535. "Done %s.\n", __func__);
  3536. *actual_size = mcp->mb[2] << 2;
  3537. }
  3538. return rval;
  3539. }
  3540. int
  3541. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3542. uint16_t size)
  3543. {
  3544. int rval;
  3545. mbx_cmd_t mc;
  3546. mbx_cmd_t *mcp = &mc;
  3547. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3548. "Entered %s.\n", __func__);
  3549. if (!IS_CNA_CAPABLE(vha->hw))
  3550. return QLA_FUNCTION_FAILED;
  3551. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3552. mcp->mb[1] = 0;
  3553. mcp->mb[2] = MSW(tlv_dma);
  3554. mcp->mb[3] = LSW(tlv_dma);
  3555. mcp->mb[6] = MSW(MSD(tlv_dma));
  3556. mcp->mb[7] = LSW(MSD(tlv_dma));
  3557. mcp->mb[8] = size;
  3558. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3559. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3560. mcp->tov = MBX_TOV_SECONDS;
  3561. mcp->flags = 0;
  3562. rval = qla2x00_mailbox_command(vha, mcp);
  3563. if (rval != QLA_SUCCESS) {
  3564. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3565. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3566. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3567. } else {
  3568. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3569. "Done %s.\n", __func__);
  3570. }
  3571. return rval;
  3572. }
  3573. int
  3574. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3575. {
  3576. int rval;
  3577. mbx_cmd_t mc;
  3578. mbx_cmd_t *mcp = &mc;
  3579. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3580. "Entered %s.\n", __func__);
  3581. if (!IS_FWI2_CAPABLE(vha->hw))
  3582. return QLA_FUNCTION_FAILED;
  3583. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3584. mcp->mb[1] = LSW(risc_addr);
  3585. mcp->mb[8] = MSW(risc_addr);
  3586. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3587. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3588. mcp->tov = 30;
  3589. mcp->flags = 0;
  3590. rval = qla2x00_mailbox_command(vha, mcp);
  3591. if (rval != QLA_SUCCESS) {
  3592. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3593. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3594. } else {
  3595. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3596. "Done %s.\n", __func__);
  3597. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3598. }
  3599. return rval;
  3600. }
  3601. int
  3602. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3603. uint16_t *mresp)
  3604. {
  3605. int rval;
  3606. mbx_cmd_t mc;
  3607. mbx_cmd_t *mcp = &mc;
  3608. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3609. "Entered %s.\n", __func__);
  3610. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3611. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3612. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3613. /* transfer count */
  3614. mcp->mb[10] = LSW(mreq->transfer_size);
  3615. mcp->mb[11] = MSW(mreq->transfer_size);
  3616. /* send data address */
  3617. mcp->mb[14] = LSW(mreq->send_dma);
  3618. mcp->mb[15] = MSW(mreq->send_dma);
  3619. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3620. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3621. /* receive data address */
  3622. mcp->mb[16] = LSW(mreq->rcv_dma);
  3623. mcp->mb[17] = MSW(mreq->rcv_dma);
  3624. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3625. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3626. /* Iteration count */
  3627. mcp->mb[18] = LSW(mreq->iteration_count);
  3628. mcp->mb[19] = MSW(mreq->iteration_count);
  3629. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3630. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3631. if (IS_CNA_CAPABLE(vha->hw))
  3632. mcp->out_mb |= MBX_2;
  3633. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3634. mcp->buf_size = mreq->transfer_size;
  3635. mcp->tov = MBX_TOV_SECONDS;
  3636. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3637. rval = qla2x00_mailbox_command(vha, mcp);
  3638. if (rval != QLA_SUCCESS) {
  3639. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3640. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3641. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3642. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3643. } else {
  3644. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3645. "Done %s.\n", __func__);
  3646. }
  3647. /* Copy mailbox information */
  3648. memcpy( mresp, mcp->mb, 64);
  3649. return rval;
  3650. }
  3651. int
  3652. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3653. uint16_t *mresp)
  3654. {
  3655. int rval;
  3656. mbx_cmd_t mc;
  3657. mbx_cmd_t *mcp = &mc;
  3658. struct qla_hw_data *ha = vha->hw;
  3659. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3660. "Entered %s.\n", __func__);
  3661. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3662. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3663. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3664. if (IS_CNA_CAPABLE(ha)) {
  3665. mcp->mb[1] |= BIT_15;
  3666. mcp->mb[2] = vha->fcoe_fcf_idx;
  3667. }
  3668. mcp->mb[16] = LSW(mreq->rcv_dma);
  3669. mcp->mb[17] = MSW(mreq->rcv_dma);
  3670. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3671. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3672. mcp->mb[10] = LSW(mreq->transfer_size);
  3673. mcp->mb[14] = LSW(mreq->send_dma);
  3674. mcp->mb[15] = MSW(mreq->send_dma);
  3675. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3676. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3677. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3678. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3679. if (IS_CNA_CAPABLE(ha))
  3680. mcp->out_mb |= MBX_2;
  3681. mcp->in_mb = MBX_0;
  3682. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3683. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3684. mcp->in_mb |= MBX_1;
  3685. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3686. mcp->in_mb |= MBX_3;
  3687. mcp->tov = MBX_TOV_SECONDS;
  3688. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3689. mcp->buf_size = mreq->transfer_size;
  3690. rval = qla2x00_mailbox_command(vha, mcp);
  3691. if (rval != QLA_SUCCESS) {
  3692. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3693. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3694. rval, mcp->mb[0], mcp->mb[1]);
  3695. } else {
  3696. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3697. "Done %s.\n", __func__);
  3698. }
  3699. /* Copy mailbox information */
  3700. memcpy(mresp, mcp->mb, 64);
  3701. return rval;
  3702. }
  3703. int
  3704. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3705. {
  3706. int rval;
  3707. mbx_cmd_t mc;
  3708. mbx_cmd_t *mcp = &mc;
  3709. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3710. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3711. mcp->mb[0] = MBC_ISP84XX_RESET;
  3712. mcp->mb[1] = enable_diagnostic;
  3713. mcp->out_mb = MBX_1|MBX_0;
  3714. mcp->in_mb = MBX_1|MBX_0;
  3715. mcp->tov = MBX_TOV_SECONDS;
  3716. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3717. rval = qla2x00_mailbox_command(vha, mcp);
  3718. if (rval != QLA_SUCCESS)
  3719. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3720. else
  3721. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3722. "Done %s.\n", __func__);
  3723. return rval;
  3724. }
  3725. int
  3726. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3727. {
  3728. int rval;
  3729. mbx_cmd_t mc;
  3730. mbx_cmd_t *mcp = &mc;
  3731. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3732. "Entered %s.\n", __func__);
  3733. if (!IS_FWI2_CAPABLE(vha->hw))
  3734. return QLA_FUNCTION_FAILED;
  3735. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3736. mcp->mb[1] = LSW(risc_addr);
  3737. mcp->mb[2] = LSW(data);
  3738. mcp->mb[3] = MSW(data);
  3739. mcp->mb[8] = MSW(risc_addr);
  3740. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3741. mcp->in_mb = MBX_0;
  3742. mcp->tov = 30;
  3743. mcp->flags = 0;
  3744. rval = qla2x00_mailbox_command(vha, mcp);
  3745. if (rval != QLA_SUCCESS) {
  3746. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3747. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3748. } else {
  3749. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3750. "Done %s.\n", __func__);
  3751. }
  3752. return rval;
  3753. }
  3754. int
  3755. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3756. {
  3757. int rval;
  3758. uint32_t stat, timer;
  3759. uint16_t mb0 = 0;
  3760. struct qla_hw_data *ha = vha->hw;
  3761. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3762. rval = QLA_SUCCESS;
  3763. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3764. "Entered %s.\n", __func__);
  3765. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3766. /* Write the MBC data to the registers */
  3767. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3768. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3769. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3770. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3771. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3772. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3773. /* Poll for MBC interrupt */
  3774. for (timer = 6000000; timer; timer--) {
  3775. /* Check for pending interrupts. */
  3776. stat = RD_REG_DWORD(&reg->host_status);
  3777. if (stat & HSRX_RISC_INT) {
  3778. stat &= 0xff;
  3779. if (stat == 0x1 || stat == 0x2 ||
  3780. stat == 0x10 || stat == 0x11) {
  3781. set_bit(MBX_INTERRUPT,
  3782. &ha->mbx_cmd_flags);
  3783. mb0 = RD_REG_WORD(&reg->mailbox0);
  3784. WRT_REG_DWORD(&reg->hccr,
  3785. HCCRX_CLR_RISC_INT);
  3786. RD_REG_DWORD(&reg->hccr);
  3787. break;
  3788. }
  3789. }
  3790. udelay(5);
  3791. }
  3792. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3793. rval = mb0 & MBS_MASK;
  3794. else
  3795. rval = QLA_FUNCTION_FAILED;
  3796. if (rval != QLA_SUCCESS) {
  3797. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3798. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3799. } else {
  3800. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3801. "Done %s.\n", __func__);
  3802. }
  3803. return rval;
  3804. }
  3805. int
  3806. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3807. {
  3808. int rval;
  3809. mbx_cmd_t mc;
  3810. mbx_cmd_t *mcp = &mc;
  3811. struct qla_hw_data *ha = vha->hw;
  3812. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3813. "Entered %s.\n", __func__);
  3814. if (!IS_FWI2_CAPABLE(ha))
  3815. return QLA_FUNCTION_FAILED;
  3816. mcp->mb[0] = MBC_DATA_RATE;
  3817. mcp->mb[1] = 0;
  3818. mcp->out_mb = MBX_1|MBX_0;
  3819. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3820. if (IS_QLA83XX(ha))
  3821. mcp->in_mb |= MBX_3;
  3822. mcp->tov = MBX_TOV_SECONDS;
  3823. mcp->flags = 0;
  3824. rval = qla2x00_mailbox_command(vha, mcp);
  3825. if (rval != QLA_SUCCESS) {
  3826. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3827. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3828. } else {
  3829. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3830. "Done %s.\n", __func__);
  3831. if (mcp->mb[1] != 0x7)
  3832. ha->link_data_rate = mcp->mb[1];
  3833. }
  3834. return rval;
  3835. }
  3836. int
  3837. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3838. {
  3839. int rval;
  3840. mbx_cmd_t mc;
  3841. mbx_cmd_t *mcp = &mc;
  3842. struct qla_hw_data *ha = vha->hw;
  3843. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3844. "Entered %s.\n", __func__);
  3845. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha))
  3846. return QLA_FUNCTION_FAILED;
  3847. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3848. mcp->out_mb = MBX_0;
  3849. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3850. mcp->tov = MBX_TOV_SECONDS;
  3851. mcp->flags = 0;
  3852. rval = qla2x00_mailbox_command(vha, mcp);
  3853. if (rval != QLA_SUCCESS) {
  3854. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3855. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3856. } else {
  3857. /* Copy all bits to preserve original value */
  3858. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3859. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3860. "Done %s.\n", __func__);
  3861. }
  3862. return rval;
  3863. }
  3864. int
  3865. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3866. {
  3867. int rval;
  3868. mbx_cmd_t mc;
  3869. mbx_cmd_t *mcp = &mc;
  3870. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3871. "Entered %s.\n", __func__);
  3872. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3873. /* Copy all bits to preserve original setting */
  3874. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3875. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3876. mcp->in_mb = MBX_0;
  3877. mcp->tov = MBX_TOV_SECONDS;
  3878. mcp->flags = 0;
  3879. rval = qla2x00_mailbox_command(vha, mcp);
  3880. if (rval != QLA_SUCCESS) {
  3881. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3882. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3883. } else
  3884. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3885. "Done %s.\n", __func__);
  3886. return rval;
  3887. }
  3888. int
  3889. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3890. uint16_t *mb)
  3891. {
  3892. int rval;
  3893. mbx_cmd_t mc;
  3894. mbx_cmd_t *mcp = &mc;
  3895. struct qla_hw_data *ha = vha->hw;
  3896. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3897. "Entered %s.\n", __func__);
  3898. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3899. return QLA_FUNCTION_FAILED;
  3900. mcp->mb[0] = MBC_PORT_PARAMS;
  3901. mcp->mb[1] = loop_id;
  3902. if (ha->flags.fcp_prio_enabled)
  3903. mcp->mb[2] = BIT_1;
  3904. else
  3905. mcp->mb[2] = BIT_2;
  3906. mcp->mb[4] = priority & 0xf;
  3907. mcp->mb[9] = vha->vp_idx;
  3908. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3909. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3910. mcp->tov = 30;
  3911. mcp->flags = 0;
  3912. rval = qla2x00_mailbox_command(vha, mcp);
  3913. if (mb != NULL) {
  3914. mb[0] = mcp->mb[0];
  3915. mb[1] = mcp->mb[1];
  3916. mb[3] = mcp->mb[3];
  3917. mb[4] = mcp->mb[4];
  3918. }
  3919. if (rval != QLA_SUCCESS) {
  3920. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3921. } else {
  3922. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  3923. "Done %s.\n", __func__);
  3924. }
  3925. return rval;
  3926. }
  3927. int
  3928. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
  3929. {
  3930. int rval = QLA_FUNCTION_FAILED;
  3931. struct qla_hw_data *ha = vha->hw;
  3932. uint8_t byte;
  3933. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
  3934. "Entered %s.\n", __func__);
  3935. if (ha->thermal_support & THERMAL_SUPPORT_I2C) {
  3936. rval = qla2x00_read_sfp(vha, 0, &byte,
  3937. 0x98, 0x1, 1, BIT_13|BIT_12|BIT_0);
  3938. *temp = byte;
  3939. if (rval == QLA_SUCCESS)
  3940. goto done;
  3941. ql_log(ql_log_warn, vha, 0x10c9,
  3942. "Thermal not supported through I2C bus, trying alternate "
  3943. "method (ISP access).\n");
  3944. ha->thermal_support &= ~THERMAL_SUPPORT_I2C;
  3945. }
  3946. if (ha->thermal_support & THERMAL_SUPPORT_ISP) {
  3947. rval = qla2x00_read_asic_temperature(vha, temp);
  3948. if (rval == QLA_SUCCESS)
  3949. goto done;
  3950. ql_log(ql_log_warn, vha, 0x1019,
  3951. "Thermal not supported through ISP.\n");
  3952. ha->thermal_support &= ~THERMAL_SUPPORT_ISP;
  3953. }
  3954. ql_log(ql_log_warn, vha, 0x1150,
  3955. "Thermal not supported by this card "
  3956. "(ignoring further requests).\n");
  3957. return rval;
  3958. done:
  3959. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
  3960. "Done %s.\n", __func__);
  3961. return rval;
  3962. }
  3963. int
  3964. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3965. {
  3966. int rval;
  3967. struct qla_hw_data *ha = vha->hw;
  3968. mbx_cmd_t mc;
  3969. mbx_cmd_t *mcp = &mc;
  3970. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  3971. "Entered %s.\n", __func__);
  3972. if (!IS_FWI2_CAPABLE(ha))
  3973. return QLA_FUNCTION_FAILED;
  3974. memset(mcp, 0, sizeof(mbx_cmd_t));
  3975. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3976. mcp->mb[1] = 1;
  3977. mcp->out_mb = MBX_1|MBX_0;
  3978. mcp->in_mb = MBX_0;
  3979. mcp->tov = 30;
  3980. mcp->flags = 0;
  3981. rval = qla2x00_mailbox_command(vha, mcp);
  3982. if (rval != QLA_SUCCESS) {
  3983. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3984. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3985. } else {
  3986. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  3987. "Done %s.\n", __func__);
  3988. }
  3989. return rval;
  3990. }
  3991. int
  3992. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3993. {
  3994. int rval;
  3995. struct qla_hw_data *ha = vha->hw;
  3996. mbx_cmd_t mc;
  3997. mbx_cmd_t *mcp = &mc;
  3998. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  3999. "Entered %s.\n", __func__);
  4000. if (!IS_P3P_TYPE(ha))
  4001. return QLA_FUNCTION_FAILED;
  4002. memset(mcp, 0, sizeof(mbx_cmd_t));
  4003. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4004. mcp->mb[1] = 0;
  4005. mcp->out_mb = MBX_1|MBX_0;
  4006. mcp->in_mb = MBX_0;
  4007. mcp->tov = 30;
  4008. mcp->flags = 0;
  4009. rval = qla2x00_mailbox_command(vha, mcp);
  4010. if (rval != QLA_SUCCESS) {
  4011. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  4012. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4013. } else {
  4014. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  4015. "Done %s.\n", __func__);
  4016. }
  4017. return rval;
  4018. }
  4019. int
  4020. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  4021. {
  4022. struct qla_hw_data *ha = vha->hw;
  4023. mbx_cmd_t mc;
  4024. mbx_cmd_t *mcp = &mc;
  4025. int rval = QLA_FUNCTION_FAILED;
  4026. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  4027. "Entered %s.\n", __func__);
  4028. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4029. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4030. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4031. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  4032. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  4033. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4034. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  4035. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4036. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4037. mcp->tov = MBX_TOV_SECONDS;
  4038. rval = qla2x00_mailbox_command(vha, mcp);
  4039. /* Always copy back return mailbox values. */
  4040. if (rval != QLA_SUCCESS) {
  4041. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  4042. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4043. (mcp->mb[1] << 16) | mcp->mb[0],
  4044. (mcp->mb[3] << 16) | mcp->mb[2]);
  4045. } else {
  4046. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  4047. "Done %s.\n", __func__);
  4048. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  4049. if (!ha->md_template_size) {
  4050. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  4051. "Null template size obtained.\n");
  4052. rval = QLA_FUNCTION_FAILED;
  4053. }
  4054. }
  4055. return rval;
  4056. }
  4057. int
  4058. qla82xx_md_get_template(scsi_qla_host_t *vha)
  4059. {
  4060. struct qla_hw_data *ha = vha->hw;
  4061. mbx_cmd_t mc;
  4062. mbx_cmd_t *mcp = &mc;
  4063. int rval = QLA_FUNCTION_FAILED;
  4064. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  4065. "Entered %s.\n", __func__);
  4066. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4067. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4068. if (!ha->md_tmplt_hdr) {
  4069. ql_log(ql_log_warn, vha, 0x1124,
  4070. "Unable to allocate memory for Minidump template.\n");
  4071. return rval;
  4072. }
  4073. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4074. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4075. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4076. mcp->mb[2] = LSW(RQST_TMPLT);
  4077. mcp->mb[3] = MSW(RQST_TMPLT);
  4078. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4079. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4080. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4081. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4082. mcp->mb[8] = LSW(ha->md_template_size);
  4083. mcp->mb[9] = MSW(ha->md_template_size);
  4084. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4085. mcp->tov = MBX_TOV_SECONDS;
  4086. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4087. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4088. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4089. rval = qla2x00_mailbox_command(vha, mcp);
  4090. if (rval != QLA_SUCCESS) {
  4091. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4092. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4093. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4094. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4095. } else
  4096. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4097. "Done %s.\n", __func__);
  4098. return rval;
  4099. }
  4100. int
  4101. qla8044_md_get_template(scsi_qla_host_t *vha)
  4102. {
  4103. struct qla_hw_data *ha = vha->hw;
  4104. mbx_cmd_t mc;
  4105. mbx_cmd_t *mcp = &mc;
  4106. int rval = QLA_FUNCTION_FAILED;
  4107. int offset = 0, size = MINIDUMP_SIZE_36K;
  4108. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
  4109. "Entered %s.\n", __func__);
  4110. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4111. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4112. if (!ha->md_tmplt_hdr) {
  4113. ql_log(ql_log_warn, vha, 0xb11b,
  4114. "Unable to allocate memory for Minidump template.\n");
  4115. return rval;
  4116. }
  4117. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4118. while (offset < ha->md_template_size) {
  4119. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4120. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4121. mcp->mb[2] = LSW(RQST_TMPLT);
  4122. mcp->mb[3] = MSW(RQST_TMPLT);
  4123. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4124. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4125. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4126. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4127. mcp->mb[8] = LSW(size);
  4128. mcp->mb[9] = MSW(size);
  4129. mcp->mb[10] = offset & 0x0000FFFF;
  4130. mcp->mb[11] = offset & 0xFFFF0000;
  4131. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4132. mcp->tov = MBX_TOV_SECONDS;
  4133. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4134. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4135. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4136. rval = qla2x00_mailbox_command(vha, mcp);
  4137. if (rval != QLA_SUCCESS) {
  4138. ql_dbg(ql_dbg_mbx, vha, 0xb11c,
  4139. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4140. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4141. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4142. return rval;
  4143. } else
  4144. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
  4145. "Done %s.\n", __func__);
  4146. offset = offset + size;
  4147. }
  4148. return rval;
  4149. }
  4150. int
  4151. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4152. {
  4153. int rval;
  4154. struct qla_hw_data *ha = vha->hw;
  4155. mbx_cmd_t mc;
  4156. mbx_cmd_t *mcp = &mc;
  4157. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4158. return QLA_FUNCTION_FAILED;
  4159. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4160. "Entered %s.\n", __func__);
  4161. memset(mcp, 0, sizeof(mbx_cmd_t));
  4162. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4163. mcp->mb[1] = led_cfg[0];
  4164. mcp->mb[2] = led_cfg[1];
  4165. if (IS_QLA8031(ha)) {
  4166. mcp->mb[3] = led_cfg[2];
  4167. mcp->mb[4] = led_cfg[3];
  4168. mcp->mb[5] = led_cfg[4];
  4169. mcp->mb[6] = led_cfg[5];
  4170. }
  4171. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4172. if (IS_QLA8031(ha))
  4173. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4174. mcp->in_mb = MBX_0;
  4175. mcp->tov = 30;
  4176. mcp->flags = 0;
  4177. rval = qla2x00_mailbox_command(vha, mcp);
  4178. if (rval != QLA_SUCCESS) {
  4179. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4180. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4181. } else {
  4182. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4183. "Done %s.\n", __func__);
  4184. }
  4185. return rval;
  4186. }
  4187. int
  4188. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4189. {
  4190. int rval;
  4191. struct qla_hw_data *ha = vha->hw;
  4192. mbx_cmd_t mc;
  4193. mbx_cmd_t *mcp = &mc;
  4194. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4195. return QLA_FUNCTION_FAILED;
  4196. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4197. "Entered %s.\n", __func__);
  4198. memset(mcp, 0, sizeof(mbx_cmd_t));
  4199. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4200. mcp->out_mb = MBX_0;
  4201. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4202. if (IS_QLA8031(ha))
  4203. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4204. mcp->tov = 30;
  4205. mcp->flags = 0;
  4206. rval = qla2x00_mailbox_command(vha, mcp);
  4207. if (rval != QLA_SUCCESS) {
  4208. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4209. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4210. } else {
  4211. led_cfg[0] = mcp->mb[1];
  4212. led_cfg[1] = mcp->mb[2];
  4213. if (IS_QLA8031(ha)) {
  4214. led_cfg[2] = mcp->mb[3];
  4215. led_cfg[3] = mcp->mb[4];
  4216. led_cfg[4] = mcp->mb[5];
  4217. led_cfg[5] = mcp->mb[6];
  4218. }
  4219. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4220. "Done %s.\n", __func__);
  4221. }
  4222. return rval;
  4223. }
  4224. int
  4225. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4226. {
  4227. int rval;
  4228. struct qla_hw_data *ha = vha->hw;
  4229. mbx_cmd_t mc;
  4230. mbx_cmd_t *mcp = &mc;
  4231. if (!IS_P3P_TYPE(ha))
  4232. return QLA_FUNCTION_FAILED;
  4233. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4234. "Entered %s.\n", __func__);
  4235. memset(mcp, 0, sizeof(mbx_cmd_t));
  4236. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4237. if (enable)
  4238. mcp->mb[7] = 0xE;
  4239. else
  4240. mcp->mb[7] = 0xD;
  4241. mcp->out_mb = MBX_7|MBX_0;
  4242. mcp->in_mb = MBX_0;
  4243. mcp->tov = MBX_TOV_SECONDS;
  4244. mcp->flags = 0;
  4245. rval = qla2x00_mailbox_command(vha, mcp);
  4246. if (rval != QLA_SUCCESS) {
  4247. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4248. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4249. } else {
  4250. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4251. "Done %s.\n", __func__);
  4252. }
  4253. return rval;
  4254. }
  4255. int
  4256. qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4257. {
  4258. int rval;
  4259. struct qla_hw_data *ha = vha->hw;
  4260. mbx_cmd_t mc;
  4261. mbx_cmd_t *mcp = &mc;
  4262. if (!IS_QLA83XX(ha))
  4263. return QLA_FUNCTION_FAILED;
  4264. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4265. "Entered %s.\n", __func__);
  4266. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4267. mcp->mb[1] = LSW(reg);
  4268. mcp->mb[2] = MSW(reg);
  4269. mcp->mb[3] = LSW(data);
  4270. mcp->mb[4] = MSW(data);
  4271. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4272. mcp->in_mb = MBX_1|MBX_0;
  4273. mcp->tov = MBX_TOV_SECONDS;
  4274. mcp->flags = 0;
  4275. rval = qla2x00_mailbox_command(vha, mcp);
  4276. if (rval != QLA_SUCCESS) {
  4277. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4278. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4279. } else {
  4280. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4281. "Done %s.\n", __func__);
  4282. }
  4283. return rval;
  4284. }
  4285. int
  4286. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4287. {
  4288. int rval;
  4289. struct qla_hw_data *ha = vha->hw;
  4290. mbx_cmd_t mc;
  4291. mbx_cmd_t *mcp = &mc;
  4292. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4293. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4294. "Implicit LOGO Unsupported.\n");
  4295. return QLA_FUNCTION_FAILED;
  4296. }
  4297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4298. "Entering %s.\n", __func__);
  4299. /* Perform Implicit LOGO. */
  4300. mcp->mb[0] = MBC_PORT_LOGOUT;
  4301. mcp->mb[1] = fcport->loop_id;
  4302. mcp->mb[10] = BIT_15;
  4303. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4304. mcp->in_mb = MBX_0;
  4305. mcp->tov = MBX_TOV_SECONDS;
  4306. mcp->flags = 0;
  4307. rval = qla2x00_mailbox_command(vha, mcp);
  4308. if (rval != QLA_SUCCESS)
  4309. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4310. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4311. else
  4312. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4313. "Done %s.\n", __func__);
  4314. return rval;
  4315. }
  4316. int
  4317. qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
  4318. {
  4319. int rval;
  4320. mbx_cmd_t mc;
  4321. mbx_cmd_t *mcp = &mc;
  4322. struct qla_hw_data *ha = vha->hw;
  4323. unsigned long retry_max_time = jiffies + (2 * HZ);
  4324. if (!IS_QLA83XX(ha))
  4325. return QLA_FUNCTION_FAILED;
  4326. ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
  4327. retry_rd_reg:
  4328. mcp->mb[0] = MBC_READ_REMOTE_REG;
  4329. mcp->mb[1] = LSW(reg);
  4330. mcp->mb[2] = MSW(reg);
  4331. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4332. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4333. mcp->tov = MBX_TOV_SECONDS;
  4334. mcp->flags = 0;
  4335. rval = qla2x00_mailbox_command(vha, mcp);
  4336. if (rval != QLA_SUCCESS) {
  4337. ql_dbg(ql_dbg_mbx, vha, 0x114c,
  4338. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4339. rval, mcp->mb[0], mcp->mb[1]);
  4340. } else {
  4341. *data = (mcp->mb[3] | (mcp->mb[4] << 16));
  4342. if (*data == QLA8XXX_BAD_VALUE) {
  4343. /*
  4344. * During soft-reset CAMRAM register reads might
  4345. * return 0xbad0bad0. So retry for MAX of 2 sec
  4346. * while reading camram registers.
  4347. */
  4348. if (time_after(jiffies, retry_max_time)) {
  4349. ql_dbg(ql_dbg_mbx, vha, 0x1141,
  4350. "Failure to read CAMRAM register. "
  4351. "data=0x%x.\n", *data);
  4352. return QLA_FUNCTION_FAILED;
  4353. }
  4354. msleep(100);
  4355. goto retry_rd_reg;
  4356. }
  4357. ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
  4358. }
  4359. return rval;
  4360. }
  4361. int
  4362. qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
  4363. {
  4364. int rval;
  4365. mbx_cmd_t mc;
  4366. mbx_cmd_t *mcp = &mc;
  4367. struct qla_hw_data *ha = vha->hw;
  4368. if (!IS_QLA83XX(ha))
  4369. return QLA_FUNCTION_FAILED;
  4370. ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
  4371. mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
  4372. mcp->out_mb = MBX_0;
  4373. mcp->in_mb = MBX_1|MBX_0;
  4374. mcp->tov = MBX_TOV_SECONDS;
  4375. mcp->flags = 0;
  4376. rval = qla2x00_mailbox_command(vha, mcp);
  4377. if (rval != QLA_SUCCESS) {
  4378. ql_dbg(ql_dbg_mbx, vha, 0x1144,
  4379. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4380. rval, mcp->mb[0], mcp->mb[1]);
  4381. ha->isp_ops->fw_dump(vha, 0);
  4382. } else {
  4383. ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
  4384. }
  4385. return rval;
  4386. }
  4387. int
  4388. qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
  4389. uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
  4390. {
  4391. int rval;
  4392. mbx_cmd_t mc;
  4393. mbx_cmd_t *mcp = &mc;
  4394. uint8_t subcode = (uint8_t)options;
  4395. struct qla_hw_data *ha = vha->hw;
  4396. if (!IS_QLA8031(ha))
  4397. return QLA_FUNCTION_FAILED;
  4398. ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
  4399. mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
  4400. mcp->mb[1] = options;
  4401. mcp->out_mb = MBX_1|MBX_0;
  4402. if (subcode & BIT_2) {
  4403. mcp->mb[2] = LSW(start_addr);
  4404. mcp->mb[3] = MSW(start_addr);
  4405. mcp->mb[4] = LSW(end_addr);
  4406. mcp->mb[5] = MSW(end_addr);
  4407. mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
  4408. }
  4409. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4410. if (!(subcode & (BIT_2 | BIT_5)))
  4411. mcp->in_mb |= MBX_4|MBX_3;
  4412. mcp->tov = MBX_TOV_SECONDS;
  4413. mcp->flags = 0;
  4414. rval = qla2x00_mailbox_command(vha, mcp);
  4415. if (rval != QLA_SUCCESS) {
  4416. ql_dbg(ql_dbg_mbx, vha, 0x1147,
  4417. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
  4418. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  4419. mcp->mb[4]);
  4420. ha->isp_ops->fw_dump(vha, 0);
  4421. } else {
  4422. if (subcode & BIT_5)
  4423. *sector_size = mcp->mb[1];
  4424. else if (subcode & (BIT_6 | BIT_7)) {
  4425. ql_dbg(ql_dbg_mbx, vha, 0x1148,
  4426. "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4427. } else if (subcode & (BIT_3 | BIT_4)) {
  4428. ql_dbg(ql_dbg_mbx, vha, 0x1149,
  4429. "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4430. }
  4431. ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
  4432. }
  4433. return rval;
  4434. }
  4435. int
  4436. qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  4437. uint32_t size)
  4438. {
  4439. int rval;
  4440. mbx_cmd_t mc;
  4441. mbx_cmd_t *mcp = &mc;
  4442. if (!IS_MCTP_CAPABLE(vha->hw))
  4443. return QLA_FUNCTION_FAILED;
  4444. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
  4445. "Entered %s.\n", __func__);
  4446. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  4447. mcp->mb[1] = LSW(addr);
  4448. mcp->mb[2] = MSW(req_dma);
  4449. mcp->mb[3] = LSW(req_dma);
  4450. mcp->mb[4] = MSW(size);
  4451. mcp->mb[5] = LSW(size);
  4452. mcp->mb[6] = MSW(MSD(req_dma));
  4453. mcp->mb[7] = LSW(MSD(req_dma));
  4454. mcp->mb[8] = MSW(addr);
  4455. /* Setting RAM ID to valid */
  4456. mcp->mb[10] |= BIT_7;
  4457. /* For MCTP RAM ID is 0x40 */
  4458. mcp->mb[10] |= 0x40;
  4459. mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
  4460. MBX_0;
  4461. mcp->in_mb = MBX_0;
  4462. mcp->tov = MBX_TOV_SECONDS;
  4463. mcp->flags = 0;
  4464. rval = qla2x00_mailbox_command(vha, mcp);
  4465. if (rval != QLA_SUCCESS) {
  4466. ql_dbg(ql_dbg_mbx, vha, 0x114e,
  4467. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4468. } else {
  4469. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
  4470. "Done %s.\n", __func__);
  4471. }
  4472. return rval;
  4473. }