ar9003_phy.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "ar9003_phy.h"
  18. /**
  19. * ar9003_hw_set_channel - set channel on single-chip device
  20. * @ah: atheros hardware structure
  21. * @chan:
  22. *
  23. * This is the function to change channel on single-chip devices, that is
  24. * all devices after ar9280.
  25. *
  26. * This function takes the channel value in MHz and sets
  27. * hardware channel value. Assumes writes have been enabled to analog bus.
  28. *
  29. * Actual Expression,
  30. *
  31. * For 2GHz channel,
  32. * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  33. * (freq_ref = 40MHz)
  34. *
  35. * For 5GHz channel,
  36. * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  37. * (freq_ref = 40MHz/(24>>amodeRefSel))
  38. *
  39. * For 5GHz channels which are 5MHz spaced,
  40. * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  41. * (freq_ref = 40MHz)
  42. */
  43. static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  44. {
  45. /* TODO */
  46. return 0;
  47. }
  48. /**
  49. * ar9003_hw_spur_mitigate - convert baseband spur frequency
  50. * @ah: atheros hardware structure
  51. * @chan:
  52. *
  53. * For single-chip solutions. Converts to baseband spur frequency given the
  54. * input channel frequency and compute register settings below.
  55. *
  56. * Spur mitigation for MRC CCK
  57. */
  58. static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
  59. struct ath9k_channel *chan)
  60. {
  61. /* TODO */
  62. }
  63. static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
  64. struct ath9k_channel *chan)
  65. {
  66. /* TODO */
  67. return 0;
  68. }
  69. static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
  70. struct ath9k_channel *chan)
  71. {
  72. /* TODO */
  73. }
  74. static void ar9003_hw_init_bb(struct ath_hw *ah,
  75. struct ath9k_channel *chan)
  76. {
  77. /* TODO */
  78. }
  79. static int ar9003_hw_process_ini(struct ath_hw *ah,
  80. struct ath9k_channel *chan)
  81. {
  82. /* TODO */
  83. return -1;
  84. }
  85. static void ar9003_hw_set_rfmode(struct ath_hw *ah,
  86. struct ath9k_channel *chan)
  87. {
  88. /* TODO */
  89. }
  90. static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
  91. {
  92. /* TODO */
  93. }
  94. static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
  95. struct ath9k_channel *chan)
  96. {
  97. /* TODO */
  98. }
  99. static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
  100. {
  101. /* TODO */
  102. return false;
  103. }
  104. static void ar9003_hw_rfbus_done(struct ath_hw *ah)
  105. {
  106. /* TODO */
  107. }
  108. static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
  109. {
  110. /* TODO */
  111. }
  112. static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
  113. {
  114. /* TODO */
  115. }
  116. void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
  117. {
  118. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  119. priv_ops->rf_set_freq = ar9003_hw_set_channel;
  120. priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
  121. priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
  122. priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
  123. priv_ops->init_bb = ar9003_hw_init_bb;
  124. priv_ops->process_ini = ar9003_hw_process_ini;
  125. priv_ops->set_rfmode = ar9003_hw_set_rfmode;
  126. priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
  127. priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
  128. priv_ops->rfbus_req = ar9003_hw_rfbus_req;
  129. priv_ops->rfbus_done = ar9003_hw_rfbus_done;
  130. priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
  131. priv_ops->set_diversity = ar9003_hw_set_diversity;
  132. }