sh_mmcif.c 25 KB

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  1. /*
  2. * MMCIF eMMC driver.
  3. *
  4. * Copyright (C) 2010 Renesas Solutions Corp.
  5. * Yusuke Goda <yusuke.goda.sx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License.
  10. *
  11. *
  12. * TODO
  13. * 1. DMA
  14. * 2. Power management
  15. * 3. Handle MMC errors better
  16. *
  17. */
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/card.h>
  21. #include <linux/mmc/core.h>
  22. #include <linux/mmc/mmc.h>
  23. #include <linux/mmc/sdio.h>
  24. #include <linux/delay.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/clk.h>
  27. #include <linux/mmc/sh_mmcif.h>
  28. #define DRIVER_NAME "sh_mmcif"
  29. #define DRIVER_VERSION "2010-04-28"
  30. /* CE_CMD_SET */
  31. #define CMD_MASK 0x3f000000
  32. #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
  33. #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  34. #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
  35. #define CMD_SET_RBSY (1 << 21) /* R1b */
  36. #define CMD_SET_CCSEN (1 << 20)
  37. #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
  38. #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
  39. #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
  40. #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
  41. #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
  42. #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
  43. #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
  44. #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
  45. #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
  46. #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  47. #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
  48. #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
  49. #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
  50. #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
  51. #define CMD_SET_CCSH (1 << 5)
  52. #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
  53. #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
  54. #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
  55. /* CE_CMD_CTRL */
  56. #define CMD_CTRL_BREAK (1 << 0)
  57. /* CE_BLOCK_SET */
  58. #define BLOCK_SIZE_MASK 0x0000ffff
  59. /* CE_INT */
  60. #define INT_CCSDE (1 << 29)
  61. #define INT_CMD12DRE (1 << 26)
  62. #define INT_CMD12RBE (1 << 25)
  63. #define INT_CMD12CRE (1 << 24)
  64. #define INT_DTRANE (1 << 23)
  65. #define INT_BUFRE (1 << 22)
  66. #define INT_BUFWEN (1 << 21)
  67. #define INT_BUFREN (1 << 20)
  68. #define INT_CCSRCV (1 << 19)
  69. #define INT_RBSYE (1 << 17)
  70. #define INT_CRSPE (1 << 16)
  71. #define INT_CMDVIO (1 << 15)
  72. #define INT_BUFVIO (1 << 14)
  73. #define INT_WDATERR (1 << 11)
  74. #define INT_RDATERR (1 << 10)
  75. #define INT_RIDXERR (1 << 9)
  76. #define INT_RSPERR (1 << 8)
  77. #define INT_CCSTO (1 << 5)
  78. #define INT_CRCSTO (1 << 4)
  79. #define INT_WDATTO (1 << 3)
  80. #define INT_RDATTO (1 << 2)
  81. #define INT_RBSYTO (1 << 1)
  82. #define INT_RSPTO (1 << 0)
  83. #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
  84. INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
  85. INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
  86. INT_RDATTO | INT_RBSYTO | INT_RSPTO)
  87. /* CE_INT_MASK */
  88. #define MASK_ALL 0x00000000
  89. #define MASK_MCCSDE (1 << 29)
  90. #define MASK_MCMD12DRE (1 << 26)
  91. #define MASK_MCMD12RBE (1 << 25)
  92. #define MASK_MCMD12CRE (1 << 24)
  93. #define MASK_MDTRANE (1 << 23)
  94. #define MASK_MBUFRE (1 << 22)
  95. #define MASK_MBUFWEN (1 << 21)
  96. #define MASK_MBUFREN (1 << 20)
  97. #define MASK_MCCSRCV (1 << 19)
  98. #define MASK_MRBSYE (1 << 17)
  99. #define MASK_MCRSPE (1 << 16)
  100. #define MASK_MCMDVIO (1 << 15)
  101. #define MASK_MBUFVIO (1 << 14)
  102. #define MASK_MWDATERR (1 << 11)
  103. #define MASK_MRDATERR (1 << 10)
  104. #define MASK_MRIDXERR (1 << 9)
  105. #define MASK_MRSPERR (1 << 8)
  106. #define MASK_MCCSTO (1 << 5)
  107. #define MASK_MCRCSTO (1 << 4)
  108. #define MASK_MWDATTO (1 << 3)
  109. #define MASK_MRDATTO (1 << 2)
  110. #define MASK_MRBSYTO (1 << 1)
  111. #define MASK_MRSPTO (1 << 0)
  112. /* CE_HOST_STS1 */
  113. #define STS1_CMDSEQ (1 << 31)
  114. /* CE_HOST_STS2 */
  115. #define STS2_CRCSTE (1 << 31)
  116. #define STS2_CRC16E (1 << 30)
  117. #define STS2_AC12CRCE (1 << 29)
  118. #define STS2_RSPCRC7E (1 << 28)
  119. #define STS2_CRCSTEBE (1 << 27)
  120. #define STS2_RDATEBE (1 << 26)
  121. #define STS2_AC12REBE (1 << 25)
  122. #define STS2_RSPEBE (1 << 24)
  123. #define STS2_AC12IDXE (1 << 23)
  124. #define STS2_RSPIDXE (1 << 22)
  125. #define STS2_CCSTO (1 << 15)
  126. #define STS2_RDATTO (1 << 14)
  127. #define STS2_DATBSYTO (1 << 13)
  128. #define STS2_CRCSTTO (1 << 12)
  129. #define STS2_AC12BSYTO (1 << 11)
  130. #define STS2_RSPBSYTO (1 << 10)
  131. #define STS2_AC12RSPTO (1 << 9)
  132. #define STS2_RSPTO (1 << 8)
  133. #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
  134. STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
  135. #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
  136. STS2_DATBSYTO | STS2_CRCSTTO | \
  137. STS2_AC12BSYTO | STS2_RSPBSYTO | \
  138. STS2_AC12RSPTO | STS2_RSPTO)
  139. #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
  140. #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
  141. #define CLKDEV_INIT 400000 /* 400 KHz */
  142. struct sh_mmcif_host {
  143. struct mmc_host *mmc;
  144. struct mmc_data *data;
  145. struct mmc_command *cmd;
  146. struct platform_device *pd;
  147. struct clk *hclk;
  148. unsigned int clk;
  149. int bus_width;
  150. u16 wait_int;
  151. u16 sd_error;
  152. long timeout;
  153. void __iomem *addr;
  154. wait_queue_head_t intr_wait;
  155. };
  156. static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
  157. unsigned int reg, u32 val)
  158. {
  159. writel(val | readl(host->addr + reg), host->addr + reg);
  160. }
  161. static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
  162. unsigned int reg, u32 val)
  163. {
  164. writel(~val & readl(host->addr + reg), host->addr + reg);
  165. }
  166. static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
  167. {
  168. struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
  169. sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
  170. sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
  171. if (!clk)
  172. return;
  173. if (p->sup_pclk && clk == host->clk)
  174. sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
  175. else
  176. sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
  177. (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
  178. sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
  179. }
  180. static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
  181. {
  182. u32 tmp;
  183. tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
  184. sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
  185. sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
  186. sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
  187. SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
  188. /* byte swap on */
  189. sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
  190. }
  191. static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
  192. {
  193. u32 state1, state2;
  194. int ret, timeout = 10000000;
  195. host->sd_error = 0;
  196. host->wait_int = 0;
  197. state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
  198. state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
  199. pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
  200. pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
  201. if (state1 & STS1_CMDSEQ) {
  202. sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
  203. sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
  204. while (1) {
  205. timeout--;
  206. if (timeout < 0) {
  207. pr_err(DRIVER_NAME": Forceed end of " \
  208. "command sequence timeout err\n");
  209. return -EIO;
  210. }
  211. if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
  212. & STS1_CMDSEQ))
  213. break;
  214. mdelay(1);
  215. }
  216. sh_mmcif_sync_reset(host);
  217. pr_debug(DRIVER_NAME": Forced end of command sequence\n");
  218. return -EIO;
  219. }
  220. if (state2 & STS2_CRC_ERR) {
  221. pr_debug(DRIVER_NAME": Happened CRC error\n");
  222. ret = -EIO;
  223. } else if (state2 & STS2_TIMEOUT_ERR) {
  224. pr_debug(DRIVER_NAME": Happened Timeout error\n");
  225. ret = -ETIMEDOUT;
  226. } else {
  227. pr_debug(DRIVER_NAME": Happened End/Index error\n");
  228. ret = -EIO;
  229. }
  230. return ret;
  231. }
  232. static int sh_mmcif_single_read(struct sh_mmcif_host *host,
  233. struct mmc_request *mrq)
  234. {
  235. struct mmc_data *data = mrq->data;
  236. long time;
  237. u32 blocksize, i, *p = sg_virt(data->sg);
  238. host->wait_int = 0;
  239. /* buf read enable */
  240. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
  241. time = wait_event_interruptible_timeout(host->intr_wait,
  242. host->wait_int == 1 ||
  243. host->sd_error == 1, host->timeout);
  244. if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
  245. return sh_mmcif_error_manage(host);
  246. host->wait_int = 0;
  247. blocksize = (BLOCK_SIZE_MASK &
  248. sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
  249. for (i = 0; i < blocksize / 4; i++)
  250. *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
  251. /* buffer read end */
  252. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
  253. time = wait_event_interruptible_timeout(host->intr_wait,
  254. host->wait_int == 1 ||
  255. host->sd_error == 1, host->timeout);
  256. if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
  257. return sh_mmcif_error_manage(host);
  258. host->wait_int = 0;
  259. return 0;
  260. }
  261. static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
  262. struct mmc_request *mrq)
  263. {
  264. struct mmc_data *data = mrq->data;
  265. long time;
  266. u32 blocksize, i, j, sec, *p;
  267. blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
  268. MMCIF_CE_BLOCK_SET);
  269. for (j = 0; j < data->sg_len; j++) {
  270. p = sg_virt(data->sg);
  271. host->wait_int = 0;
  272. for (sec = 0; sec < data->sg->length / blocksize; sec++) {
  273. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
  274. /* buf read enable */
  275. time = wait_event_interruptible_timeout(host->intr_wait,
  276. host->wait_int == 1 ||
  277. host->sd_error == 1, host->timeout);
  278. if (host->wait_int != 1 &&
  279. (time == 0 || host->sd_error != 0))
  280. return sh_mmcif_error_manage(host);
  281. host->wait_int = 0;
  282. for (i = 0; i < blocksize / 4; i++)
  283. *p++ = sh_mmcif_readl(host->addr,
  284. MMCIF_CE_DATA);
  285. }
  286. if (j < data->sg_len - 1)
  287. data->sg++;
  288. }
  289. return 0;
  290. }
  291. static int sh_mmcif_single_write(struct sh_mmcif_host *host,
  292. struct mmc_request *mrq)
  293. {
  294. struct mmc_data *data = mrq->data;
  295. long time;
  296. u32 blocksize, i, *p = sg_virt(data->sg);
  297. host->wait_int = 0;
  298. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
  299. /* buf write enable */
  300. time = wait_event_interruptible_timeout(host->intr_wait,
  301. host->wait_int == 1 ||
  302. host->sd_error == 1, host->timeout);
  303. if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
  304. return sh_mmcif_error_manage(host);
  305. host->wait_int = 0;
  306. blocksize = (BLOCK_SIZE_MASK &
  307. sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
  308. for (i = 0; i < blocksize / 4; i++)
  309. sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
  310. /* buffer write end */
  311. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
  312. time = wait_event_interruptible_timeout(host->intr_wait,
  313. host->wait_int == 1 ||
  314. host->sd_error == 1, host->timeout);
  315. if (host->wait_int != 1 && (time == 0 || host->sd_error != 0))
  316. return sh_mmcif_error_manage(host);
  317. host->wait_int = 0;
  318. return 0;
  319. }
  320. static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
  321. struct mmc_request *mrq)
  322. {
  323. struct mmc_data *data = mrq->data;
  324. long time;
  325. u32 i, sec, j, blocksize, *p;
  326. blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
  327. MMCIF_CE_BLOCK_SET);
  328. for (j = 0; j < data->sg_len; j++) {
  329. p = sg_virt(data->sg);
  330. host->wait_int = 0;
  331. for (sec = 0; sec < data->sg->length / blocksize; sec++) {
  332. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
  333. /* buf write enable*/
  334. time = wait_event_interruptible_timeout(host->intr_wait,
  335. host->wait_int == 1 ||
  336. host->sd_error == 1, host->timeout);
  337. if (host->wait_int != 1 &&
  338. (time == 0 || host->sd_error != 0))
  339. return sh_mmcif_error_manage(host);
  340. host->wait_int = 0;
  341. for (i = 0; i < blocksize / 4; i++)
  342. sh_mmcif_writel(host->addr,
  343. MMCIF_CE_DATA, *p++);
  344. }
  345. if (j < data->sg_len - 1)
  346. data->sg++;
  347. }
  348. return 0;
  349. }
  350. static void sh_mmcif_get_response(struct sh_mmcif_host *host,
  351. struct mmc_command *cmd)
  352. {
  353. if (cmd->flags & MMC_RSP_136) {
  354. cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
  355. cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
  356. cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
  357. cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
  358. } else
  359. cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
  360. }
  361. static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
  362. struct mmc_command *cmd)
  363. {
  364. cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
  365. }
  366. static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
  367. struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
  368. {
  369. u32 tmp = 0;
  370. /* Response Type check */
  371. switch (mmc_resp_type(cmd)) {
  372. case MMC_RSP_NONE:
  373. tmp |= CMD_SET_RTYP_NO;
  374. break;
  375. case MMC_RSP_R1:
  376. case MMC_RSP_R1B:
  377. case MMC_RSP_R3:
  378. tmp |= CMD_SET_RTYP_6B;
  379. break;
  380. case MMC_RSP_R2:
  381. tmp |= CMD_SET_RTYP_17B;
  382. break;
  383. default:
  384. pr_err(DRIVER_NAME": Not support type response.\n");
  385. break;
  386. }
  387. switch (opc) {
  388. /* RBSY */
  389. case MMC_SWITCH:
  390. case MMC_STOP_TRANSMISSION:
  391. case MMC_SET_WRITE_PROT:
  392. case MMC_CLR_WRITE_PROT:
  393. case MMC_ERASE:
  394. case MMC_GEN_CMD:
  395. tmp |= CMD_SET_RBSY;
  396. break;
  397. }
  398. /* WDAT / DATW */
  399. if (host->data) {
  400. tmp |= CMD_SET_WDAT;
  401. switch (host->bus_width) {
  402. case MMC_BUS_WIDTH_1:
  403. tmp |= CMD_SET_DATW_1;
  404. break;
  405. case MMC_BUS_WIDTH_4:
  406. tmp |= CMD_SET_DATW_4;
  407. break;
  408. case MMC_BUS_WIDTH_8:
  409. tmp |= CMD_SET_DATW_8;
  410. break;
  411. default:
  412. pr_err(DRIVER_NAME": Not support bus width.\n");
  413. break;
  414. }
  415. }
  416. /* DWEN */
  417. if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
  418. tmp |= CMD_SET_DWEN;
  419. /* CMLTE/CMD12EN */
  420. if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
  421. tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
  422. sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
  423. mrq->data->blocks << 16);
  424. }
  425. /* RIDXC[1:0] check bits */
  426. if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
  427. opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
  428. tmp |= CMD_SET_RIDXC_BITS;
  429. /* RCRC7C[1:0] check bits */
  430. if (opc == MMC_SEND_OP_COND)
  431. tmp |= CMD_SET_CRC7C_BITS;
  432. /* RCRC7C[1:0] internal CRC7 */
  433. if (opc == MMC_ALL_SEND_CID ||
  434. opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
  435. tmp |= CMD_SET_CRC7C_INTERNAL;
  436. return opc = ((opc << 24) | tmp);
  437. }
  438. static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
  439. struct mmc_request *mrq, u32 opc)
  440. {
  441. u32 ret;
  442. switch (opc) {
  443. case MMC_READ_MULTIPLE_BLOCK:
  444. ret = sh_mmcif_multi_read(host, mrq);
  445. break;
  446. case MMC_WRITE_MULTIPLE_BLOCK:
  447. ret = sh_mmcif_multi_write(host, mrq);
  448. break;
  449. case MMC_WRITE_BLOCK:
  450. ret = sh_mmcif_single_write(host, mrq);
  451. break;
  452. case MMC_READ_SINGLE_BLOCK:
  453. case MMC_SEND_EXT_CSD:
  454. ret = sh_mmcif_single_read(host, mrq);
  455. break;
  456. default:
  457. pr_err(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
  458. ret = -EINVAL;
  459. break;
  460. }
  461. return ret;
  462. }
  463. static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
  464. struct mmc_request *mrq, struct mmc_command *cmd)
  465. {
  466. long time;
  467. int ret = 0, mask = 0;
  468. u32 opc = cmd->opcode;
  469. host->cmd = cmd;
  470. switch (opc) {
  471. /* respons busy check */
  472. case MMC_SWITCH:
  473. case MMC_STOP_TRANSMISSION:
  474. case MMC_SET_WRITE_PROT:
  475. case MMC_CLR_WRITE_PROT:
  476. case MMC_ERASE:
  477. case MMC_GEN_CMD:
  478. mask = MASK_MRBSYE;
  479. break;
  480. default:
  481. mask = MASK_MCRSPE;
  482. break;
  483. }
  484. mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
  485. MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
  486. MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
  487. MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
  488. if (host->data) {
  489. sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
  490. sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
  491. mrq->data->blksz);
  492. }
  493. opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
  494. sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
  495. sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
  496. /* set arg */
  497. sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
  498. host->wait_int = 0;
  499. /* set cmd */
  500. sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
  501. time = wait_event_interruptible_timeout(host->intr_wait,
  502. host->wait_int == 1 || host->sd_error == 1, host->timeout);
  503. if (host->wait_int != 1 && time == 0) {
  504. cmd->error = sh_mmcif_error_manage(host);
  505. return;
  506. }
  507. if (host->sd_error) {
  508. switch (cmd->opcode) {
  509. case MMC_ALL_SEND_CID:
  510. case MMC_SELECT_CARD:
  511. case MMC_APP_CMD:
  512. cmd->error = -ETIMEDOUT;
  513. break;
  514. default:
  515. pr_debug("%s: Cmd(d'%d) err\n",
  516. DRIVER_NAME, cmd->opcode);
  517. cmd->error = sh_mmcif_error_manage(host);
  518. break;
  519. }
  520. host->sd_error = 0;
  521. host->wait_int = 0;
  522. return;
  523. }
  524. if (!(cmd->flags & MMC_RSP_PRESENT)) {
  525. cmd->error = ret;
  526. host->wait_int = 0;
  527. return;
  528. }
  529. if (host->wait_int == 1) {
  530. sh_mmcif_get_response(host, cmd);
  531. host->wait_int = 0;
  532. }
  533. if (host->data) {
  534. ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
  535. if (ret < 0)
  536. mrq->data->bytes_xfered = 0;
  537. else
  538. mrq->data->bytes_xfered =
  539. mrq->data->blocks * mrq->data->blksz;
  540. }
  541. cmd->error = ret;
  542. }
  543. static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
  544. struct mmc_request *mrq, struct mmc_command *cmd)
  545. {
  546. long time;
  547. if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
  548. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
  549. else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
  550. sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
  551. else {
  552. pr_err(DRIVER_NAME": not support stop cmd\n");
  553. cmd->error = sh_mmcif_error_manage(host);
  554. return;
  555. }
  556. time = wait_event_interruptible_timeout(host->intr_wait,
  557. host->wait_int == 1 ||
  558. host->sd_error == 1, host->timeout);
  559. if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) {
  560. cmd->error = sh_mmcif_error_manage(host);
  561. return;
  562. }
  563. sh_mmcif_get_cmd12response(host, cmd);
  564. host->wait_int = 0;
  565. cmd->error = 0;
  566. }
  567. static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
  568. {
  569. struct sh_mmcif_host *host = mmc_priv(mmc);
  570. switch (mrq->cmd->opcode) {
  571. /* MMCIF does not support SD/SDIO command */
  572. case SD_IO_SEND_OP_COND:
  573. case MMC_APP_CMD:
  574. mrq->cmd->error = -ETIMEDOUT;
  575. mmc_request_done(mmc, mrq);
  576. return;
  577. case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
  578. if (!mrq->data) {
  579. /* send_if_cond cmd (not support) */
  580. mrq->cmd->error = -ETIMEDOUT;
  581. mmc_request_done(mmc, mrq);
  582. return;
  583. }
  584. break;
  585. default:
  586. break;
  587. }
  588. host->data = mrq->data;
  589. sh_mmcif_start_cmd(host, mrq, mrq->cmd);
  590. host->data = NULL;
  591. if (mrq->cmd->error != 0) {
  592. mmc_request_done(mmc, mrq);
  593. return;
  594. }
  595. if (mrq->stop)
  596. sh_mmcif_stop_cmd(host, mrq, mrq->stop);
  597. mmc_request_done(mmc, mrq);
  598. }
  599. static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  600. {
  601. struct sh_mmcif_host *host = mmc_priv(mmc);
  602. struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
  603. if (ios->power_mode == MMC_POWER_OFF) {
  604. /* clock stop */
  605. sh_mmcif_clock_control(host, 0);
  606. if (p->down_pwr)
  607. p->down_pwr(host->pd);
  608. return;
  609. } else if (ios->power_mode == MMC_POWER_UP) {
  610. if (p->set_pwr)
  611. p->set_pwr(host->pd, ios->power_mode);
  612. }
  613. if (ios->clock)
  614. sh_mmcif_clock_control(host, ios->clock);
  615. host->bus_width = ios->bus_width;
  616. }
  617. static int sh_mmcif_get_cd(struct mmc_host *mmc)
  618. {
  619. struct sh_mmcif_host *host = mmc_priv(mmc);
  620. struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
  621. if (!p->get_cd)
  622. return -ENOSYS;
  623. else
  624. return p->get_cd(host->pd);
  625. }
  626. static struct mmc_host_ops sh_mmcif_ops = {
  627. .request = sh_mmcif_request,
  628. .set_ios = sh_mmcif_set_ios,
  629. .get_cd = sh_mmcif_get_cd,
  630. };
  631. static void sh_mmcif_detect(struct mmc_host *mmc)
  632. {
  633. mmc_detect_change(mmc, 0);
  634. }
  635. static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
  636. {
  637. struct sh_mmcif_host *host = dev_id;
  638. u32 state = 0;
  639. int err = 0;
  640. state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
  641. if (state & INT_RBSYE) {
  642. sh_mmcif_writel(host->addr, MMCIF_CE_INT,
  643. ~(INT_RBSYE | INT_CRSPE));
  644. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
  645. } else if (state & INT_CRSPE) {
  646. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
  647. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
  648. } else if (state & INT_BUFREN) {
  649. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
  650. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
  651. } else if (state & INT_BUFWEN) {
  652. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
  653. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
  654. } else if (state & INT_CMD12DRE) {
  655. sh_mmcif_writel(host->addr, MMCIF_CE_INT,
  656. ~(INT_CMD12DRE | INT_CMD12RBE |
  657. INT_CMD12CRE | INT_BUFRE));
  658. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
  659. } else if (state & INT_BUFRE) {
  660. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
  661. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
  662. } else if (state & INT_DTRANE) {
  663. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
  664. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
  665. } else if (state & INT_CMD12RBE) {
  666. sh_mmcif_writel(host->addr, MMCIF_CE_INT,
  667. ~(INT_CMD12RBE | INT_CMD12CRE));
  668. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
  669. } else if (state & INT_ERR_STS) {
  670. /* err interrupts */
  671. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
  672. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
  673. err = 1;
  674. } else {
  675. pr_debug("%s: Not support int\n", DRIVER_NAME);
  676. sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
  677. sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
  678. err = 1;
  679. }
  680. if (err) {
  681. host->sd_error = 1;
  682. pr_debug("%s: int err state = %08x\n", DRIVER_NAME, state);
  683. }
  684. host->wait_int = 1;
  685. wake_up(&host->intr_wait);
  686. return IRQ_HANDLED;
  687. }
  688. static int __devinit sh_mmcif_probe(struct platform_device *pdev)
  689. {
  690. int ret = 0, irq[2];
  691. struct mmc_host *mmc;
  692. struct sh_mmcif_host *host = NULL;
  693. struct sh_mmcif_plat_data *pd = NULL;
  694. struct resource *res;
  695. void __iomem *reg;
  696. char clk_name[8];
  697. irq[0] = platform_get_irq(pdev, 0);
  698. irq[1] = platform_get_irq(pdev, 1);
  699. if (irq[0] < 0 || irq[1] < 0) {
  700. pr_err(DRIVER_NAME": Get irq error\n");
  701. return -ENXIO;
  702. }
  703. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  704. if (!res) {
  705. dev_err(&pdev->dev, "platform_get_resource error.\n");
  706. return -ENXIO;
  707. }
  708. reg = ioremap(res->start, resource_size(res));
  709. if (!reg) {
  710. dev_err(&pdev->dev, "ioremap error.\n");
  711. return -ENOMEM;
  712. }
  713. pd = (struct sh_mmcif_plat_data *)(pdev->dev.platform_data);
  714. if (!pd) {
  715. dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
  716. ret = -ENXIO;
  717. goto clean_up;
  718. }
  719. mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
  720. if (!mmc) {
  721. ret = -ENOMEM;
  722. goto clean_up;
  723. }
  724. host = mmc_priv(mmc);
  725. host->mmc = mmc;
  726. host->addr = reg;
  727. host->timeout = 1000;
  728. snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
  729. host->hclk = clk_get(&pdev->dev, clk_name);
  730. if (IS_ERR(host->hclk)) {
  731. dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
  732. ret = PTR_ERR(host->hclk);
  733. goto clean_up1;
  734. }
  735. clk_enable(host->hclk);
  736. host->clk = clk_get_rate(host->hclk);
  737. host->pd = pdev;
  738. init_waitqueue_head(&host->intr_wait);
  739. mmc->ops = &sh_mmcif_ops;
  740. mmc->f_max = host->clk;
  741. /* close to 400KHz */
  742. if (mmc->f_max < 51200000)
  743. mmc->f_min = mmc->f_max / 128;
  744. else if (mmc->f_max < 102400000)
  745. mmc->f_min = mmc->f_max / 256;
  746. else
  747. mmc->f_min = mmc->f_max / 512;
  748. if (pd->ocr)
  749. mmc->ocr_avail = pd->ocr;
  750. mmc->caps = MMC_CAP_MMC_HIGHSPEED;
  751. if (pd->caps)
  752. mmc->caps |= pd->caps;
  753. mmc->max_segs = 128;
  754. mmc->max_blk_size = 512;
  755. mmc->max_blk_count = 65535;
  756. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  757. mmc->max_seg_size = mmc->max_req_size;
  758. sh_mmcif_sync_reset(host);
  759. platform_set_drvdata(pdev, host);
  760. mmc_add_host(mmc);
  761. ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
  762. if (ret) {
  763. pr_err(DRIVER_NAME": request_irq error (sh_mmc:error)\n");
  764. goto clean_up2;
  765. }
  766. ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
  767. if (ret) {
  768. free_irq(irq[0], host);
  769. pr_err(DRIVER_NAME": request_irq error (sh_mmc:int)\n");
  770. goto clean_up2;
  771. }
  772. sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
  773. sh_mmcif_detect(host->mmc);
  774. pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
  775. pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
  776. sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
  777. return ret;
  778. clean_up2:
  779. clk_disable(host->hclk);
  780. clean_up1:
  781. mmc_free_host(mmc);
  782. clean_up:
  783. if (reg)
  784. iounmap(reg);
  785. return ret;
  786. }
  787. static int __devexit sh_mmcif_remove(struct platform_device *pdev)
  788. {
  789. struct sh_mmcif_host *host = platform_get_drvdata(pdev);
  790. int irq[2];
  791. sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
  792. irq[0] = platform_get_irq(pdev, 0);
  793. irq[1] = platform_get_irq(pdev, 1);
  794. if (host->addr)
  795. iounmap(host->addr);
  796. platform_set_drvdata(pdev, NULL);
  797. mmc_remove_host(host->mmc);
  798. free_irq(irq[0], host);
  799. free_irq(irq[1], host);
  800. clk_disable(host->hclk);
  801. mmc_free_host(host->mmc);
  802. return 0;
  803. }
  804. static struct platform_driver sh_mmcif_driver = {
  805. .probe = sh_mmcif_probe,
  806. .remove = sh_mmcif_remove,
  807. .driver = {
  808. .name = DRIVER_NAME,
  809. },
  810. };
  811. static int __init sh_mmcif_init(void)
  812. {
  813. return platform_driver_register(&sh_mmcif_driver);
  814. }
  815. static void __exit sh_mmcif_exit(void)
  816. {
  817. platform_driver_unregister(&sh_mmcif_driver);
  818. }
  819. module_init(sh_mmcif_init);
  820. module_exit(sh_mmcif_exit);
  821. MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
  822. MODULE_LICENSE("GPL");
  823. MODULE_ALIAS(DRIVER_NAME);
  824. MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");