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asm-arm
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arch-orion
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orion.h

orion.h 6.7 KB
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  1. /*
    2. 

  2.  * include/asm-arm/arch-orion/orion.h
    3. 

  3.  *
    4. 

  4.  * Generic definitions of Orion SoC flavors:
    5. 

  5.  *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
    6. 

  6.  *
    7. 

  7.  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
    8. 

  8.  *
    9. 

  9.  * This file is licensed under the terms of the GNU General Public
    10. 

  10.  * License version 2. This program is licensed "as is" without any
    11. 

  11.  * warranty of any kind, whether express or implied.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef __ASM_ARCH_ORION_H__
    15. 

  15. #define __ASM_ARCH_ORION_H__
    16. 

  16. 

  17. /*****************************************************************************
    18. 

  18.  * Orion Address Maps
    19. 

  19.  *
    20. 

  20.  * phys
    21. 

  21.  * e0000000	PCIe MEM space
    22. 

  22.  * e8000000	PCI MEM space
    23. 

  23.  * f0000000	PCIe WA space (Orion-1/Orion-NAS only)
    24. 

  24.  * f1000000	on-chip peripheral registers
    25. 

  25.  * f2000000	PCIe I/O space
    26. 

  26.  * f2100000	PCI I/O space
    27. 

  27.  * f4000000	device bus mappings (boot)
    28. 

  28.  * fa000000	device bus mappings (cs0)
    29. 

  29.  * fa800000	device bus mappings (cs2)
    30. 

  30.  * fc000000	device bus mappings (cs0/cs1)
    31. 

  31.  *
    32. 

  32.  * virt		phys		size
    33. 

  33.  * fdd00000	f1000000	1M	on-chip peripheral registers
    34. 

  34.  * fde00000	f2000000	1M	PCIe I/O space
    35. 

  35.  * fdf00000	f2100000	1M	PCI I/O space
    36. 

  36.  * fe000000	f0000000	16M	PCIe WA space (Orion-1/Orion-NAS only)
    37. 

  37.  ****************************************************************************/
    38. 

  38. #define ORION_REGS_PHYS_BASE	0xf1000000
    39. 

  39. #define ORION_REGS_VIRT_BASE	0xfdd00000
    40. 

  40. #define ORION_REGS_SIZE		SZ_1M
    41. 

  41. 

  42. #define ORION_PCIE_IO_PHYS_BASE	0xf2000000
    43. 

  43. #define ORION_PCIE_IO_VIRT_BASE	0xfde00000
    44. 

  44. #define ORION_PCIE_IO_BUS_BASE	0x00000000
    45. 

  45. #define ORION_PCIE_IO_SIZE	SZ_1M
    46. 

  46. 

  47. #define ORION_PCI_IO_PHYS_BASE	0xf2100000
    48. 

  48. #define ORION_PCI_IO_VIRT_BASE	0xfdf00000
    49. 

  49. #define ORION_PCI_IO_BUS_BASE	0x00100000
    50. 

  50. #define ORION_PCI_IO_SIZE	SZ_1M
    51. 

  51. 

  52. /* Relevant only for Orion-1/Orion-NAS */
    53. 

  53. #define ORION_PCIE_WA_PHYS_BASE	0xf0000000
    54. 

  54. #define ORION_PCIE_WA_VIRT_BASE	0xfe000000
    55. 

  55. #define ORION_PCIE_WA_SIZE	SZ_16M
    56. 

  56. 

  57. #define ORION_PCIE_MEM_PHYS_BASE	0xe0000000
    58. 

  58. #define ORION_PCIE_MEM_SIZE		SZ_128M
    59. 

  59. 

  60. #define ORION_PCI_MEM_PHYS_BASE		0xe8000000
    61. 

  61. #define ORION_PCI_MEM_SIZE		SZ_128M
    62. 

  62. 

  63. /*******************************************************************************
    64. 

  64.  * Supported Devices & Revisions
    65. 

  65.  ******************************************************************************/
    66. 

  66. /* Orion-1 (88F5181) */
    67. 

  67. #define MV88F5181_DEV_ID	0x5181
    68. 

  68. #define MV88F5181_REV_B1	3
    69. 

  69. /* Orion-NAS (88F5182) */
    70. 

  70. #define MV88F5182_DEV_ID	0x5182
    71. 

  71. #define MV88F5182_REV_A2	2
    72. 

  72. /* Orion-2 (88F5281) */
    73. 

  73. #define MV88F5281_DEV_ID	0x5281
    74. 

  74. #define MV88F5281_REV_D1	5
    75. 

  75. #define MV88F5281_REV_D2	6
    76. 

  76. 

  77. /*******************************************************************************
    78. 

  78.  * Orion Registers Map
    79. 

  79.  ******************************************************************************/
    80. 

  80. #define ORION_DDR_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x00000)
    81. 

  81. #define ORION_DDR_REG(x)		(ORION_DDR_VIRT_BASE | (x))
    82. 

  82. 

  83. #define ORION_DEV_BUS_PHYS_BASE		(ORION_REGS_PHYS_BASE | 0x10000)
    84. 

  84. #define ORION_DEV_BUS_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x10000)
    85. 

  85. #define ORION_DEV_BUS_REG(x)		(ORION_DEV_BUS_VIRT_BASE | (x))
    86. 

  86. #define  I2C_PHYS_BASE			(ORION_DEV_BUS_PHYS_BASE | 0x1000)
    87. 

  87. #define  UART0_PHYS_BASE		(ORION_DEV_BUS_PHYS_BASE | 0x2000)
    88. 

  88. #define  UART0_VIRT_BASE		(ORION_DEV_BUS_VIRT_BASE | 0x2000)
    89. 

  89. #define  UART1_PHYS_BASE		(ORION_DEV_BUS_PHYS_BASE | 0x2100)
    90. 

  90. #define  UART1_VIRT_BASE		(ORION_DEV_BUS_VIRT_BASE | 0x2100)
    91. 

  91. 

  92. #define ORION_BRIDGE_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x20000)
    93. 

  93. #define ORION_BRIDGE_REG(x)		(ORION_BRIDGE_VIRT_BASE | (x))
    94. 

  94. 

  95. #define ORION_PCI_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x30000)
    96. 

  96. #define ORION_PCI_REG(x)		(ORION_PCI_VIRT_BASE | (x))
    97. 

  97. 

  98. #define ORION_PCIE_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x40000)
    99. 

  99. #define ORION_PCIE_REG(x)		(ORION_PCIE_VIRT_BASE | (x))
    100. 

  100. 

  101. #define ORION_USB0_PHYS_BASE		(ORION_REGS_PHYS_BASE | 0x50000)
    102. 

  102. #define ORION_USB0_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x50000)
    103. 

  103. #define ORION_USB0_REG(x)		(ORION_USB0_VIRT_BASE | (x))
    104. 

  104. 

  105. #define ORION_ETH_PHYS_BASE		(ORION_REGS_PHYS_BASE | 0x70000)
    106. 

  106. #define ORION_ETH_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x70000)
    107. 

  107. #define ORION_ETH_REG(x)		(ORION_ETH_VIRT_BASE | (x))
    108. 

  108. 

  109. #define ORION_SATA_PHYS_BASE		(ORION_REGS_PHYS_BASE | 0x80000)
    110. 

  110. #define ORION_SATA_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0x80000)
    111. 

  111. #define ORION_SATA_REG(x)		(ORION_SATA_VIRT_BASE | (x))
    112. 

  112. 

  113. #define ORION_USB1_PHYS_BASE		(ORION_REGS_PHYS_BASE | 0xa0000)
    114. 

  114. #define ORION_USB1_VIRT_BASE		(ORION_REGS_VIRT_BASE | 0xa0000)
    115. 

  115. #define ORION_USB1_REG(x)		(ORION_USB1_VIRT_BASE | (x))
    116. 

  116. 

  117. /*******************************************************************************
    118. 

  118.  * Device Bus Registers
    119. 

  119.  ******************************************************************************/
    120. 

  120. #define MPP_0_7_CTRL		ORION_DEV_BUS_REG(0x000)
    121. 

  121. #define MPP_8_15_CTRL		ORION_DEV_BUS_REG(0x004)
    122. 

  122. #define MPP_16_19_CTRL		ORION_DEV_BUS_REG(0x050)
    123. 

  123. #define MPP_DEV_CTRL		ORION_DEV_BUS_REG(0x008)
    124. 

  124. #define MPP_RESET_SAMPLE	ORION_DEV_BUS_REG(0x010)
    125. 

  125. #define GPIO_OUT		ORION_DEV_BUS_REG(0x100)
    126. 

  126. #define GPIO_IO_CONF		ORION_DEV_BUS_REG(0x104)
    127. 

  127. #define GPIO_BLINK_EN		ORION_DEV_BUS_REG(0x108)
    128. 

  128. #define GPIO_IN_POL		ORION_DEV_BUS_REG(0x10c)
    129. 

  129. #define GPIO_DATA_IN		ORION_DEV_BUS_REG(0x110)
    130. 

  130. #define GPIO_EDGE_CAUSE		ORION_DEV_BUS_REG(0x114)
    131. 

  131. #define GPIO_EDGE_MASK		ORION_DEV_BUS_REG(0x118)
    132. 

  132. #define GPIO_LEVEL_MASK		ORION_DEV_BUS_REG(0x11c)
    133. 

  133. #define DEV_BANK_0_PARAM	ORION_DEV_BUS_REG(0x45c)
    134. 

  134. #define DEV_BANK_1_PARAM	ORION_DEV_BUS_REG(0x460)
    135. 

  135. #define DEV_BANK_2_PARAM	ORION_DEV_BUS_REG(0x464)
    136. 

  136. #define DEV_BANK_BOOT_PARAM	ORION_DEV_BUS_REG(0x46c)
    137. 

  137. #define DEV_BUS_CTRL		ORION_DEV_BUS_REG(0x4c0)
    138. 

  138. #define DEV_BUS_INT_CAUSE	ORION_DEV_BUS_REG(0x4d0)
    139. 

  139. #define DEV_BUS_INT_MASK	ORION_DEV_BUS_REG(0x4d4)
    140. 

  140. #define GPIO_MAX		32
    141. 

  141. 

  142. /***************************************************************************
    143. 

  143.  * Orion CPU Bridge Registers
    144. 

  144.  **************************************************************************/
    145. 

  145. #define CPU_CONF		ORION_BRIDGE_REG(0x100)
    146. 

  146. #define CPU_CTRL		ORION_BRIDGE_REG(0x104)
    147. 

  147. #define CPU_RESET_MASK		ORION_BRIDGE_REG(0x108)
    148. 

  148. #define CPU_SOFT_RESET		ORION_BRIDGE_REG(0x10c)
    149. 

  149. #define POWER_MNG_CTRL_REG	ORION_BRIDGE_REG(0x11C)
    150. 

  150. #define BRIDGE_CAUSE		ORION_BRIDGE_REG(0x110)
    151. 

  151. #define BRIDGE_MASK		ORION_BRIDGE_REG(0x114)
    152. 

  152. #define  BRIDGE_INT_TIMER0	0x0002
    153. 

  153. #define  BRIDGE_INT_TIMER1	0x0004
    154. 

  154. #define MAIN_IRQ_CAUSE		ORION_BRIDGE_REG(0x200)
    155. 

  155. #define MAIN_IRQ_MASK		ORION_BRIDGE_REG(0x204)
    156. 

  156. 

  157. #define TIMER_VIRT_BASE		(ORION_BRIDGE_VIRT_BASE | 0x300)
    158. 

  158. 

  159. #ifndef __ASSEMBLY__
    160. 

  160. 

  161. /*******************************************************************************
    162. 

  162.  * Helpers to access Orion registers
    163. 

  163.  ******************************************************************************/
    164. 

  164. #include <asm/types.h>
    165. 

  165. #include <asm/io.h>
    166. 

  166. 

  167. #define orion_read(r)		__raw_readl(r)
    168. 

  168. #define orion_write(r, val)	__raw_writel(val, r)
    169. 

  169. 

  170. /*
    171. 

  171.  * These are not preempt safe. Locks, if needed, must be taken care by caller.
    172. 

  172.  */
    173. 

  173. #define orion_setbits(r, mask)	orion_write((r), orion_read(r) | (mask))
    174. 

  174. #define orion_clrbits(r, mask)	orion_write((r), orion_read(r) & ~(mask))
    175. 

  175. 

  176. #endif /* __ASSEMBLY__ */
    177. 

  177. 

  178. #endif /* __ASM_ARCH_ORION_H__ */
    179.