xhci-hub.c 21 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <asm/unaligned.h>
  23. #include "xhci.h"
  24. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  25. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  26. PORT_RC | PORT_PLC | PORT_PE)
  27. static void xhci_hub_descriptor(struct xhci_hcd *xhci,
  28. struct usb_hub_descriptor *desc)
  29. {
  30. int ports;
  31. u16 temp;
  32. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  33. /* USB 3.0 hubs have a different descriptor, but we fake this for now */
  34. desc->bDescriptorType = 0x29;
  35. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  36. desc->bHubContrCurrent = 0;
  37. desc->bNbrPorts = ports;
  38. temp = 1 + (ports / 8);
  39. desc->bDescLength = 7 + 2 * temp;
  40. memset(&desc->DeviceRemovable[0], 0, temp);
  41. memset(&desc->DeviceRemovable[temp], 0xff, temp);
  42. /* Ugh, these should be #defines, FIXME */
  43. /* Using table 11-13 in USB 2.0 spec. */
  44. temp = 0;
  45. /* Bits 1:0 - support port power switching, or power always on */
  46. if (HCC_PPC(xhci->hcc_params))
  47. temp |= 0x0001;
  48. else
  49. temp |= 0x0002;
  50. /* Bit 2 - root hubs are not part of a compound device */
  51. /* Bits 4:3 - individual port over current protection */
  52. temp |= 0x0008;
  53. /* Bits 6:5 - no TTs in root ports */
  54. /* Bit 7 - no port indicators */
  55. desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
  56. }
  57. static unsigned int xhci_port_speed(unsigned int port_status)
  58. {
  59. if (DEV_LOWSPEED(port_status))
  60. return USB_PORT_STAT_LOW_SPEED;
  61. if (DEV_HIGHSPEED(port_status))
  62. return USB_PORT_STAT_HIGH_SPEED;
  63. if (DEV_SUPERSPEED(port_status))
  64. return USB_PORT_STAT_SUPER_SPEED;
  65. /*
  66. * FIXME: Yes, we should check for full speed, but the core uses that as
  67. * a default in portspeed() in usb/core/hub.c (which is the only place
  68. * USB_PORT_STAT_*_SPEED is used).
  69. */
  70. return 0;
  71. }
  72. /*
  73. * These bits are Read Only (RO) and should be saved and written to the
  74. * registers: 0, 3, 10:13, 30
  75. * connect status, over-current status, port speed, and device removable.
  76. * connect status and port speed are also sticky - meaning they're in
  77. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  78. */
  79. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  80. /*
  81. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  82. * bits 5:8, 9, 14:15, 25:27
  83. * link state, port power, port indicator state, "wake on" enable state
  84. */
  85. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  86. /*
  87. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  88. * bit 4 (port reset)
  89. */
  90. #define XHCI_PORT_RW1S ((1<<4))
  91. /*
  92. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  93. * bits 1, 17, 18, 19, 20, 21, 22, 23
  94. * port enable/disable, and
  95. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  96. * over-current, reset, link state, and L1 change
  97. */
  98. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  99. /*
  100. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  101. * latched in
  102. */
  103. #define XHCI_PORT_RW ((1<<16))
  104. /*
  105. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  106. * bits 2, 24, 28:31
  107. */
  108. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  109. /*
  110. * Given a port state, this function returns a value that would result in the
  111. * port being in the same state, if the value was written to the port status
  112. * control register.
  113. * Save Read Only (RO) bits and save read/write bits where
  114. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  115. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  116. */
  117. u32 xhci_port_state_to_neutral(u32 state)
  118. {
  119. /* Save read-only status and port state */
  120. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  121. }
  122. /*
  123. * find slot id based on port number.
  124. */
  125. int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port)
  126. {
  127. int slot_id;
  128. int i;
  129. slot_id = 0;
  130. for (i = 0; i < MAX_HC_SLOTS; i++) {
  131. if (!xhci->devs[i])
  132. continue;
  133. if (xhci->devs[i]->port == port) {
  134. slot_id = i;
  135. break;
  136. }
  137. }
  138. return slot_id;
  139. }
  140. /*
  141. * Stop device
  142. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  143. * to complete.
  144. * suspend will set to 1, if suspend bit need to set in command.
  145. */
  146. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  147. {
  148. struct xhci_virt_device *virt_dev;
  149. struct xhci_command *cmd;
  150. unsigned long flags;
  151. int timeleft;
  152. int ret;
  153. int i;
  154. ret = 0;
  155. virt_dev = xhci->devs[slot_id];
  156. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  157. if (!cmd) {
  158. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  159. return -ENOMEM;
  160. }
  161. spin_lock_irqsave(&xhci->lock, flags);
  162. for (i = LAST_EP_INDEX; i > 0; i--) {
  163. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  164. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  165. }
  166. cmd->command_trb = xhci->cmd_ring->enqueue;
  167. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  168. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  169. xhci_ring_cmd_db(xhci);
  170. spin_unlock_irqrestore(&xhci->lock, flags);
  171. /* Wait for last stop endpoint command to finish */
  172. timeleft = wait_for_completion_interruptible_timeout(
  173. cmd->completion,
  174. USB_CTRL_SET_TIMEOUT);
  175. if (timeleft <= 0) {
  176. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  177. timeleft == 0 ? "Timeout" : "Signal");
  178. spin_lock_irqsave(&xhci->lock, flags);
  179. /* The timeout might have raced with the event ring handler, so
  180. * only delete from the list if the item isn't poisoned.
  181. */
  182. if (cmd->cmd_list.next != LIST_POISON1)
  183. list_del(&cmd->cmd_list);
  184. spin_unlock_irqrestore(&xhci->lock, flags);
  185. ret = -ETIME;
  186. goto command_cleanup;
  187. }
  188. command_cleanup:
  189. xhci_free_command(xhci, cmd);
  190. return ret;
  191. }
  192. /*
  193. * Ring device, it rings the all doorbells unconditionally.
  194. */
  195. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  196. {
  197. int i;
  198. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  199. if (xhci->devs[slot_id]->eps[i].ring &&
  200. xhci->devs[slot_id]->eps[i].ring->dequeue)
  201. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  202. return;
  203. }
  204. static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex,
  205. u32 __iomem *addr, u32 port_status)
  206. {
  207. /* Don't allow the USB core to disable SuperSpeed ports. */
  208. if (xhci->port_array[wIndex] == 0x03) {
  209. xhci_dbg(xhci, "Ignoring request to disable "
  210. "SuperSpeed port.\n");
  211. return;
  212. }
  213. /* Write 1 to disable the port */
  214. xhci_writel(xhci, port_status | PORT_PE, addr);
  215. port_status = xhci_readl(xhci, addr);
  216. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  217. wIndex, port_status);
  218. }
  219. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  220. u16 wIndex, u32 __iomem *addr, u32 port_status)
  221. {
  222. char *port_change_bit;
  223. u32 status;
  224. switch (wValue) {
  225. case USB_PORT_FEAT_C_RESET:
  226. status = PORT_RC;
  227. port_change_bit = "reset";
  228. break;
  229. case USB_PORT_FEAT_C_CONNECTION:
  230. status = PORT_CSC;
  231. port_change_bit = "connect";
  232. break;
  233. case USB_PORT_FEAT_C_OVER_CURRENT:
  234. status = PORT_OCC;
  235. port_change_bit = "over-current";
  236. break;
  237. case USB_PORT_FEAT_C_ENABLE:
  238. status = PORT_PEC;
  239. port_change_bit = "enable/disable";
  240. break;
  241. case USB_PORT_FEAT_C_SUSPEND:
  242. status = PORT_PLC;
  243. port_change_bit = "suspend/resume";
  244. break;
  245. default:
  246. /* Should never happen */
  247. return;
  248. }
  249. /* Change bits are all write 1 to clear */
  250. xhci_writel(xhci, port_status | status, addr);
  251. port_status = xhci_readl(xhci, addr);
  252. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  253. port_change_bit, wIndex, port_status);
  254. }
  255. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  256. u16 wIndex, char *buf, u16 wLength)
  257. {
  258. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  259. int ports;
  260. unsigned long flags;
  261. u32 temp, temp1, status;
  262. int retval = 0;
  263. u32 __iomem *addr;
  264. int slot_id;
  265. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  266. spin_lock_irqsave(&xhci->lock, flags);
  267. switch (typeReq) {
  268. case GetHubStatus:
  269. /* No power source, over-current reported per port */
  270. memset(buf, 0, 4);
  271. break;
  272. case GetHubDescriptor:
  273. xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf);
  274. break;
  275. case GetPortStatus:
  276. if (!wIndex || wIndex > ports)
  277. goto error;
  278. wIndex--;
  279. status = 0;
  280. addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
  281. temp = xhci_readl(xhci, addr);
  282. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
  283. /* wPortChange bits */
  284. if (temp & PORT_CSC)
  285. status |= USB_PORT_STAT_C_CONNECTION << 16;
  286. if (temp & PORT_PEC)
  287. status |= USB_PORT_STAT_C_ENABLE << 16;
  288. if ((temp & PORT_OCC))
  289. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  290. /*
  291. * FIXME ignoring reset and USB 2.1/3.0 specific
  292. * changes
  293. */
  294. if ((temp & PORT_PLS_MASK) == XDEV_U3
  295. && (temp & PORT_POWER))
  296. status |= 1 << USB_PORT_FEAT_SUSPEND;
  297. if ((temp & PORT_PLS_MASK) == XDEV_RESUME) {
  298. if ((temp & PORT_RESET) || !(temp & PORT_PE))
  299. goto error;
  300. if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies,
  301. xhci->resume_done[wIndex])) {
  302. xhci_dbg(xhci, "Resume USB2 port %d\n",
  303. wIndex + 1);
  304. xhci->resume_done[wIndex] = 0;
  305. temp1 = xhci_port_state_to_neutral(temp);
  306. temp1 &= ~PORT_PLS_MASK;
  307. temp1 |= PORT_LINK_STROBE | XDEV_U0;
  308. xhci_writel(xhci, temp1, addr);
  309. xhci_dbg(xhci, "set port %d resume\n",
  310. wIndex + 1);
  311. slot_id = xhci_find_slot_id_by_port(xhci,
  312. wIndex + 1);
  313. if (!slot_id) {
  314. xhci_dbg(xhci, "slot_id is zero\n");
  315. goto error;
  316. }
  317. xhci_ring_device(xhci, slot_id);
  318. xhci->port_c_suspend[wIndex >> 5] |=
  319. 1 << (wIndex & 31);
  320. xhci->suspended_ports[wIndex >> 5] &=
  321. ~(1 << (wIndex & 31));
  322. }
  323. }
  324. if ((temp & PORT_PLS_MASK) == XDEV_U0
  325. && (temp & PORT_POWER)
  326. && (xhci->suspended_ports[wIndex >> 5] &
  327. (1 << (wIndex & 31)))) {
  328. xhci->suspended_ports[wIndex >> 5] &=
  329. ~(1 << (wIndex & 31));
  330. xhci->port_c_suspend[wIndex >> 5] |=
  331. 1 << (wIndex & 31);
  332. }
  333. if (temp & PORT_CONNECT) {
  334. status |= USB_PORT_STAT_CONNECTION;
  335. status |= xhci_port_speed(temp);
  336. }
  337. if (temp & PORT_PE)
  338. status |= USB_PORT_STAT_ENABLE;
  339. if (temp & PORT_OC)
  340. status |= USB_PORT_STAT_OVERCURRENT;
  341. if (temp & PORT_RESET)
  342. status |= USB_PORT_STAT_RESET;
  343. if (temp & PORT_POWER)
  344. status |= USB_PORT_STAT_POWER;
  345. if (xhci->port_c_suspend[wIndex >> 5] & (1 << (wIndex & 31)))
  346. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  347. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  348. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  349. break;
  350. case SetPortFeature:
  351. wIndex &= 0xff;
  352. if (!wIndex || wIndex > ports)
  353. goto error;
  354. wIndex--;
  355. addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
  356. temp = xhci_readl(xhci, addr);
  357. temp = xhci_port_state_to_neutral(temp);
  358. switch (wValue) {
  359. case USB_PORT_FEAT_SUSPEND:
  360. temp = xhci_readl(xhci, addr);
  361. /* In spec software should not attempt to suspend
  362. * a port unless the port reports that it is in the
  363. * enabled (PED = ‘1’,PLS < ‘3’) state.
  364. */
  365. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  366. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  367. xhci_warn(xhci, "USB core suspending device "
  368. "not in U0/U1/U2.\n");
  369. goto error;
  370. }
  371. slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1);
  372. if (!slot_id) {
  373. xhci_warn(xhci, "slot_id is zero\n");
  374. goto error;
  375. }
  376. /* unlock to execute stop endpoint commands */
  377. spin_unlock_irqrestore(&xhci->lock, flags);
  378. xhci_stop_device(xhci, slot_id, 1);
  379. spin_lock_irqsave(&xhci->lock, flags);
  380. temp = xhci_port_state_to_neutral(temp);
  381. temp &= ~PORT_PLS_MASK;
  382. temp |= PORT_LINK_STROBE | XDEV_U3;
  383. xhci_writel(xhci, temp, addr);
  384. spin_unlock_irqrestore(&xhci->lock, flags);
  385. msleep(10); /* wait device to enter */
  386. spin_lock_irqsave(&xhci->lock, flags);
  387. temp = xhci_readl(xhci, addr);
  388. xhci->suspended_ports[wIndex >> 5] |=
  389. 1 << (wIndex & (31));
  390. break;
  391. case USB_PORT_FEAT_POWER:
  392. /*
  393. * Turn on ports, even if there isn't per-port switching.
  394. * HC will report connect events even before this is set.
  395. * However, khubd will ignore the roothub events until
  396. * the roothub is registered.
  397. */
  398. xhci_writel(xhci, temp | PORT_POWER, addr);
  399. temp = xhci_readl(xhci, addr);
  400. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  401. break;
  402. case USB_PORT_FEAT_RESET:
  403. temp = (temp | PORT_RESET);
  404. xhci_writel(xhci, temp, addr);
  405. temp = xhci_readl(xhci, addr);
  406. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  407. break;
  408. default:
  409. goto error;
  410. }
  411. temp = xhci_readl(xhci, addr); /* unblock any posted writes */
  412. break;
  413. case ClearPortFeature:
  414. if (!wIndex || wIndex > ports)
  415. goto error;
  416. wIndex--;
  417. addr = &xhci->op_regs->port_status_base +
  418. NUM_PORT_REGS*(wIndex & 0xff);
  419. temp = xhci_readl(xhci, addr);
  420. temp = xhci_port_state_to_neutral(temp);
  421. switch (wValue) {
  422. case USB_PORT_FEAT_SUSPEND:
  423. temp = xhci_readl(xhci, addr);
  424. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  425. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  426. if (temp & PORT_RESET)
  427. goto error;
  428. if (temp & XDEV_U3) {
  429. if ((temp & PORT_PE) == 0)
  430. goto error;
  431. if (DEV_SUPERSPEED(temp)) {
  432. temp = xhci_port_state_to_neutral(temp);
  433. temp &= ~PORT_PLS_MASK;
  434. temp |= PORT_LINK_STROBE | XDEV_U0;
  435. xhci_writel(xhci, temp, addr);
  436. xhci_readl(xhci, addr);
  437. } else {
  438. temp = xhci_port_state_to_neutral(temp);
  439. temp &= ~PORT_PLS_MASK;
  440. temp |= PORT_LINK_STROBE | XDEV_RESUME;
  441. xhci_writel(xhci, temp, addr);
  442. spin_unlock_irqrestore(&xhci->lock,
  443. flags);
  444. msleep(20);
  445. spin_lock_irqsave(&xhci->lock, flags);
  446. temp = xhci_readl(xhci, addr);
  447. temp = xhci_port_state_to_neutral(temp);
  448. temp &= ~PORT_PLS_MASK;
  449. temp |= PORT_LINK_STROBE | XDEV_U0;
  450. xhci_writel(xhci, temp, addr);
  451. }
  452. xhci->port_c_suspend[wIndex >> 5] |=
  453. 1 << (wIndex & 31);
  454. }
  455. slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1);
  456. if (!slot_id) {
  457. xhci_dbg(xhci, "slot_id is zero\n");
  458. goto error;
  459. }
  460. xhci_ring_device(xhci, slot_id);
  461. break;
  462. case USB_PORT_FEAT_C_SUSPEND:
  463. xhci->port_c_suspend[wIndex >> 5] &=
  464. ~(1 << (wIndex & 31));
  465. case USB_PORT_FEAT_C_RESET:
  466. case USB_PORT_FEAT_C_CONNECTION:
  467. case USB_PORT_FEAT_C_OVER_CURRENT:
  468. case USB_PORT_FEAT_C_ENABLE:
  469. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  470. addr, temp);
  471. break;
  472. case USB_PORT_FEAT_ENABLE:
  473. xhci_disable_port(xhci, wIndex, addr, temp);
  474. break;
  475. default:
  476. goto error;
  477. }
  478. break;
  479. default:
  480. error:
  481. /* "stall" on error */
  482. retval = -EPIPE;
  483. }
  484. spin_unlock_irqrestore(&xhci->lock, flags);
  485. return retval;
  486. }
  487. /*
  488. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  489. * Ports are 0-indexed from the HCD point of view,
  490. * and 1-indexed from the USB core pointer of view.
  491. *
  492. * Note that the status change bits will be cleared as soon as a port status
  493. * change event is generated, so we use the saved status from that event.
  494. */
  495. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  496. {
  497. unsigned long flags;
  498. u32 temp, status;
  499. u32 mask;
  500. int i, retval;
  501. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  502. int ports;
  503. u32 __iomem *addr;
  504. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  505. /* Initial status is no changes */
  506. retval = (ports + 8) / 8;
  507. memset(buf, 0, retval);
  508. status = 0;
  509. mask = PORT_CSC | PORT_PEC | PORT_OCC;
  510. spin_lock_irqsave(&xhci->lock, flags);
  511. /* For each port, did anything change? If so, set that bit in buf. */
  512. for (i = 0; i < ports; i++) {
  513. addr = &xhci->op_regs->port_status_base +
  514. NUM_PORT_REGS*i;
  515. temp = xhci_readl(xhci, addr);
  516. if ((temp & mask) != 0 ||
  517. (xhci->port_c_suspend[i >> 5] & 1 << (i & 31)) ||
  518. (xhci->resume_done[i] && time_after_eq(
  519. jiffies, xhci->resume_done[i]))) {
  520. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  521. status = 1;
  522. }
  523. }
  524. spin_unlock_irqrestore(&xhci->lock, flags);
  525. return status ? retval : 0;
  526. }
  527. #ifdef CONFIG_PM
  528. int xhci_bus_suspend(struct usb_hcd *hcd)
  529. {
  530. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  531. int port;
  532. unsigned long flags;
  533. xhci_dbg(xhci, "suspend root hub\n");
  534. spin_lock_irqsave(&xhci->lock, flags);
  535. if (hcd->self.root_hub->do_remote_wakeup) {
  536. port = HCS_MAX_PORTS(xhci->hcs_params1);
  537. while (port--) {
  538. if (xhci->resume_done[port] != 0) {
  539. spin_unlock_irqrestore(&xhci->lock, flags);
  540. xhci_dbg(xhci, "suspend failed because "
  541. "port %d is resuming\n",
  542. port + 1);
  543. return -EBUSY;
  544. }
  545. }
  546. }
  547. port = HCS_MAX_PORTS(xhci->hcs_params1);
  548. xhci->bus_suspended = 0;
  549. while (port--) {
  550. /* suspend the port if the port is not suspended */
  551. u32 __iomem *addr;
  552. u32 t1, t2;
  553. int slot_id;
  554. addr = &xhci->op_regs->port_status_base +
  555. NUM_PORT_REGS * (port & 0xff);
  556. t1 = xhci_readl(xhci, addr);
  557. t2 = xhci_port_state_to_neutral(t1);
  558. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  559. xhci_dbg(xhci, "port %d not suspended\n", port);
  560. slot_id = xhci_find_slot_id_by_port(xhci, port + 1);
  561. if (slot_id) {
  562. spin_unlock_irqrestore(&xhci->lock, flags);
  563. xhci_stop_device(xhci, slot_id, 1);
  564. spin_lock_irqsave(&xhci->lock, flags);
  565. }
  566. t2 &= ~PORT_PLS_MASK;
  567. t2 |= PORT_LINK_STROBE | XDEV_U3;
  568. set_bit(port, &xhci->bus_suspended);
  569. }
  570. if (hcd->self.root_hub->do_remote_wakeup) {
  571. if (t1 & PORT_CONNECT) {
  572. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  573. t2 &= ~PORT_WKCONN_E;
  574. } else {
  575. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  576. t2 &= ~PORT_WKDISC_E;
  577. }
  578. } else
  579. t2 &= ~PORT_WAKE_BITS;
  580. t1 = xhci_port_state_to_neutral(t1);
  581. if (t1 != t2)
  582. xhci_writel(xhci, t2, addr);
  583. if (DEV_HIGHSPEED(t1)) {
  584. /* enable remote wake up for USB 2.0 */
  585. u32 __iomem *addr;
  586. u32 tmp;
  587. addr = &xhci->op_regs->port_power_base +
  588. NUM_PORT_REGS * (port & 0xff);
  589. tmp = xhci_readl(xhci, addr);
  590. tmp |= PORT_RWE;
  591. xhci_writel(xhci, tmp, addr);
  592. }
  593. }
  594. hcd->state = HC_STATE_SUSPENDED;
  595. xhci->next_statechange = jiffies + msecs_to_jiffies(10);
  596. spin_unlock_irqrestore(&xhci->lock, flags);
  597. return 0;
  598. }
  599. int xhci_bus_resume(struct usb_hcd *hcd)
  600. {
  601. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  602. int port;
  603. u32 temp;
  604. unsigned long flags;
  605. xhci_dbg(xhci, "resume root hub\n");
  606. if (time_before(jiffies, xhci->next_statechange))
  607. msleep(5);
  608. spin_lock_irqsave(&xhci->lock, flags);
  609. if (!HCD_HW_ACCESSIBLE(hcd)) {
  610. spin_unlock_irqrestore(&xhci->lock, flags);
  611. return -ESHUTDOWN;
  612. }
  613. /* delay the irqs */
  614. temp = xhci_readl(xhci, &xhci->op_regs->command);
  615. temp &= ~CMD_EIE;
  616. xhci_writel(xhci, temp, &xhci->op_regs->command);
  617. port = HCS_MAX_PORTS(xhci->hcs_params1);
  618. while (port--) {
  619. /* Check whether need resume ports. If needed
  620. resume port and disable remote wakeup */
  621. u32 __iomem *addr;
  622. u32 temp;
  623. int slot_id;
  624. addr = &xhci->op_regs->port_status_base +
  625. NUM_PORT_REGS * (port & 0xff);
  626. temp = xhci_readl(xhci, addr);
  627. if (DEV_SUPERSPEED(temp))
  628. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  629. else
  630. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  631. if (test_bit(port, &xhci->bus_suspended) &&
  632. (temp & PORT_PLS_MASK)) {
  633. if (DEV_SUPERSPEED(temp)) {
  634. temp = xhci_port_state_to_neutral(temp);
  635. temp &= ~PORT_PLS_MASK;
  636. temp |= PORT_LINK_STROBE | XDEV_U0;
  637. xhci_writel(xhci, temp, addr);
  638. } else {
  639. temp = xhci_port_state_to_neutral(temp);
  640. temp &= ~PORT_PLS_MASK;
  641. temp |= PORT_LINK_STROBE | XDEV_RESUME;
  642. xhci_writel(xhci, temp, addr);
  643. spin_unlock_irqrestore(&xhci->lock, flags);
  644. msleep(20);
  645. spin_lock_irqsave(&xhci->lock, flags);
  646. temp = xhci_readl(xhci, addr);
  647. temp = xhci_port_state_to_neutral(temp);
  648. temp &= ~PORT_PLS_MASK;
  649. temp |= PORT_LINK_STROBE | XDEV_U0;
  650. xhci_writel(xhci, temp, addr);
  651. }
  652. slot_id = xhci_find_slot_id_by_port(xhci, port + 1);
  653. if (slot_id)
  654. xhci_ring_device(xhci, slot_id);
  655. } else
  656. xhci_writel(xhci, temp, addr);
  657. if (DEV_HIGHSPEED(temp)) {
  658. /* disable remote wake up for USB 2.0 */
  659. u32 __iomem *addr;
  660. u32 tmp;
  661. addr = &xhci->op_regs->port_power_base +
  662. NUM_PORT_REGS * (port & 0xff);
  663. tmp = xhci_readl(xhci, addr);
  664. tmp &= ~PORT_RWE;
  665. xhci_writel(xhci, tmp, addr);
  666. }
  667. }
  668. (void) xhci_readl(xhci, &xhci->op_regs->command);
  669. xhci->next_statechange = jiffies + msecs_to_jiffies(5);
  670. hcd->state = HC_STATE_RUNNING;
  671. /* re-enable irqs */
  672. temp = xhci_readl(xhci, &xhci->op_regs->command);
  673. temp |= CMD_EIE;
  674. xhci_writel(xhci, temp, &xhci->op_regs->command);
  675. temp = xhci_readl(xhci, &xhci->op_regs->command);
  676. spin_unlock_irqrestore(&xhci->lock, flags);
  677. return 0;
  678. }
  679. #endif /* CONFIG_PM */