main.c 47 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. static char *dev_info = "ath9k";
  22. MODULE_AUTHOR("Atheros Communications");
  23. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25. MODULE_LICENSE("Dual BSD/GPL");
  26. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  27. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  28. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  31. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32. { 0 }
  33. };
  34. static int ath_get_channel(struct ath_softc *sc,
  35. struct ieee80211_channel *chan)
  36. {
  37. int i;
  38. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  39. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  40. return i;
  41. }
  42. return -1;
  43. }
  44. static u32 ath_get_extchanmode(struct ath_softc *sc,
  45. struct ieee80211_channel *chan)
  46. {
  47. u32 chanmode = 0;
  48. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  49. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  50. switch (chan->band) {
  51. case IEEE80211_BAND_2GHZ:
  52. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  53. (tx_chan_width == ATH9K_HT_MACMODE_20))
  54. chanmode = CHANNEL_G_HT20;
  55. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  56. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  57. chanmode = CHANNEL_G_HT40PLUS;
  58. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  59. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  60. chanmode = CHANNEL_G_HT40MINUS;
  61. break;
  62. case IEEE80211_BAND_5GHZ:
  63. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  64. (tx_chan_width == ATH9K_HT_MACMODE_20))
  65. chanmode = CHANNEL_A_HT20;
  66. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  67. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  68. chanmode = CHANNEL_A_HT40PLUS;
  69. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  70. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  71. chanmode = CHANNEL_A_HT40MINUS;
  72. break;
  73. default:
  74. break;
  75. }
  76. return chanmode;
  77. }
  78. static int ath_setkey_tkip(struct ath_softc *sc,
  79. struct ieee80211_key_conf *key,
  80. struct ath9k_keyval *hk,
  81. const u8 *addr)
  82. {
  83. u8 *key_rxmic = NULL;
  84. u8 *key_txmic = NULL;
  85. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  86. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  87. if (addr == NULL) {
  88. /* Group key installation */
  89. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  90. return ath_keyset(sc, key->keyidx, hk, addr);
  91. }
  92. if (!sc->sc_splitmic) {
  93. /*
  94. * data key goes at first index,
  95. * the hal handles the MIC keys at index+64.
  96. */
  97. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  98. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  99. return ath_keyset(sc, key->keyidx, hk, addr);
  100. }
  101. /*
  102. * TX key goes at first index, RX key at +32.
  103. * The hal handles the MIC keys at index+64.
  104. */
  105. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  106. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  107. /* Txmic entry failed. No need to proceed further */
  108. DPRINTF(sc, ATH_DBG_KEYCACHE,
  109. "%s Setting TX MIC Key Failed\n", __func__);
  110. return 0;
  111. }
  112. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  113. /* XXX delete tx key on failure? */
  114. return ath_keyset(sc, key->keyidx+32, hk, addr);
  115. }
  116. static int ath_key_config(struct ath_softc *sc,
  117. const u8 *addr,
  118. struct ieee80211_key_conf *key)
  119. {
  120. struct ieee80211_vif *vif;
  121. struct ath9k_keyval hk;
  122. const u8 *mac = NULL;
  123. int ret = 0;
  124. enum nl80211_iftype opmode;
  125. memset(&hk, 0, sizeof(hk));
  126. switch (key->alg) {
  127. case ALG_WEP:
  128. hk.kv_type = ATH9K_CIPHER_WEP;
  129. break;
  130. case ALG_TKIP:
  131. hk.kv_type = ATH9K_CIPHER_TKIP;
  132. break;
  133. case ALG_CCMP:
  134. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  135. break;
  136. default:
  137. return -EINVAL;
  138. }
  139. hk.kv_len = key->keylen;
  140. memcpy(hk.kv_val, key->key, key->keylen);
  141. if (!sc->sc_vaps[0])
  142. return -EIO;
  143. vif = sc->sc_vaps[0]->av_if_data;
  144. opmode = vif->type;
  145. /*
  146. * Strategy:
  147. * For _M_STA mc tx, we will not setup a key at all since we never
  148. * tx mc.
  149. * _M_STA mc rx, we will use the keyID.
  150. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  151. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  152. * peer node. BUT we will plumb a cleartext key so that we can do
  153. * perSta default key table lookup in software.
  154. */
  155. if (is_broadcast_ether_addr(addr)) {
  156. switch (opmode) {
  157. case NL80211_IFTYPE_STATION:
  158. /* default key: could be group WPA key
  159. * or could be static WEP key */
  160. mac = NULL;
  161. break;
  162. case NL80211_IFTYPE_ADHOC:
  163. break;
  164. case NL80211_IFTYPE_AP:
  165. break;
  166. default:
  167. ASSERT(0);
  168. break;
  169. }
  170. } else {
  171. mac = addr;
  172. }
  173. if (key->alg == ALG_TKIP)
  174. ret = ath_setkey_tkip(sc, key, &hk, mac);
  175. else
  176. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  177. if (!ret)
  178. return -EIO;
  179. return 0;
  180. }
  181. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  182. {
  183. int freeslot;
  184. freeslot = (key->keyidx >= 4) ? 1 : 0;
  185. ath_key_reset(sc, key->keyidx, freeslot);
  186. }
  187. static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
  188. {
  189. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  190. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  191. ht_info->ht_supported = true;
  192. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  193. IEEE80211_HT_CAP_SM_PS |
  194. IEEE80211_HT_CAP_SGI_40 |
  195. IEEE80211_HT_CAP_DSSSCCK40;
  196. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  197. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  198. /* set up supported mcs set */
  199. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  200. ht_info->mcs.rx_mask[0] = 0xff;
  201. ht_info->mcs.rx_mask[1] = 0xff;
  202. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  203. }
  204. static int ath_rate2idx(struct ath_softc *sc, int rate)
  205. {
  206. int i = 0, cur_band, n_rates;
  207. struct ieee80211_hw *hw = sc->hw;
  208. cur_band = hw->conf.channel->band;
  209. n_rates = sc->sbands[cur_band].n_bitrates;
  210. for (i = 0; i < n_rates; i++) {
  211. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  212. break;
  213. }
  214. /*
  215. * NB:mac80211 validates rx rate index against the supported legacy rate
  216. * index only (should be done against ht rates also), return the highest
  217. * legacy rate index for rx rate which does not match any one of the
  218. * supported basic and extended rates to make mac80211 happy.
  219. * The following hack will be cleaned up once the issue with
  220. * the rx rate index validation in mac80211 is fixed.
  221. */
  222. if (i == n_rates)
  223. return n_rates - 1;
  224. return i;
  225. }
  226. static void ath9k_rx_prepare(struct ath_softc *sc,
  227. struct sk_buff *skb,
  228. struct ath_recv_status *status,
  229. struct ieee80211_rx_status *rx_status)
  230. {
  231. struct ieee80211_hw *hw = sc->hw;
  232. struct ieee80211_channel *curchan = hw->conf.channel;
  233. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  234. rx_status->mactime = status->tsf;
  235. rx_status->band = curchan->band;
  236. rx_status->freq = curchan->center_freq;
  237. rx_status->noise = sc->sc_ani.sc_noise_floor;
  238. rx_status->signal = rx_status->noise + status->rssi;
  239. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  240. rx_status->antenna = status->antenna;
  241. /* XXX Fix me, 64 cannot be the max rssi value, rigure it out */
  242. rx_status->qual = status->rssi * 100 / 64;
  243. if (status->flags & ATH_RX_MIC_ERROR)
  244. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  245. if (status->flags & ATH_RX_FCS_ERROR)
  246. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  247. rx_status->flag |= RX_FLAG_TSFT;
  248. }
  249. static u8 parse_mpdudensity(u8 mpdudensity)
  250. {
  251. /*
  252. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  253. * 0 for no restriction
  254. * 1 for 1/4 us
  255. * 2 for 1/2 us
  256. * 3 for 1 us
  257. * 4 for 2 us
  258. * 5 for 4 us
  259. * 6 for 8 us
  260. * 7 for 16 us
  261. */
  262. switch (mpdudensity) {
  263. case 0:
  264. return 0;
  265. case 1:
  266. case 2:
  267. case 3:
  268. /* Our lower layer calculations limit our precision to
  269. 1 microsecond */
  270. return 1;
  271. case 4:
  272. return 2;
  273. case 5:
  274. return 4;
  275. case 6:
  276. return 8;
  277. case 7:
  278. return 16;
  279. default:
  280. return 0;
  281. }
  282. }
  283. static void ath9k_ht_conf(struct ath_softc *sc,
  284. struct ieee80211_bss_conf *bss_conf)
  285. {
  286. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  287. if (bss_conf->assoc_ht) {
  288. ht_info->ext_chan_offset =
  289. bss_conf->ht_bss_conf->bss_cap &
  290. IEEE80211_HT_PARAM_CHA_SEC_OFFSET;
  291. if (!(bss_conf->ht_cap->cap &
  292. IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
  293. (bss_conf->ht_bss_conf->bss_cap &
  294. IEEE80211_HT_PARAM_CHAN_WIDTH_ANY))
  295. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  296. else
  297. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  298. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  299. ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  300. bss_conf->ht_cap->ampdu_factor);
  301. ht_info->mpdudensity =
  302. parse_mpdudensity(bss_conf->ht_cap->ampdu_density);
  303. }
  304. }
  305. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  306. struct ieee80211_bss_conf *bss_conf)
  307. {
  308. struct ieee80211_hw *hw = sc->hw;
  309. struct ieee80211_channel *curchan = hw->conf.channel;
  310. struct ath_vap *avp;
  311. int pos;
  312. if (bss_conf->assoc) {
  313. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  314. __func__,
  315. bss_conf->aid);
  316. avp = sc->sc_vaps[0];
  317. if (avp == NULL) {
  318. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  319. __func__);
  320. return;
  321. }
  322. /* New association, store aid */
  323. if (avp->av_opmode == ATH9K_M_STA) {
  324. sc->sc_curaid = bss_conf->aid;
  325. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  326. sc->sc_curaid);
  327. }
  328. /* Configure the beacon */
  329. ath_beacon_config(sc, 0);
  330. sc->sc_flags |= SC_OP_BEACONS;
  331. /* Reset rssi stats */
  332. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  333. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  334. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  335. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  336. /* Update chainmask */
  337. ath_update_chainmask(sc, bss_conf->assoc_ht);
  338. DPRINTF(sc, ATH_DBG_CONFIG,
  339. "%s: bssid %pM aid 0x%x\n",
  340. __func__,
  341. sc->sc_curbssid, sc->sc_curaid);
  342. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  343. __func__,
  344. curchan->center_freq);
  345. pos = ath_get_channel(sc, curchan);
  346. if (pos == -1) {
  347. DPRINTF(sc, ATH_DBG_FATAL,
  348. "%s: Invalid channel\n", __func__);
  349. return;
  350. }
  351. if (hw->conf.ht_cap.ht_supported)
  352. sc->sc_ah->ah_channels[pos].chanmode =
  353. ath_get_extchanmode(sc, curchan);
  354. else
  355. sc->sc_ah->ah_channels[pos].chanmode =
  356. (curchan->band == IEEE80211_BAND_2GHZ) ?
  357. CHANNEL_G : CHANNEL_A;
  358. /* set h/w channel */
  359. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  360. DPRINTF(sc, ATH_DBG_FATAL,
  361. "%s: Unable to set channel\n",
  362. __func__);
  363. ath_rate_newstate(sc, avp);
  364. /* Update ratectrl about the new state */
  365. ath_rc_node_update(hw, avp->rc_node);
  366. /* Start ANI */
  367. mod_timer(&sc->sc_ani.timer,
  368. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  369. } else {
  370. DPRINTF(sc, ATH_DBG_CONFIG,
  371. "%s: Bss Info DISSOC\n", __func__);
  372. sc->sc_curaid = 0;
  373. }
  374. }
  375. void ath_get_beaconconfig(struct ath_softc *sc,
  376. int if_id,
  377. struct ath_beacon_config *conf)
  378. {
  379. struct ieee80211_hw *hw = sc->hw;
  380. /* fill in beacon config data */
  381. conf->beacon_interval = hw->conf.beacon_int;
  382. conf->listen_interval = 100;
  383. conf->dtim_count = 1;
  384. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  385. }
  386. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  387. struct ath_xmit_status *tx_status, struct ath_node *an)
  388. {
  389. struct ieee80211_hw *hw = sc->hw;
  390. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  391. DPRINTF(sc, ATH_DBG_XMIT,
  392. "%s: TX complete: skb: %p\n", __func__, skb);
  393. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  394. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  395. /* free driver's private data area of tx_info */
  396. if (tx_info->driver_data[0] != NULL)
  397. kfree(tx_info->driver_data[0]);
  398. tx_info->driver_data[0] = NULL;
  399. }
  400. if (tx_status->flags & ATH_TX_BAR) {
  401. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  402. tx_status->flags &= ~ATH_TX_BAR;
  403. }
  404. if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
  405. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  406. /* Frame was not ACKed, but an ACK was expected */
  407. tx_info->status.excessive_retries = 1;
  408. }
  409. } else {
  410. /* Frame was ACKed */
  411. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  412. }
  413. tx_info->status.retry_count = tx_status->retries;
  414. ieee80211_tx_status(hw, skb);
  415. if (an)
  416. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  417. }
  418. int _ath_rx_indicate(struct ath_softc *sc,
  419. struct sk_buff *skb,
  420. struct ath_recv_status *status,
  421. u16 keyix)
  422. {
  423. struct ieee80211_hw *hw = sc->hw;
  424. struct ath_node *an = NULL;
  425. struct ieee80211_rx_status rx_status;
  426. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  427. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  428. int padsize;
  429. enum ATH_RX_TYPE st;
  430. /* see if any padding is done by the hw and remove it */
  431. if (hdrlen & 3) {
  432. padsize = hdrlen % 4;
  433. memmove(skb->data + padsize, skb->data, hdrlen);
  434. skb_pull(skb, padsize);
  435. }
  436. /* Prepare rx status */
  437. ath9k_rx_prepare(sc, skb, status, &rx_status);
  438. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  439. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  440. rx_status.flag |= RX_FLAG_DECRYPTED;
  441. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  442. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  443. && skb->len >= hdrlen + 4) {
  444. keyix = skb->data[hdrlen + 3] >> 6;
  445. if (test_bit(keyix, sc->sc_keymap))
  446. rx_status.flag |= RX_FLAG_DECRYPTED;
  447. }
  448. spin_lock_bh(&sc->node_lock);
  449. an = ath_node_find(sc, hdr->addr2);
  450. spin_unlock_bh(&sc->node_lock);
  451. if (an) {
  452. ath_rx_input(sc, an,
  453. hw->conf.ht_cap.ht_supported,
  454. skb, status, &st);
  455. }
  456. if (!an || (st != ATH_RX_CONSUMED))
  457. __ieee80211_rx(hw, skb, &rx_status);
  458. return 0;
  459. }
  460. int ath_rx_subframe(struct ath_node *an,
  461. struct sk_buff *skb,
  462. struct ath_recv_status *status)
  463. {
  464. struct ath_softc *sc = an->an_sc;
  465. struct ieee80211_hw *hw = sc->hw;
  466. struct ieee80211_rx_status rx_status;
  467. /* Prepare rx status */
  468. ath9k_rx_prepare(sc, skb, status, &rx_status);
  469. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  470. rx_status.flag |= RX_FLAG_DECRYPTED;
  471. __ieee80211_rx(hw, skb, &rx_status);
  472. return 0;
  473. }
  474. /********************************/
  475. /* LED functions */
  476. /********************************/
  477. static void ath_led_brightness(struct led_classdev *led_cdev,
  478. enum led_brightness brightness)
  479. {
  480. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  481. struct ath_softc *sc = led->sc;
  482. switch (brightness) {
  483. case LED_OFF:
  484. if (led->led_type == ATH_LED_ASSOC ||
  485. led->led_type == ATH_LED_RADIO)
  486. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  487. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  488. (led->led_type == ATH_LED_RADIO) ? 1 :
  489. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  490. break;
  491. case LED_FULL:
  492. if (led->led_type == ATH_LED_ASSOC)
  493. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  494. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  495. break;
  496. default:
  497. break;
  498. }
  499. }
  500. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  501. char *trigger)
  502. {
  503. int ret;
  504. led->sc = sc;
  505. led->led_cdev.name = led->name;
  506. led->led_cdev.default_trigger = trigger;
  507. led->led_cdev.brightness_set = ath_led_brightness;
  508. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  509. if (ret)
  510. DPRINTF(sc, ATH_DBG_FATAL,
  511. "Failed to register led:%s", led->name);
  512. else
  513. led->registered = 1;
  514. return ret;
  515. }
  516. static void ath_unregister_led(struct ath_led *led)
  517. {
  518. if (led->registered) {
  519. led_classdev_unregister(&led->led_cdev);
  520. led->registered = 0;
  521. }
  522. }
  523. static void ath_deinit_leds(struct ath_softc *sc)
  524. {
  525. ath_unregister_led(&sc->assoc_led);
  526. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  527. ath_unregister_led(&sc->tx_led);
  528. ath_unregister_led(&sc->rx_led);
  529. ath_unregister_led(&sc->radio_led);
  530. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  531. }
  532. static void ath_init_leds(struct ath_softc *sc)
  533. {
  534. char *trigger;
  535. int ret;
  536. /* Configure gpio 1 for output */
  537. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  538. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  539. /* LED off, active low */
  540. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  541. trigger = ieee80211_get_radio_led_name(sc->hw);
  542. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  543. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  544. ret = ath_register_led(sc, &sc->radio_led, trigger);
  545. sc->radio_led.led_type = ATH_LED_RADIO;
  546. if (ret)
  547. goto fail;
  548. trigger = ieee80211_get_assoc_led_name(sc->hw);
  549. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  550. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  551. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  552. sc->assoc_led.led_type = ATH_LED_ASSOC;
  553. if (ret)
  554. goto fail;
  555. trigger = ieee80211_get_tx_led_name(sc->hw);
  556. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  557. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  558. ret = ath_register_led(sc, &sc->tx_led, trigger);
  559. sc->tx_led.led_type = ATH_LED_TX;
  560. if (ret)
  561. goto fail;
  562. trigger = ieee80211_get_rx_led_name(sc->hw);
  563. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  564. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  565. ret = ath_register_led(sc, &sc->rx_led, trigger);
  566. sc->rx_led.led_type = ATH_LED_RX;
  567. if (ret)
  568. goto fail;
  569. return;
  570. fail:
  571. ath_deinit_leds(sc);
  572. }
  573. #ifdef CONFIG_RFKILL
  574. /*******************/
  575. /* Rfkill */
  576. /*******************/
  577. static void ath_radio_enable(struct ath_softc *sc)
  578. {
  579. struct ath_hal *ah = sc->sc_ah;
  580. int status;
  581. spin_lock_bh(&sc->sc_resetlock);
  582. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  583. sc->sc_ht_info.tx_chan_width,
  584. sc->sc_tx_chainmask,
  585. sc->sc_rx_chainmask,
  586. sc->sc_ht_extprotspacing,
  587. false, &status)) {
  588. DPRINTF(sc, ATH_DBG_FATAL,
  589. "%s: unable to reset channel %u (%uMhz) "
  590. "flags 0x%x hal status %u\n", __func__,
  591. ath9k_hw_mhz2ieee(ah,
  592. ah->ah_curchan->channel,
  593. ah->ah_curchan->channelFlags),
  594. ah->ah_curchan->channel,
  595. ah->ah_curchan->channelFlags, status);
  596. }
  597. spin_unlock_bh(&sc->sc_resetlock);
  598. ath_update_txpow(sc);
  599. if (ath_startrecv(sc) != 0) {
  600. DPRINTF(sc, ATH_DBG_FATAL,
  601. "%s: unable to restart recv logic\n", __func__);
  602. return;
  603. }
  604. if (sc->sc_flags & SC_OP_BEACONS)
  605. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  606. /* Re-Enable interrupts */
  607. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  608. /* Enable LED */
  609. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  610. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  611. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  612. ieee80211_wake_queues(sc->hw);
  613. }
  614. static void ath_radio_disable(struct ath_softc *sc)
  615. {
  616. struct ath_hal *ah = sc->sc_ah;
  617. int status;
  618. ieee80211_stop_queues(sc->hw);
  619. /* Disable LED */
  620. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  621. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  622. /* Disable interrupts */
  623. ath9k_hw_set_interrupts(ah, 0);
  624. ath_draintxq(sc, false); /* clear pending tx frames */
  625. ath_stoprecv(sc); /* turn off frame recv */
  626. ath_flushrecv(sc); /* flush recv queue */
  627. spin_lock_bh(&sc->sc_resetlock);
  628. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  629. sc->sc_ht_info.tx_chan_width,
  630. sc->sc_tx_chainmask,
  631. sc->sc_rx_chainmask,
  632. sc->sc_ht_extprotspacing,
  633. false, &status)) {
  634. DPRINTF(sc, ATH_DBG_FATAL,
  635. "%s: unable to reset channel %u (%uMhz) "
  636. "flags 0x%x hal status %u\n", __func__,
  637. ath9k_hw_mhz2ieee(ah,
  638. ah->ah_curchan->channel,
  639. ah->ah_curchan->channelFlags),
  640. ah->ah_curchan->channel,
  641. ah->ah_curchan->channelFlags, status);
  642. }
  643. spin_unlock_bh(&sc->sc_resetlock);
  644. ath9k_hw_phy_disable(ah);
  645. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  646. }
  647. static bool ath_is_rfkill_set(struct ath_softc *sc)
  648. {
  649. struct ath_hal *ah = sc->sc_ah;
  650. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  651. ah->ah_rfkill_polarity;
  652. }
  653. /* h/w rfkill poll function */
  654. static void ath_rfkill_poll(struct work_struct *work)
  655. {
  656. struct ath_softc *sc = container_of(work, struct ath_softc,
  657. rf_kill.rfkill_poll.work);
  658. bool radio_on;
  659. if (sc->sc_flags & SC_OP_INVALID)
  660. return;
  661. radio_on = !ath_is_rfkill_set(sc);
  662. /*
  663. * enable/disable radio only when there is a
  664. * state change in RF switch
  665. */
  666. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  667. enum rfkill_state state;
  668. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  669. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  670. : RFKILL_STATE_HARD_BLOCKED;
  671. } else if (radio_on) {
  672. ath_radio_enable(sc);
  673. state = RFKILL_STATE_UNBLOCKED;
  674. } else {
  675. ath_radio_disable(sc);
  676. state = RFKILL_STATE_HARD_BLOCKED;
  677. }
  678. if (state == RFKILL_STATE_HARD_BLOCKED)
  679. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  680. else
  681. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  682. rfkill_force_state(sc->rf_kill.rfkill, state);
  683. }
  684. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  685. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  686. }
  687. /* s/w rfkill handler */
  688. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  689. {
  690. struct ath_softc *sc = data;
  691. switch (state) {
  692. case RFKILL_STATE_SOFT_BLOCKED:
  693. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  694. SC_OP_RFKILL_SW_BLOCKED)))
  695. ath_radio_disable(sc);
  696. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  697. return 0;
  698. case RFKILL_STATE_UNBLOCKED:
  699. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  700. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  701. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  702. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  703. "radio as it is disabled by h/w \n");
  704. return -EPERM;
  705. }
  706. ath_radio_enable(sc);
  707. }
  708. return 0;
  709. default:
  710. return -EINVAL;
  711. }
  712. }
  713. /* Init s/w rfkill */
  714. static int ath_init_sw_rfkill(struct ath_softc *sc)
  715. {
  716. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  717. RFKILL_TYPE_WLAN);
  718. if (!sc->rf_kill.rfkill) {
  719. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  720. return -ENOMEM;
  721. }
  722. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  723. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  724. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  725. sc->rf_kill.rfkill->data = sc;
  726. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  727. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  728. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  729. return 0;
  730. }
  731. /* Deinitialize rfkill */
  732. static void ath_deinit_rfkill(struct ath_softc *sc)
  733. {
  734. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  735. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  736. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  737. rfkill_unregister(sc->rf_kill.rfkill);
  738. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  739. sc->rf_kill.rfkill = NULL;
  740. }
  741. }
  742. #endif /* CONFIG_RFKILL */
  743. static int ath_detach(struct ath_softc *sc)
  744. {
  745. struct ieee80211_hw *hw = sc->hw;
  746. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  747. /* Deinit LED control */
  748. ath_deinit_leds(sc);
  749. #ifdef CONFIG_RFKILL
  750. /* deinit rfkill */
  751. ath_deinit_rfkill(sc);
  752. #endif
  753. /* Unregister hw */
  754. ieee80211_unregister_hw(hw);
  755. /* unregister Rate control */
  756. ath_rate_control_unregister();
  757. /* tx/rx cleanup */
  758. ath_rx_cleanup(sc);
  759. ath_tx_cleanup(sc);
  760. /* Deinit */
  761. ath_deinit(sc);
  762. return 0;
  763. }
  764. static int ath_attach(u16 devid,
  765. struct ath_softc *sc)
  766. {
  767. struct ieee80211_hw *hw = sc->hw;
  768. int error = 0;
  769. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  770. error = ath_init(devid, sc);
  771. if (error != 0)
  772. return error;
  773. /* Init nodes */
  774. INIT_LIST_HEAD(&sc->node_list);
  775. spin_lock_init(&sc->node_lock);
  776. /* get mac address from hardware and set in mac80211 */
  777. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  778. /* setup channels and rates */
  779. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  780. sc->channels[IEEE80211_BAND_2GHZ];
  781. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  782. sc->rates[IEEE80211_BAND_2GHZ];
  783. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  784. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  785. /* Setup HT capabilities for 2.4Ghz*/
  786. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  787. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  788. &sc->sbands[IEEE80211_BAND_2GHZ];
  789. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  790. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  791. sc->channels[IEEE80211_BAND_5GHZ];
  792. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  793. sc->rates[IEEE80211_BAND_5GHZ];
  794. sc->sbands[IEEE80211_BAND_5GHZ].band =
  795. IEEE80211_BAND_5GHZ;
  796. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  797. /* Setup HT capabilities for 5Ghz*/
  798. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  799. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  800. &sc->sbands[IEEE80211_BAND_5GHZ];
  801. }
  802. /* FIXME: Have to figure out proper hw init values later */
  803. hw->queues = 4;
  804. hw->ampdu_queues = 1;
  805. /* Register rate control */
  806. hw->rate_control_algorithm = "ath9k_rate_control";
  807. error = ath_rate_control_register();
  808. if (error != 0) {
  809. DPRINTF(sc, ATH_DBG_FATAL,
  810. "%s: Unable to register rate control "
  811. "algorithm:%d\n", __func__, error);
  812. ath_rate_control_unregister();
  813. goto bad;
  814. }
  815. error = ieee80211_register_hw(hw);
  816. if (error != 0) {
  817. ath_rate_control_unregister();
  818. goto bad;
  819. }
  820. /* Initialize LED control */
  821. ath_init_leds(sc);
  822. #ifdef CONFIG_RFKILL
  823. /* Initialze h/w Rfkill */
  824. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  825. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  826. /* Initialize s/w rfkill */
  827. if (ath_init_sw_rfkill(sc))
  828. goto detach;
  829. #endif
  830. /* initialize tx/rx engine */
  831. error = ath_tx_init(sc, ATH_TXBUF);
  832. if (error != 0)
  833. goto detach;
  834. error = ath_rx_init(sc, ATH_RXBUF);
  835. if (error != 0)
  836. goto detach;
  837. return 0;
  838. detach:
  839. ath_detach(sc);
  840. bad:
  841. return error;
  842. }
  843. static int ath9k_start(struct ieee80211_hw *hw)
  844. {
  845. struct ath_softc *sc = hw->priv;
  846. struct ieee80211_channel *curchan = hw->conf.channel;
  847. int error = 0, pos;
  848. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  849. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  850. /* setup initial channel */
  851. pos = ath_get_channel(sc, curchan);
  852. if (pos == -1) {
  853. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  854. return -EINVAL;
  855. }
  856. sc->sc_ah->ah_channels[pos].chanmode =
  857. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  858. /* open ath_dev */
  859. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  860. if (error) {
  861. DPRINTF(sc, ATH_DBG_FATAL,
  862. "%s: Unable to complete ath_open\n", __func__);
  863. return error;
  864. }
  865. #ifdef CONFIG_RFKILL
  866. /* Start rfkill polling */
  867. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  868. queue_delayed_work(sc->hw->workqueue,
  869. &sc->rf_kill.rfkill_poll, 0);
  870. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  871. if (rfkill_register(sc->rf_kill.rfkill)) {
  872. DPRINTF(sc, ATH_DBG_FATAL,
  873. "Unable to register rfkill\n");
  874. rfkill_free(sc->rf_kill.rfkill);
  875. /* Deinitialize the device */
  876. if (sc->pdev->irq)
  877. free_irq(sc->pdev->irq, sc);
  878. ath_detach(sc);
  879. pci_iounmap(sc->pdev, sc->mem);
  880. pci_release_region(sc->pdev, 0);
  881. pci_disable_device(sc->pdev);
  882. ieee80211_free_hw(hw);
  883. return -EIO;
  884. } else {
  885. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  886. }
  887. }
  888. #endif
  889. ieee80211_wake_queues(hw);
  890. return 0;
  891. }
  892. static int ath9k_tx(struct ieee80211_hw *hw,
  893. struct sk_buff *skb)
  894. {
  895. struct ath_softc *sc = hw->priv;
  896. int hdrlen, padsize;
  897. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  898. /*
  899. * As a temporary workaround, assign seq# here; this will likely need
  900. * to be cleaned up to work better with Beacon transmission and virtual
  901. * BSSes.
  902. */
  903. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  904. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  905. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  906. sc->seq_no += 0x10;
  907. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  908. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  909. }
  910. /* Add the padding after the header if this is not already done */
  911. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  912. if (hdrlen & 3) {
  913. padsize = hdrlen % 4;
  914. if (skb_headroom(skb) < padsize)
  915. return -1;
  916. skb_push(skb, padsize);
  917. memmove(skb->data, skb->data + padsize, hdrlen);
  918. }
  919. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  920. __func__,
  921. skb);
  922. if (ath_tx_start(sc, skb) != 0) {
  923. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  924. dev_kfree_skb_any(skb);
  925. /* FIXME: Check for proper return value from ATH_DEV */
  926. return 0;
  927. }
  928. return 0;
  929. }
  930. static void ath9k_stop(struct ieee80211_hw *hw)
  931. {
  932. struct ath_softc *sc = hw->priv;
  933. int error;
  934. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  935. error = ath_suspend(sc);
  936. if (error)
  937. DPRINTF(sc, ATH_DBG_CONFIG,
  938. "%s: Device is no longer present\n", __func__);
  939. ieee80211_stop_queues(hw);
  940. #ifdef CONFIG_RFKILL
  941. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  942. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  943. #endif
  944. }
  945. static int ath9k_add_interface(struct ieee80211_hw *hw,
  946. struct ieee80211_if_init_conf *conf)
  947. {
  948. struct ath_softc *sc = hw->priv;
  949. int error, ic_opmode = 0;
  950. /* Support only vap for now */
  951. if (sc->sc_nvaps)
  952. return -ENOBUFS;
  953. switch (conf->type) {
  954. case NL80211_IFTYPE_STATION:
  955. ic_opmode = ATH9K_M_STA;
  956. break;
  957. case NL80211_IFTYPE_ADHOC:
  958. ic_opmode = ATH9K_M_IBSS;
  959. break;
  960. case NL80211_IFTYPE_AP:
  961. ic_opmode = ATH9K_M_HOSTAP;
  962. break;
  963. default:
  964. DPRINTF(sc, ATH_DBG_FATAL,
  965. "%s: Interface type %d not yet supported\n",
  966. __func__, conf->type);
  967. return -EOPNOTSUPP;
  968. }
  969. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  970. __func__,
  971. ic_opmode);
  972. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  973. if (error) {
  974. DPRINTF(sc, ATH_DBG_FATAL,
  975. "%s: Unable to attach vap, error: %d\n",
  976. __func__, error);
  977. return error;
  978. }
  979. if (conf->type == NL80211_IFTYPE_AP) {
  980. /* TODO: is this a suitable place to start ANI for AP mode? */
  981. /* Start ANI */
  982. mod_timer(&sc->sc_ani.timer,
  983. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  984. }
  985. return 0;
  986. }
  987. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  988. struct ieee80211_if_init_conf *conf)
  989. {
  990. struct ath_softc *sc = hw->priv;
  991. struct ath_vap *avp;
  992. int error;
  993. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  994. avp = sc->sc_vaps[0];
  995. if (avp == NULL) {
  996. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  997. __func__);
  998. return;
  999. }
  1000. #ifdef CONFIG_SLOW_ANT_DIV
  1001. ath_slow_ant_div_stop(&sc->sc_antdiv);
  1002. #endif
  1003. /* Stop ANI */
  1004. del_timer_sync(&sc->sc_ani.timer);
  1005. /* Update ratectrl */
  1006. ath_rate_newstate(sc, avp);
  1007. /* Reclaim beacon resources */
  1008. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  1009. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  1010. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1011. ath_beacon_return(sc, avp);
  1012. }
  1013. /* Set interrupt mask */
  1014. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1015. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  1016. sc->sc_flags &= ~SC_OP_BEACONS;
  1017. error = ath_vap_detach(sc, 0);
  1018. if (error)
  1019. DPRINTF(sc, ATH_DBG_FATAL,
  1020. "%s: Unable to detach vap, error: %d\n",
  1021. __func__, error);
  1022. }
  1023. static int ath9k_config(struct ieee80211_hw *hw,
  1024. struct ieee80211_conf *conf)
  1025. {
  1026. struct ath_softc *sc = hw->priv;
  1027. struct ieee80211_channel *curchan = hw->conf.channel;
  1028. int pos;
  1029. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  1030. __func__,
  1031. curchan->center_freq);
  1032. pos = ath_get_channel(sc, curchan);
  1033. if (pos == -1) {
  1034. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  1035. return -EINVAL;
  1036. }
  1037. sc->sc_ah->ah_channels[pos].chanmode =
  1038. (curchan->band == IEEE80211_BAND_2GHZ) ?
  1039. CHANNEL_G : CHANNEL_A;
  1040. if (sc->sc_curaid && hw->conf.ht_cap.ht_supported)
  1041. sc->sc_ah->ah_channels[pos].chanmode =
  1042. ath_get_extchanmode(sc, curchan);
  1043. sc->sc_config.txpowlimit = 2 * conf->power_level;
  1044. /* set h/w channel */
  1045. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  1046. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  1047. __func__);
  1048. return 0;
  1049. }
  1050. static int ath9k_config_interface(struct ieee80211_hw *hw,
  1051. struct ieee80211_vif *vif,
  1052. struct ieee80211_if_conf *conf)
  1053. {
  1054. struct ath_softc *sc = hw->priv;
  1055. struct ath_hal *ah = sc->sc_ah;
  1056. struct ath_vap *avp;
  1057. u32 rfilt = 0;
  1058. int error, i;
  1059. avp = sc->sc_vaps[0];
  1060. if (avp == NULL) {
  1061. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  1062. __func__);
  1063. return -EINVAL;
  1064. }
  1065. /* TODO: Need to decide which hw opmode to use for multi-interface
  1066. * cases */
  1067. if (vif->type == NL80211_IFTYPE_AP &&
  1068. ah->ah_opmode != ATH9K_M_HOSTAP) {
  1069. ah->ah_opmode = ATH9K_M_HOSTAP;
  1070. ath9k_hw_setopmode(ah);
  1071. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  1072. /* Request full reset to get hw opmode changed properly */
  1073. sc->sc_flags |= SC_OP_FULL_RESET;
  1074. }
  1075. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  1076. !is_zero_ether_addr(conf->bssid)) {
  1077. switch (vif->type) {
  1078. case NL80211_IFTYPE_STATION:
  1079. case NL80211_IFTYPE_ADHOC:
  1080. /* Update ratectrl about the new state */
  1081. ath_rate_newstate(sc, avp);
  1082. /* Set BSSID */
  1083. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  1084. sc->sc_curaid = 0;
  1085. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  1086. sc->sc_curaid);
  1087. /* Set aggregation protection mode parameters */
  1088. sc->sc_config.ath_aggr_prot = 0;
  1089. /*
  1090. * Reset our TSF so that its value is lower than the
  1091. * beacon that we are trying to catch.
  1092. * Only then hw will update its TSF register with the
  1093. * new beacon. Reset the TSF before setting the BSSID
  1094. * to avoid allowing in any frames that would update
  1095. * our TSF only to have us clear it
  1096. * immediately thereafter.
  1097. */
  1098. ath9k_hw_reset_tsf(sc->sc_ah);
  1099. /* Disable BMISS interrupt when we're not associated */
  1100. ath9k_hw_set_interrupts(sc->sc_ah,
  1101. sc->sc_imask &
  1102. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  1103. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1104. DPRINTF(sc, ATH_DBG_CONFIG,
  1105. "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
  1106. __func__, rfilt,
  1107. sc->sc_curbssid, sc->sc_curaid);
  1108. /* need to reconfigure the beacon */
  1109. sc->sc_flags &= ~SC_OP_BEACONS ;
  1110. break;
  1111. default:
  1112. break;
  1113. }
  1114. }
  1115. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  1116. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  1117. (vif->type == NL80211_IFTYPE_AP))) {
  1118. /*
  1119. * Allocate and setup the beacon frame.
  1120. *
  1121. * Stop any previous beacon DMA. This may be
  1122. * necessary, for example, when an ibss merge
  1123. * causes reconfiguration; we may be called
  1124. * with beacon transmission active.
  1125. */
  1126. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1127. error = ath_beacon_alloc(sc, 0);
  1128. if (error != 0)
  1129. return error;
  1130. ath_beacon_sync(sc, 0);
  1131. }
  1132. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  1133. if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
  1134. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  1135. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  1136. ath9k_hw_keysetmac(sc->sc_ah,
  1137. (u16)i,
  1138. sc->sc_curbssid);
  1139. }
  1140. /* Only legacy IBSS for now */
  1141. if (vif->type == NL80211_IFTYPE_ADHOC)
  1142. ath_update_chainmask(sc, 0);
  1143. return 0;
  1144. }
  1145. #define SUPPORTED_FILTERS \
  1146. (FIF_PROMISC_IN_BSS | \
  1147. FIF_ALLMULTI | \
  1148. FIF_CONTROL | \
  1149. FIF_OTHER_BSS | \
  1150. FIF_BCN_PRBRESP_PROMISC | \
  1151. FIF_FCSFAIL)
  1152. /* FIXME: sc->sc_full_reset ? */
  1153. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1154. unsigned int changed_flags,
  1155. unsigned int *total_flags,
  1156. int mc_count,
  1157. struct dev_mc_list *mclist)
  1158. {
  1159. struct ath_softc *sc = hw->priv;
  1160. u32 rfilt;
  1161. changed_flags &= SUPPORTED_FILTERS;
  1162. *total_flags &= SUPPORTED_FILTERS;
  1163. sc->rx_filter = *total_flags;
  1164. rfilt = ath_calcrxfilter(sc);
  1165. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1166. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1167. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1168. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  1169. }
  1170. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  1171. __func__, sc->rx_filter);
  1172. }
  1173. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1174. struct ieee80211_vif *vif,
  1175. enum sta_notify_cmd cmd,
  1176. struct ieee80211_sta *sta)
  1177. {
  1178. struct ath_softc *sc = hw->priv;
  1179. struct ath_node *an;
  1180. unsigned long flags;
  1181. spin_lock_irqsave(&sc->node_lock, flags);
  1182. an = ath_node_find(sc, sta->addr);
  1183. spin_unlock_irqrestore(&sc->node_lock, flags);
  1184. switch (cmd) {
  1185. case STA_NOTIFY_ADD:
  1186. spin_lock_irqsave(&sc->node_lock, flags);
  1187. if (!an) {
  1188. ath_node_attach(sc, sta->addr, 0);
  1189. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %pM\n",
  1190. __func__, sta->addr);
  1191. } else {
  1192. ath_node_get(sc, sta->addr);
  1193. }
  1194. spin_unlock_irqrestore(&sc->node_lock, flags);
  1195. break;
  1196. case STA_NOTIFY_REMOVE:
  1197. if (!an)
  1198. DPRINTF(sc, ATH_DBG_FATAL,
  1199. "%s: Removal of a non-existent node\n",
  1200. __func__);
  1201. else {
  1202. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  1203. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %pM\n",
  1204. __func__,
  1205. sta->addr);
  1206. }
  1207. break;
  1208. default:
  1209. break;
  1210. }
  1211. }
  1212. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1213. u16 queue,
  1214. const struct ieee80211_tx_queue_params *params)
  1215. {
  1216. struct ath_softc *sc = hw->priv;
  1217. struct ath9k_tx_queue_info qi;
  1218. int ret = 0, qnum;
  1219. if (queue >= WME_NUM_AC)
  1220. return 0;
  1221. qi.tqi_aifs = params->aifs;
  1222. qi.tqi_cwmin = params->cw_min;
  1223. qi.tqi_cwmax = params->cw_max;
  1224. qi.tqi_burstTime = params->txop;
  1225. qnum = ath_get_hal_qnum(queue, sc);
  1226. DPRINTF(sc, ATH_DBG_CONFIG,
  1227. "%s: Configure tx [queue/halq] [%d/%d], "
  1228. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1229. __func__,
  1230. queue,
  1231. qnum,
  1232. params->aifs,
  1233. params->cw_min,
  1234. params->cw_max,
  1235. params->txop);
  1236. ret = ath_txq_update(sc, qnum, &qi);
  1237. if (ret)
  1238. DPRINTF(sc, ATH_DBG_FATAL,
  1239. "%s: TXQ Update failed\n", __func__);
  1240. return ret;
  1241. }
  1242. static int ath9k_set_key(struct ieee80211_hw *hw,
  1243. enum set_key_cmd cmd,
  1244. const u8 *local_addr,
  1245. const u8 *addr,
  1246. struct ieee80211_key_conf *key)
  1247. {
  1248. struct ath_softc *sc = hw->priv;
  1249. int ret = 0;
  1250. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1251. switch (cmd) {
  1252. case SET_KEY:
  1253. ret = ath_key_config(sc, addr, key);
  1254. if (!ret) {
  1255. set_bit(key->keyidx, sc->sc_keymap);
  1256. key->hw_key_idx = key->keyidx;
  1257. /* push IV and Michael MIC generation to stack */
  1258. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1259. if (key->alg == ALG_TKIP)
  1260. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1261. }
  1262. break;
  1263. case DISABLE_KEY:
  1264. ath_key_delete(sc, key);
  1265. clear_bit(key->keyidx, sc->sc_keymap);
  1266. break;
  1267. default:
  1268. ret = -EINVAL;
  1269. }
  1270. return ret;
  1271. }
  1272. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1273. struct ieee80211_vif *vif,
  1274. struct ieee80211_bss_conf *bss_conf,
  1275. u32 changed)
  1276. {
  1277. struct ath_softc *sc = hw->priv;
  1278. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1279. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1280. __func__,
  1281. bss_conf->use_short_preamble);
  1282. if (bss_conf->use_short_preamble)
  1283. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1284. else
  1285. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1286. }
  1287. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1288. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1289. __func__,
  1290. bss_conf->use_cts_prot);
  1291. if (bss_conf->use_cts_prot &&
  1292. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1293. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1294. else
  1295. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1296. }
  1297. if (changed & BSS_CHANGED_HT) {
  1298. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
  1299. __func__,
  1300. bss_conf->assoc_ht);
  1301. ath9k_ht_conf(sc, bss_conf);
  1302. }
  1303. if (changed & BSS_CHANGED_ASSOC) {
  1304. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1305. __func__,
  1306. bss_conf->assoc);
  1307. ath9k_bss_assoc_info(sc, bss_conf);
  1308. }
  1309. }
  1310. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1311. {
  1312. u64 tsf;
  1313. struct ath_softc *sc = hw->priv;
  1314. struct ath_hal *ah = sc->sc_ah;
  1315. tsf = ath9k_hw_gettsf64(ah);
  1316. return tsf;
  1317. }
  1318. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1319. {
  1320. struct ath_softc *sc = hw->priv;
  1321. struct ath_hal *ah = sc->sc_ah;
  1322. ath9k_hw_reset_tsf(ah);
  1323. }
  1324. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1325. enum ieee80211_ampdu_mlme_action action,
  1326. struct ieee80211_sta *sta,
  1327. u16 tid, u16 *ssn)
  1328. {
  1329. struct ath_softc *sc = hw->priv;
  1330. int ret = 0;
  1331. switch (action) {
  1332. case IEEE80211_AMPDU_RX_START:
  1333. ret = ath_rx_aggr_start(sc, sta->addr, tid, ssn);
  1334. if (ret < 0)
  1335. DPRINTF(sc, ATH_DBG_FATAL,
  1336. "%s: Unable to start RX aggregation\n",
  1337. __func__);
  1338. break;
  1339. case IEEE80211_AMPDU_RX_STOP:
  1340. ret = ath_rx_aggr_stop(sc, sta->addr, tid);
  1341. if (ret < 0)
  1342. DPRINTF(sc, ATH_DBG_FATAL,
  1343. "%s: Unable to stop RX aggregation\n",
  1344. __func__);
  1345. break;
  1346. case IEEE80211_AMPDU_TX_START:
  1347. ret = ath_tx_aggr_start(sc, sta->addr, tid, ssn);
  1348. if (ret < 0)
  1349. DPRINTF(sc, ATH_DBG_FATAL,
  1350. "%s: Unable to start TX aggregation\n",
  1351. __func__);
  1352. else
  1353. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1354. break;
  1355. case IEEE80211_AMPDU_TX_STOP:
  1356. ret = ath_tx_aggr_stop(sc, sta->addr, tid);
  1357. if (ret < 0)
  1358. DPRINTF(sc, ATH_DBG_FATAL,
  1359. "%s: Unable to stop TX aggregation\n",
  1360. __func__);
  1361. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1362. break;
  1363. default:
  1364. DPRINTF(sc, ATH_DBG_FATAL,
  1365. "%s: Unknown AMPDU action\n", __func__);
  1366. }
  1367. return ret;
  1368. }
  1369. static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
  1370. {
  1371. return -EOPNOTSUPP;
  1372. }
  1373. static struct ieee80211_ops ath9k_ops = {
  1374. .tx = ath9k_tx,
  1375. .start = ath9k_start,
  1376. .stop = ath9k_stop,
  1377. .add_interface = ath9k_add_interface,
  1378. .remove_interface = ath9k_remove_interface,
  1379. .config = ath9k_config,
  1380. .config_interface = ath9k_config_interface,
  1381. .configure_filter = ath9k_configure_filter,
  1382. .get_stats = NULL,
  1383. .sta_notify = ath9k_sta_notify,
  1384. .conf_tx = ath9k_conf_tx,
  1385. .get_tx_stats = NULL,
  1386. .bss_info_changed = ath9k_bss_info_changed,
  1387. .set_tim = NULL,
  1388. .set_key = ath9k_set_key,
  1389. .hw_scan = NULL,
  1390. .get_tkip_seq = NULL,
  1391. .set_rts_threshold = NULL,
  1392. .set_frag_threshold = NULL,
  1393. .set_retry_limit = NULL,
  1394. .get_tsf = ath9k_get_tsf,
  1395. .reset_tsf = ath9k_reset_tsf,
  1396. .tx_last_beacon = NULL,
  1397. .ampdu_action = ath9k_ampdu_action,
  1398. .set_frag_threshold = ath9k_no_fragmentation,
  1399. };
  1400. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1401. {
  1402. void __iomem *mem;
  1403. struct ath_softc *sc;
  1404. struct ieee80211_hw *hw;
  1405. const char *athname;
  1406. u8 csz;
  1407. u32 val;
  1408. int ret = 0;
  1409. if (pci_enable_device(pdev))
  1410. return -EIO;
  1411. /* XXX 32-bit addressing only */
  1412. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1413. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1414. ret = -ENODEV;
  1415. goto bad;
  1416. }
  1417. /*
  1418. * Cache line size is used to size and align various
  1419. * structures used to communicate with the hardware.
  1420. */
  1421. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1422. if (csz == 0) {
  1423. /*
  1424. * Linux 2.4.18 (at least) writes the cache line size
  1425. * register as a 16-bit wide register which is wrong.
  1426. * We must have this setup properly for rx buffer
  1427. * DMA to work so force a reasonable value here if it
  1428. * comes up zero.
  1429. */
  1430. csz = L1_CACHE_BYTES / sizeof(u32);
  1431. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1432. }
  1433. /*
  1434. * The default setting of latency timer yields poor results,
  1435. * set it to the value used by other systems. It may be worth
  1436. * tweaking this setting more.
  1437. */
  1438. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1439. pci_set_master(pdev);
  1440. /*
  1441. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1442. * PCI Tx retries from interfering with C3 CPU state.
  1443. */
  1444. pci_read_config_dword(pdev, 0x40, &val);
  1445. if ((val & 0x0000ff00) != 0)
  1446. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1447. ret = pci_request_region(pdev, 0, "ath9k");
  1448. if (ret) {
  1449. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1450. ret = -ENODEV;
  1451. goto bad;
  1452. }
  1453. mem = pci_iomap(pdev, 0, 0);
  1454. if (!mem) {
  1455. printk(KERN_ERR "PCI memory map error\n") ;
  1456. ret = -EIO;
  1457. goto bad1;
  1458. }
  1459. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1460. if (hw == NULL) {
  1461. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1462. goto bad2;
  1463. }
  1464. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  1465. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1466. IEEE80211_HW_SIGNAL_DBM |
  1467. IEEE80211_HW_NOISE_DBM;
  1468. hw->wiphy->interface_modes =
  1469. BIT(NL80211_IFTYPE_AP) |
  1470. BIT(NL80211_IFTYPE_STATION) |
  1471. BIT(NL80211_IFTYPE_ADHOC);
  1472. SET_IEEE80211_DEV(hw, &pdev->dev);
  1473. pci_set_drvdata(pdev, hw);
  1474. sc = hw->priv;
  1475. sc->hw = hw;
  1476. sc->pdev = pdev;
  1477. sc->mem = mem;
  1478. if (ath_attach(id->device, sc) != 0) {
  1479. ret = -ENODEV;
  1480. goto bad3;
  1481. }
  1482. /* setup interrupt service routine */
  1483. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1484. printk(KERN_ERR "%s: request_irq failed\n",
  1485. wiphy_name(hw->wiphy));
  1486. ret = -EIO;
  1487. goto bad4;
  1488. }
  1489. athname = ath9k_hw_probe(id->vendor, id->device);
  1490. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1491. wiphy_name(hw->wiphy),
  1492. athname ? athname : "Atheros ???",
  1493. (unsigned long)mem, pdev->irq);
  1494. return 0;
  1495. bad4:
  1496. ath_detach(sc);
  1497. bad3:
  1498. ieee80211_free_hw(hw);
  1499. bad2:
  1500. pci_iounmap(pdev, mem);
  1501. bad1:
  1502. pci_release_region(pdev, 0);
  1503. bad:
  1504. pci_disable_device(pdev);
  1505. return ret;
  1506. }
  1507. static void ath_pci_remove(struct pci_dev *pdev)
  1508. {
  1509. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1510. struct ath_softc *sc = hw->priv;
  1511. enum ath9k_int status;
  1512. if (pdev->irq) {
  1513. ath9k_hw_set_interrupts(sc->sc_ah, 0);
  1514. /* clear the ISR */
  1515. ath9k_hw_getisr(sc->sc_ah, &status);
  1516. sc->sc_flags |= SC_OP_INVALID;
  1517. free_irq(pdev->irq, sc);
  1518. }
  1519. ath_detach(sc);
  1520. pci_iounmap(pdev, sc->mem);
  1521. pci_release_region(pdev, 0);
  1522. pci_disable_device(pdev);
  1523. ieee80211_free_hw(hw);
  1524. }
  1525. #ifdef CONFIG_PM
  1526. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1527. {
  1528. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1529. struct ath_softc *sc = hw->priv;
  1530. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1531. #ifdef CONFIG_RFKILL
  1532. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1533. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1534. #endif
  1535. pci_save_state(pdev);
  1536. pci_disable_device(pdev);
  1537. pci_set_power_state(pdev, 3);
  1538. return 0;
  1539. }
  1540. static int ath_pci_resume(struct pci_dev *pdev)
  1541. {
  1542. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1543. struct ath_softc *sc = hw->priv;
  1544. u32 val;
  1545. int err;
  1546. err = pci_enable_device(pdev);
  1547. if (err)
  1548. return err;
  1549. pci_restore_state(pdev);
  1550. /*
  1551. * Suspend/Resume resets the PCI configuration space, so we have to
  1552. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1553. * PCI Tx retries from interfering with C3 CPU state
  1554. */
  1555. pci_read_config_dword(pdev, 0x40, &val);
  1556. if ((val & 0x0000ff00) != 0)
  1557. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1558. /* Enable LED */
  1559. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1560. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1561. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1562. #ifdef CONFIG_RFKILL
  1563. /*
  1564. * check the h/w rfkill state on resume
  1565. * and start the rfkill poll timer
  1566. */
  1567. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1568. queue_delayed_work(sc->hw->workqueue,
  1569. &sc->rf_kill.rfkill_poll, 0);
  1570. #endif
  1571. return 0;
  1572. }
  1573. #endif /* CONFIG_PM */
  1574. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1575. static struct pci_driver ath_pci_driver = {
  1576. .name = "ath9k",
  1577. .id_table = ath_pci_id_table,
  1578. .probe = ath_pci_probe,
  1579. .remove = ath_pci_remove,
  1580. #ifdef CONFIG_PM
  1581. .suspend = ath_pci_suspend,
  1582. .resume = ath_pci_resume,
  1583. #endif /* CONFIG_PM */
  1584. };
  1585. static int __init init_ath_pci(void)
  1586. {
  1587. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1588. if (pci_register_driver(&ath_pci_driver) < 0) {
  1589. printk(KERN_ERR
  1590. "ath_pci: No devices found, driver not installed.\n");
  1591. pci_unregister_driver(&ath_pci_driver);
  1592. return -ENODEV;
  1593. }
  1594. return 0;
  1595. }
  1596. module_init(init_ath_pci);
  1597. static void __exit exit_ath_pci(void)
  1598. {
  1599. pci_unregister_driver(&ath_pci_driver);
  1600. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1601. }
  1602. module_exit(exit_ath_pci);