netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct nx_host_rds_ring *rds_ring;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  152. rds_ring = &recv_ctx->rds_rings[ring];
  153. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  154. rx_buf = &(rds_ring->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rds_ring->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct nx_host_rds_ring *rds_ring;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  205. rds_ring = &recv_ctx->rds_rings[ring];
  206. if (rds_ring->rx_buf_arr) {
  207. vfree(rds_ring->rx_buf_arr);
  208. rds_ring->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct nx_host_rds_ring *rds_ring;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  235. rds_ring = &recv_ctx->rds_rings[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rds_ring->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rds_ring->flags = RCV_DESC_NORMAL;
  241. if (adapter->ahw.cut_through) {
  242. rds_ring->dma_size =
  243. NX_CT_DEFAULT_RX_BUF_LEN;
  244. rds_ring->skb_size =
  245. NX_CT_DEFAULT_RX_BUF_LEN;
  246. } else {
  247. rds_ring->dma_size = RX_DMA_MAP_LEN;
  248. rds_ring->skb_size =
  249. MAX_RX_BUFFER_LENGTH;
  250. }
  251. break;
  252. case RCV_DESC_JUMBO:
  253. rds_ring->max_rx_desc_count =
  254. adapter->max_jumbo_rx_desc_count;
  255. rds_ring->flags = RCV_DESC_JUMBO;
  256. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  257. rds_ring->dma_size =
  258. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  259. else
  260. rds_ring->dma_size =
  261. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  262. rds_ring->skb_size =
  263. rds_ring->dma_size + NET_IP_ALIGN;
  264. break;
  265. case RCV_RING_LRO:
  266. rds_ring->max_rx_desc_count =
  267. adapter->max_lro_rx_desc_count;
  268. rds_ring->flags = RCV_DESC_LRO;
  269. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  270. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  271. break;
  272. }
  273. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  274. vmalloc(RCV_BUFFSIZE);
  275. if (rds_ring->rx_buf_arr == NULL) {
  276. printk(KERN_ERR "%s: Failed to allocate "
  277. "rx buffer ring %d\n",
  278. netdev->name, ring);
  279. /* free whatever was already allocated */
  280. goto err_out;
  281. }
  282. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  283. INIT_LIST_HEAD(&rds_ring->free_list);
  284. rds_ring->begin_alloc = 0;
  285. /*
  286. * Now go through all of them, set reference handles
  287. * and put them in the queues.
  288. */
  289. num_rx_bufs = rds_ring->max_rx_desc_count;
  290. rx_buf = rds_ring->rx_buf_arr;
  291. for (i = 0; i < num_rx_bufs; i++) {
  292. list_add_tail(&rx_buf->list,
  293. &rds_ring->free_list);
  294. rx_buf->ref_handle = i;
  295. rx_buf->state = NETXEN_BUFFER_FREE;
  296. rx_buf++;
  297. }
  298. }
  299. }
  300. return 0;
  301. err_out:
  302. netxen_free_sw_resources(adapter);
  303. return -ENOMEM;
  304. }
  305. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  306. {
  307. switch (adapter->ahw.board_type) {
  308. case NETXEN_NIC_GBE:
  309. adapter->enable_phy_interrupts =
  310. netxen_niu_gbe_enable_phy_interrupts;
  311. adapter->disable_phy_interrupts =
  312. netxen_niu_gbe_disable_phy_interrupts;
  313. adapter->macaddr_set = netxen_niu_macaddr_set;
  314. adapter->set_mtu = netxen_nic_set_mtu_gb;
  315. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  316. adapter->phy_read = netxen_niu_gbe_phy_read;
  317. adapter->phy_write = netxen_niu_gbe_phy_write;
  318. adapter->init_port = netxen_niu_gbe_init_port;
  319. adapter->stop_port = netxen_niu_disable_gbe_port;
  320. break;
  321. case NETXEN_NIC_XGBE:
  322. adapter->enable_phy_interrupts =
  323. netxen_niu_xgbe_enable_phy_interrupts;
  324. adapter->disable_phy_interrupts =
  325. netxen_niu_xgbe_disable_phy_interrupts;
  326. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  327. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  328. adapter->init_port = netxen_niu_xg_init_port;
  329. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  330. adapter->stop_port = netxen_niu_disable_xg_port;
  331. break;
  332. default:
  333. break;
  334. }
  335. }
  336. /*
  337. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  338. * address to external PCI CRB address.
  339. */
  340. static u32 netxen_decode_crb_addr(u32 addr)
  341. {
  342. int i;
  343. u32 base_addr, offset, pci_base;
  344. crb_addr_transform_setup();
  345. pci_base = NETXEN_ADDR_ERROR;
  346. base_addr = addr & 0xfff00000;
  347. offset = addr & 0x000fffff;
  348. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  349. if (crb_addr_xform[i] == base_addr) {
  350. pci_base = i << 20;
  351. break;
  352. }
  353. }
  354. if (pci_base == NETXEN_ADDR_ERROR)
  355. return pci_base;
  356. else
  357. return (pci_base + offset);
  358. }
  359. static long rom_max_timeout = 100;
  360. static long rom_lock_timeout = 10000;
  361. #if 0
  362. static long rom_write_timeout = 700;
  363. #endif
  364. static int rom_lock(struct netxen_adapter *adapter)
  365. {
  366. int iter;
  367. u32 done = 0;
  368. int timeout = 0;
  369. while (!done) {
  370. /* acquire semaphore2 from PCI HW block */
  371. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  372. &done);
  373. if (done == 1)
  374. break;
  375. if (timeout >= rom_lock_timeout)
  376. return -EIO;
  377. timeout++;
  378. /*
  379. * Yield CPU
  380. */
  381. if (!in_atomic())
  382. schedule();
  383. else {
  384. for (iter = 0; iter < 20; iter++)
  385. cpu_relax(); /*This a nop instr on i386 */
  386. }
  387. }
  388. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  389. return 0;
  390. }
  391. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  392. {
  393. long timeout = 0;
  394. long done = 0;
  395. while (done == 0) {
  396. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  397. done &= 2;
  398. timeout++;
  399. if (timeout >= rom_max_timeout) {
  400. printk("Timeout reached waiting for rom done");
  401. return -EIO;
  402. }
  403. }
  404. return 0;
  405. }
  406. #if 0
  407. static int netxen_rom_wren(struct netxen_adapter *adapter)
  408. {
  409. /* Set write enable latch in ROM status register */
  410. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  411. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  412. M25P_INSTR_WREN);
  413. if (netxen_wait_rom_done(adapter)) {
  414. return -1;
  415. }
  416. return 0;
  417. }
  418. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  419. unsigned int addr)
  420. {
  421. unsigned int data = 0xdeaddead;
  422. data = netxen_nic_reg_read(adapter, addr);
  423. return data;
  424. }
  425. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  426. {
  427. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  428. M25P_INSTR_RDSR);
  429. if (netxen_wait_rom_done(adapter)) {
  430. return -1;
  431. }
  432. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  433. }
  434. #endif
  435. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  436. {
  437. u32 val;
  438. /* release semaphore2 */
  439. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  440. }
  441. #if 0
  442. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  443. {
  444. long timeout = 0;
  445. long wip = 1;
  446. int val;
  447. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  448. while (wip != 0) {
  449. val = netxen_do_rom_rdsr(adapter);
  450. wip = val & 1;
  451. timeout++;
  452. if (timeout > rom_max_timeout) {
  453. return -1;
  454. }
  455. }
  456. return 0;
  457. }
  458. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  459. int data)
  460. {
  461. if (netxen_rom_wren(adapter)) {
  462. return -1;
  463. }
  464. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  465. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  466. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  467. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  468. M25P_INSTR_PP);
  469. if (netxen_wait_rom_done(adapter)) {
  470. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  471. return -1;
  472. }
  473. return netxen_rom_wip_poll(adapter);
  474. }
  475. #endif
  476. static int do_rom_fast_read(struct netxen_adapter *adapter,
  477. int addr, int *valp)
  478. {
  479. cond_resched();
  480. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  481. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  482. udelay(100); /* prevent bursting on CRB */
  483. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  484. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  485. if (netxen_wait_rom_done(adapter)) {
  486. printk("Error waiting for rom done\n");
  487. return -EIO;
  488. }
  489. /* reset abyte_cnt and dummy_byte_cnt */
  490. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  491. udelay(100); /* prevent bursting on CRB */
  492. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  493. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  494. return 0;
  495. }
  496. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  497. u8 *bytes, size_t size)
  498. {
  499. int addridx;
  500. int ret = 0;
  501. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  502. int v;
  503. ret = do_rom_fast_read(adapter, addridx, &v);
  504. if (ret != 0)
  505. break;
  506. *(__le32 *)bytes = cpu_to_le32(v);
  507. bytes += 4;
  508. }
  509. return ret;
  510. }
  511. int
  512. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  513. u8 *bytes, size_t size)
  514. {
  515. int ret;
  516. ret = rom_lock(adapter);
  517. if (ret < 0)
  518. return ret;
  519. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  520. netxen_rom_unlock(adapter);
  521. return ret;
  522. }
  523. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  524. {
  525. int ret;
  526. if (rom_lock(adapter) != 0)
  527. return -EIO;
  528. ret = do_rom_fast_read(adapter, addr, valp);
  529. netxen_rom_unlock(adapter);
  530. return ret;
  531. }
  532. #if 0
  533. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  534. {
  535. int ret = 0;
  536. if (rom_lock(adapter) != 0) {
  537. return -1;
  538. }
  539. ret = do_rom_fast_write(adapter, addr, data);
  540. netxen_rom_unlock(adapter);
  541. return ret;
  542. }
  543. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  544. int addr, u8 *bytes, size_t size)
  545. {
  546. int addridx = addr;
  547. int ret = 0;
  548. while (addridx < (addr + size)) {
  549. int last_attempt = 0;
  550. int timeout = 0;
  551. int data;
  552. data = le32_to_cpu((*(__le32*)bytes));
  553. ret = do_rom_fast_write(adapter, addridx, data);
  554. if (ret < 0)
  555. return ret;
  556. while(1) {
  557. int data1;
  558. ret = do_rom_fast_read(adapter, addridx, &data1);
  559. if (ret < 0)
  560. return ret;
  561. if (data1 == data)
  562. break;
  563. if (timeout++ >= rom_write_timeout) {
  564. if (last_attempt++ < 4) {
  565. ret = do_rom_fast_write(adapter,
  566. addridx, data);
  567. if (ret < 0)
  568. return ret;
  569. }
  570. else {
  571. printk(KERN_INFO "Data write did not "
  572. "succeed at address 0x%x\n", addridx);
  573. break;
  574. }
  575. }
  576. }
  577. bytes += 4;
  578. addridx += 4;
  579. }
  580. return ret;
  581. }
  582. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  583. u8 *bytes, size_t size)
  584. {
  585. int ret = 0;
  586. ret = rom_lock(adapter);
  587. if (ret < 0)
  588. return ret;
  589. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  590. netxen_rom_unlock(adapter);
  591. return ret;
  592. }
  593. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  594. {
  595. int ret;
  596. ret = netxen_rom_wren(adapter);
  597. if (ret < 0)
  598. return ret;
  599. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  600. netxen_crb_writelit_adapter(adapter,
  601. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  602. ret = netxen_wait_rom_done(adapter);
  603. if (ret < 0)
  604. return ret;
  605. return netxen_rom_wip_poll(adapter);
  606. }
  607. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  608. {
  609. int ret;
  610. ret = rom_lock(adapter);
  611. if (ret < 0)
  612. return ret;
  613. ret = netxen_do_rom_rdsr(adapter);
  614. netxen_rom_unlock(adapter);
  615. return ret;
  616. }
  617. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  618. {
  619. int ret = FLASH_SUCCESS;
  620. int val;
  621. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  622. if (!buffer)
  623. return -ENOMEM;
  624. /* unlock sector 63 */
  625. val = netxen_rom_rdsr(adapter);
  626. val = val & 0xe3;
  627. ret = netxen_rom_wrsr(adapter, val);
  628. if (ret != FLASH_SUCCESS)
  629. goto out_kfree;
  630. ret = netxen_rom_wip_poll(adapter);
  631. if (ret != FLASH_SUCCESS)
  632. goto out_kfree;
  633. /* copy sector 0 to sector 63 */
  634. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  635. buffer, NETXEN_FLASH_SECTOR_SIZE);
  636. if (ret != FLASH_SUCCESS)
  637. goto out_kfree;
  638. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  639. buffer, NETXEN_FLASH_SECTOR_SIZE);
  640. if (ret != FLASH_SUCCESS)
  641. goto out_kfree;
  642. /* lock sector 63 */
  643. val = netxen_rom_rdsr(adapter);
  644. if (!(val & 0x8)) {
  645. val |= (0x1 << 2);
  646. /* lock sector 63 */
  647. if (netxen_rom_wrsr(adapter, val) == 0) {
  648. ret = netxen_rom_wip_poll(adapter);
  649. if (ret != FLASH_SUCCESS)
  650. goto out_kfree;
  651. /* lock SR writes */
  652. ret = netxen_rom_wip_poll(adapter);
  653. if (ret != FLASH_SUCCESS)
  654. goto out_kfree;
  655. }
  656. }
  657. out_kfree:
  658. kfree(buffer);
  659. return ret;
  660. }
  661. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  662. {
  663. netxen_rom_wren(adapter);
  664. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  665. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  666. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  667. M25P_INSTR_SE);
  668. if (netxen_wait_rom_done(adapter)) {
  669. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  670. return -1;
  671. }
  672. return netxen_rom_wip_poll(adapter);
  673. }
  674. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  675. {
  676. int i;
  677. int val;
  678. int count = 0, erased_errors = 0;
  679. int range;
  680. range = (addr == NETXEN_USER_START) ?
  681. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  682. for (i = addr; i < range; i += 4) {
  683. netxen_rom_fast_read(adapter, i, &val);
  684. if (val != 0xffffffff)
  685. erased_errors++;
  686. count++;
  687. }
  688. if (erased_errors)
  689. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  690. "for sector address: %x\n", erased_errors, count, addr);
  691. }
  692. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  693. {
  694. int ret = 0;
  695. if (rom_lock(adapter) != 0) {
  696. return -1;
  697. }
  698. ret = netxen_do_rom_se(adapter, addr);
  699. netxen_rom_unlock(adapter);
  700. msleep(30);
  701. check_erased_flash(adapter, addr);
  702. return ret;
  703. }
  704. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  705. int start, int end)
  706. {
  707. int ret = FLASH_SUCCESS;
  708. int i;
  709. for (i = start; i < end; i++) {
  710. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  711. if (ret)
  712. break;
  713. ret = netxen_rom_wip_poll(adapter);
  714. if (ret < 0)
  715. return ret;
  716. }
  717. return ret;
  718. }
  719. int
  720. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  721. {
  722. int ret = FLASH_SUCCESS;
  723. int start, end;
  724. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  725. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  726. ret = netxen_flash_erase_sections(adapter, start, end);
  727. return ret;
  728. }
  729. int
  730. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  731. {
  732. int ret = FLASH_SUCCESS;
  733. int start, end;
  734. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  735. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  736. ret = netxen_flash_erase_sections(adapter, start, end);
  737. return ret;
  738. }
  739. void netxen_halt_pegs(struct netxen_adapter *adapter)
  740. {
  741. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  742. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  743. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  744. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  745. }
  746. int netxen_flash_unlock(struct netxen_adapter *adapter)
  747. {
  748. int ret = 0;
  749. ret = netxen_rom_wrsr(adapter, 0);
  750. if (ret < 0)
  751. return ret;
  752. ret = netxen_rom_wren(adapter);
  753. if (ret < 0)
  754. return ret;
  755. return ret;
  756. }
  757. #endif /* 0 */
  758. #define NETXEN_BOARDTYPE 0x4008
  759. #define NETXEN_BOARDNUM 0x400c
  760. #define NETXEN_CHIPNUM 0x4010
  761. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  762. {
  763. int addr, val;
  764. int i, init_delay = 0;
  765. struct crb_addr_pair *buf;
  766. unsigned offset, n;
  767. u32 off;
  768. /* resetall */
  769. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  770. 0xffffffff);
  771. if (verbose) {
  772. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  773. printk("P2 ROM board type: 0x%08x\n", val);
  774. else
  775. printk("Could not read board type\n");
  776. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  777. printk("P2 ROM board num: 0x%08x\n", val);
  778. else
  779. printk("Could not read board number\n");
  780. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  781. printk("P2 ROM chip num: 0x%08x\n", val);
  782. else
  783. printk("Could not read chip number\n");
  784. }
  785. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  786. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  787. (n != 0xcafecafeUL) ||
  788. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  789. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  790. "n: %08x\n", netxen_nic_driver_name, n);
  791. return -EIO;
  792. }
  793. offset = n & 0xffffU;
  794. n = (n >> 16) & 0xffffU;
  795. } else {
  796. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  797. !(n & 0x80000000)) {
  798. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  799. "n: %08x\n", netxen_nic_driver_name, n);
  800. return -EIO;
  801. }
  802. offset = 1;
  803. n &= ~0x80000000;
  804. }
  805. if (n < 1024) {
  806. if (verbose)
  807. printk(KERN_DEBUG "%s: %d CRB init values found"
  808. " in ROM.\n", netxen_nic_driver_name, n);
  809. } else {
  810. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  811. " initialized.\n", __func__, n);
  812. return -EIO;
  813. }
  814. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  815. if (buf == NULL) {
  816. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  817. netxen_nic_driver_name);
  818. return -ENOMEM;
  819. }
  820. for (i = 0; i < n; i++) {
  821. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  822. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0)
  823. return -EIO;
  824. buf[i].addr = addr;
  825. buf[i].data = val;
  826. if (verbose)
  827. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  828. netxen_nic_driver_name,
  829. (u32)netxen_decode_crb_addr(addr), val);
  830. }
  831. for (i = 0; i < n; i++) {
  832. off = netxen_decode_crb_addr(buf[i].addr);
  833. if (off == NETXEN_ADDR_ERROR) {
  834. printk(KERN_ERR"CRB init value out of range %x\n",
  835. buf[i].addr);
  836. continue;
  837. }
  838. off += NETXEN_PCI_CRBSPACE;
  839. /* skipping cold reboot MAGIC */
  840. if (off == NETXEN_CAM_RAM(0x1fc))
  841. continue;
  842. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  843. /* do not reset PCI */
  844. if (off == (ROMUSB_GLB + 0xbc))
  845. continue;
  846. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  847. buf[i].data = 0x1020;
  848. /* skip the function enable register */
  849. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  850. continue;
  851. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  852. continue;
  853. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  854. continue;
  855. }
  856. if (off == NETXEN_ADDR_ERROR) {
  857. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  858. netxen_nic_driver_name, buf[i].addr);
  859. continue;
  860. }
  861. /* After writing this register, HW needs time for CRB */
  862. /* to quiet down (else crb_window returns 0xffffffff) */
  863. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  864. init_delay = 1;
  865. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  866. /* hold xdma in reset also */
  867. buf[i].data = NETXEN_NIC_XDMA_RESET;
  868. }
  869. }
  870. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  871. if (init_delay == 1) {
  872. msleep(1000);
  873. init_delay = 0;
  874. }
  875. msleep(1);
  876. }
  877. kfree(buf);
  878. /* disable_peg_cache_all */
  879. /* unreset_net_cache */
  880. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  881. adapter->hw_read_wx(adapter,
  882. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  883. netxen_crb_writelit_adapter(adapter,
  884. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  885. }
  886. /* p2dn replyCount */
  887. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  888. /* disable_peg_cache 0 */
  889. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  890. /* disable_peg_cache 1 */
  891. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  892. /* peg_clr_all */
  893. /* peg_clr 0 */
  894. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  895. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  896. /* peg_clr 1 */
  897. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  898. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  899. /* peg_clr 2 */
  900. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  901. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  902. /* peg_clr 3 */
  903. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  904. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  905. return 0;
  906. }
  907. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  908. {
  909. uint64_t addr;
  910. uint32_t hi;
  911. uint32_t lo;
  912. adapter->dummy_dma.addr =
  913. pci_alloc_consistent(adapter->pdev,
  914. NETXEN_HOST_DUMMY_DMA_SIZE,
  915. &adapter->dummy_dma.phys_addr);
  916. if (adapter->dummy_dma.addr == NULL) {
  917. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  918. __func__);
  919. return -ENOMEM;
  920. }
  921. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  922. hi = (addr >> 32) & 0xffffffff;
  923. lo = addr & 0xffffffff;
  924. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  925. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  926. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  927. uint32_t temp = 0;
  928. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  929. }
  930. return 0;
  931. }
  932. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  933. {
  934. int i;
  935. if (adapter->dummy_dma.addr) {
  936. i = 100;
  937. do {
  938. if (dma_watchdog_shutdown_request(adapter) == 1)
  939. break;
  940. msleep(50);
  941. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  942. break;
  943. } while (--i);
  944. if (i) {
  945. pci_free_consistent(adapter->pdev,
  946. NETXEN_HOST_DUMMY_DMA_SIZE,
  947. adapter->dummy_dma.addr,
  948. adapter->dummy_dma.phys_addr);
  949. adapter->dummy_dma.addr = NULL;
  950. } else {
  951. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  952. adapter->netdev->name);
  953. }
  954. }
  955. }
  956. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  957. {
  958. u32 val = 0;
  959. int retries = 60;
  960. if (!pegtune_val) {
  961. do {
  962. val = adapter->pci_read_normalize(adapter,
  963. CRB_CMDPEG_STATE);
  964. if (val == PHAN_INITIALIZE_COMPLETE ||
  965. val == PHAN_INITIALIZE_ACK)
  966. return 0;
  967. msleep(500);
  968. } while (--retries);
  969. if (!retries) {
  970. pegtune_val = adapter->pci_read_normalize(adapter,
  971. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  972. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  973. "pegtune_val=%x\n", pegtune_val);
  974. return -1;
  975. }
  976. }
  977. return 0;
  978. }
  979. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  980. {
  981. u32 val = 0;
  982. int retries = 2000;
  983. do {
  984. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  985. if (val == PHAN_PEG_RCV_INITIALIZED)
  986. return 0;
  987. msleep(10);
  988. } while (--retries);
  989. if (!retries) {
  990. printk(KERN_ERR "Receive Peg initialization not "
  991. "complete, state: 0x%x.\n", val);
  992. return -EIO;
  993. }
  994. return 0;
  995. }
  996. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  997. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  998. {
  999. struct netxen_rx_buffer *buffer;
  1000. struct sk_buff *skb;
  1001. buffer = &rds_ring->rx_buf_arr[index];
  1002. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1003. PCI_DMA_FROMDEVICE);
  1004. skb = buffer->skb;
  1005. if (!skb)
  1006. goto no_skb;
  1007. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1008. adapter->stats.csummed++;
  1009. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1010. } else
  1011. skb->ip_summed = CHECKSUM_NONE;
  1012. skb->dev = adapter->netdev;
  1013. buffer->skb = NULL;
  1014. no_skb:
  1015. buffer->state = NETXEN_BUFFER_FREE;
  1016. buffer->lro_current_frags = 0;
  1017. buffer->lro_expected_frags = 0;
  1018. list_add_tail(&buffer->list, &rds_ring->free_list);
  1019. return skb;
  1020. }
  1021. /*
  1022. * netxen_process_rcv() send the received packet to the protocol stack.
  1023. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  1024. * invoke the routine to send more rx buffers to the Phantom...
  1025. */
  1026. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  1027. struct status_desc *desc, struct status_desc *frag_desc)
  1028. {
  1029. struct net_device *netdev = adapter->netdev;
  1030. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  1031. int index = netxen_get_sts_refhandle(sts_data);
  1032. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1033. struct netxen_rx_buffer *buffer;
  1034. struct sk_buff *skb;
  1035. u32 length = netxen_get_sts_totallength(sts_data);
  1036. u32 desc_ctx;
  1037. u16 pkt_offset = 0, cksum;
  1038. struct nx_host_rds_ring *rds_ring;
  1039. desc_ctx = netxen_get_sts_type(sts_data);
  1040. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1041. printk("%s: %s Bad Rcv descriptor ring\n",
  1042. netxen_nic_driver_name, netdev->name);
  1043. return;
  1044. }
  1045. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  1046. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  1047. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1048. index, rds_ring->max_rx_desc_count);
  1049. return;
  1050. }
  1051. buffer = &rds_ring->rx_buf_arr[index];
  1052. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1053. buffer->lro_current_frags++;
  1054. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1055. buffer->lro_expected_frags =
  1056. netxen_get_sts_desc_lro_cnt(desc);
  1057. buffer->lro_length = length;
  1058. }
  1059. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1060. if (buffer->lro_expected_frags != 0) {
  1061. printk("LRO: (refhandle:%x) recv frag. "
  1062. "wait for last. flags: %x expected:%d "
  1063. "have:%d\n", index,
  1064. netxen_get_sts_desc_lro_last_frag(desc),
  1065. buffer->lro_expected_frags,
  1066. buffer->lro_current_frags);
  1067. }
  1068. return;
  1069. }
  1070. }
  1071. cksum = netxen_get_sts_status(sts_data);
  1072. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1073. if (!skb)
  1074. return;
  1075. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1076. /* True length was only available on the last pkt */
  1077. skb_put(skb, buffer->lro_length);
  1078. } else {
  1079. if (length > rds_ring->skb_size)
  1080. skb_put(skb, rds_ring->skb_size);
  1081. else
  1082. skb_put(skb, length);
  1083. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1084. if (pkt_offset)
  1085. skb_pull(skb, pkt_offset);
  1086. }
  1087. skb->protocol = eth_type_trans(skb, netdev);
  1088. /*
  1089. * rx buffer chaining is disabled, walk and free
  1090. * any spurious rx buffer chain.
  1091. */
  1092. if (frag_desc) {
  1093. u16 i, nr_frags = desc->nr_frags;
  1094. dev_kfree_skb_any(skb);
  1095. for (i = 0; i < nr_frags; i++) {
  1096. index = frag_desc->frag_handles[i];
  1097. skb = netxen_process_rxbuf(adapter,
  1098. rds_ring, index, cksum);
  1099. if (skb)
  1100. dev_kfree_skb_any(skb);
  1101. }
  1102. adapter->stats.rxdropped++;
  1103. } else {
  1104. netif_receive_skb(skb);
  1105. netdev->last_rx = jiffies;
  1106. adapter->stats.no_rcv++;
  1107. adapter->stats.rxbytes += length;
  1108. }
  1109. }
  1110. /* Process Receive status ring */
  1111. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1112. {
  1113. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1114. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1115. struct status_desc *desc, *frag_desc;
  1116. u32 consumer = recv_ctx->status_rx_consumer;
  1117. int count = 0, ring;
  1118. u64 sts_data;
  1119. u16 opcode;
  1120. while (count < max) {
  1121. desc = &desc_head[consumer];
  1122. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1123. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1124. netxen_get_sts_owner(desc));
  1125. break;
  1126. }
  1127. sts_data = le64_to_cpu(desc->status_desc_data);
  1128. opcode = netxen_get_sts_opcode(sts_data);
  1129. frag_desc = NULL;
  1130. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  1131. if (desc->nr_frags) {
  1132. consumer = get_next_index(consumer,
  1133. adapter->max_rx_desc_count);
  1134. frag_desc = &desc_head[consumer];
  1135. netxen_set_sts_owner(frag_desc,
  1136. STATUS_OWNER_PHANTOM);
  1137. }
  1138. }
  1139. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  1140. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1141. consumer = get_next_index(consumer,
  1142. adapter->max_rx_desc_count);
  1143. count++;
  1144. }
  1145. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  1146. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1147. /* update the consumer index in phantom */
  1148. if (count) {
  1149. recv_ctx->status_rx_consumer = consumer;
  1150. /* Window = 1 */
  1151. adapter->pci_write_normalize(adapter,
  1152. recv_ctx->crb_sts_consumer, consumer);
  1153. }
  1154. return count;
  1155. }
  1156. /* Process Command status ring */
  1157. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1158. {
  1159. u32 last_consumer, consumer;
  1160. int count = 0, i;
  1161. struct netxen_cmd_buffer *buffer;
  1162. struct pci_dev *pdev = adapter->pdev;
  1163. struct net_device *netdev = adapter->netdev;
  1164. struct netxen_skb_frag *frag;
  1165. int done = 0;
  1166. last_consumer = adapter->last_cmd_consumer;
  1167. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1168. while (last_consumer != consumer) {
  1169. buffer = &adapter->cmd_buf_arr[last_consumer];
  1170. if (buffer->skb) {
  1171. frag = &buffer->frag_array[0];
  1172. pci_unmap_single(pdev, frag->dma, frag->length,
  1173. PCI_DMA_TODEVICE);
  1174. frag->dma = 0ULL;
  1175. for (i = 1; i < buffer->frag_count; i++) {
  1176. frag++; /* Get the next frag */
  1177. pci_unmap_page(pdev, frag->dma, frag->length,
  1178. PCI_DMA_TODEVICE);
  1179. frag->dma = 0ULL;
  1180. }
  1181. adapter->stats.xmitfinished++;
  1182. dev_kfree_skb_any(buffer->skb);
  1183. buffer->skb = NULL;
  1184. }
  1185. last_consumer = get_next_index(last_consumer,
  1186. adapter->max_tx_desc_count);
  1187. if (++count >= MAX_STATUS_HANDLE)
  1188. break;
  1189. }
  1190. if (count) {
  1191. adapter->last_cmd_consumer = last_consumer;
  1192. smp_mb();
  1193. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1194. netif_tx_lock(netdev);
  1195. netif_wake_queue(netdev);
  1196. smp_mb();
  1197. netif_tx_unlock(netdev);
  1198. }
  1199. }
  1200. /*
  1201. * If everything is freed up to consumer then check if the ring is full
  1202. * If the ring is full then check if more needs to be freed and
  1203. * schedule the call back again.
  1204. *
  1205. * This happens when there are 2 CPUs. One could be freeing and the
  1206. * other filling it. If the ring is full when we get out of here and
  1207. * the card has already interrupted the host then the host can miss the
  1208. * interrupt.
  1209. *
  1210. * There is still a possible race condition and the host could miss an
  1211. * interrupt. The card has to take care of this.
  1212. */
  1213. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1214. done = (last_consumer == consumer);
  1215. return (done);
  1216. }
  1217. /*
  1218. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1219. */
  1220. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1221. {
  1222. struct pci_dev *pdev = adapter->pdev;
  1223. struct sk_buff *skb;
  1224. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1225. struct nx_host_rds_ring *rds_ring = NULL;
  1226. uint producer;
  1227. struct rcv_desc *pdesc;
  1228. struct netxen_rx_buffer *buffer;
  1229. int count = 0;
  1230. int index = 0;
  1231. netxen_ctx_msg msg = 0;
  1232. dma_addr_t dma;
  1233. struct list_head *head;
  1234. rds_ring = &recv_ctx->rds_rings[ringid];
  1235. producer = rds_ring->producer;
  1236. index = rds_ring->begin_alloc;
  1237. head = &rds_ring->free_list;
  1238. /* We can start writing rx descriptors into the phantom memory. */
  1239. while (!list_empty(head)) {
  1240. skb = dev_alloc_skb(rds_ring->skb_size);
  1241. if (unlikely(!skb)) {
  1242. rds_ring->begin_alloc = index;
  1243. break;
  1244. }
  1245. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1246. list_del(&buffer->list);
  1247. count++; /* now there should be no failure */
  1248. pdesc = &rds_ring->desc_head[producer];
  1249. if (!adapter->ahw.cut_through)
  1250. skb_reserve(skb, 2);
  1251. /* This will be setup when we receive the
  1252. * buffer after it has been filled FSL TBD TBD
  1253. * skb->dev = netdev;
  1254. */
  1255. dma = pci_map_single(pdev, skb->data, rds_ring->dma_size,
  1256. PCI_DMA_FROMDEVICE);
  1257. pdesc->addr_buffer = cpu_to_le64(dma);
  1258. buffer->skb = skb;
  1259. buffer->state = NETXEN_BUFFER_BUSY;
  1260. buffer->dma = dma;
  1261. /* make a rcv descriptor */
  1262. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1263. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1264. DPRINTK(INFO, "done writing descripter\n");
  1265. producer =
  1266. get_next_index(producer, rds_ring->max_rx_desc_count);
  1267. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1268. }
  1269. /* if we did allocate buffers, then write the count to Phantom */
  1270. if (count) {
  1271. rds_ring->begin_alloc = index;
  1272. rds_ring->producer = producer;
  1273. /* Window = 1 */
  1274. adapter->pci_write_normalize(adapter,
  1275. rds_ring->crb_rcv_producer,
  1276. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1277. if (adapter->fw_major < 4) {
  1278. /*
  1279. * Write a doorbell msg to tell phanmon of change in
  1280. * receive ring producer
  1281. * Only for firmware version < 4.0.0
  1282. */
  1283. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1284. netxen_set_msg_privid(msg);
  1285. netxen_set_msg_count(msg,
  1286. ((producer -
  1287. 1) & (rds_ring->
  1288. max_rx_desc_count - 1)));
  1289. netxen_set_msg_ctxid(msg, adapter->portnum);
  1290. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1291. writel(msg,
  1292. DB_NORMALIZE(adapter,
  1293. NETXEN_RCV_PRODUCER_OFFSET));
  1294. }
  1295. }
  1296. }
  1297. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1298. uint32_t ctx, uint32_t ringid)
  1299. {
  1300. struct pci_dev *pdev = adapter->pdev;
  1301. struct sk_buff *skb;
  1302. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1303. struct nx_host_rds_ring *rds_ring = NULL;
  1304. u32 producer;
  1305. struct rcv_desc *pdesc;
  1306. struct netxen_rx_buffer *buffer;
  1307. int count = 0;
  1308. int index = 0;
  1309. struct list_head *head;
  1310. rds_ring = &recv_ctx->rds_rings[ringid];
  1311. producer = rds_ring->producer;
  1312. index = rds_ring->begin_alloc;
  1313. head = &rds_ring->free_list;
  1314. /* We can start writing rx descriptors into the phantom memory. */
  1315. while (!list_empty(head)) {
  1316. skb = dev_alloc_skb(rds_ring->skb_size);
  1317. if (unlikely(!skb)) {
  1318. rds_ring->begin_alloc = index;
  1319. break;
  1320. }
  1321. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1322. list_del(&buffer->list);
  1323. count++; /* now there should be no failure */
  1324. pdesc = &rds_ring->desc_head[producer];
  1325. if (!adapter->ahw.cut_through)
  1326. skb_reserve(skb, 2);
  1327. buffer->skb = skb;
  1328. buffer->state = NETXEN_BUFFER_BUSY;
  1329. buffer->dma = pci_map_single(pdev, skb->data,
  1330. rds_ring->dma_size,
  1331. PCI_DMA_FROMDEVICE);
  1332. /* make a rcv descriptor */
  1333. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1334. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1335. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1336. producer =
  1337. get_next_index(producer, rds_ring->max_rx_desc_count);
  1338. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1339. buffer = &rds_ring->rx_buf_arr[index];
  1340. }
  1341. /* if we did allocate buffers, then write the count to Phantom */
  1342. if (count) {
  1343. rds_ring->begin_alloc = index;
  1344. rds_ring->producer = producer;
  1345. /* Window = 1 */
  1346. adapter->pci_write_normalize(adapter,
  1347. rds_ring->crb_rcv_producer,
  1348. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1349. wmb();
  1350. }
  1351. }
  1352. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1353. {
  1354. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1355. return;
  1356. }