at91sam9g45.dtsi 10 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. dbgu {
  109. pinctrl_dbgu: dbgu-0 {
  110. atmel,pins =
  111. <1 12 0x1 0x0 /* PB12 periph A */
  112. 1 13 0x1 0x0>; /* PB13 periph A */
  113. };
  114. };
  115. uart0 {
  116. pinctrl_uart0: uart0-0 {
  117. atmel,pins =
  118. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  119. 1 18 0x1 0x0>; /* PB18 periph A */
  120. };
  121. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  122. atmel,pins =
  123. <1 17 0x2 0x0 /* PB17 periph B */
  124. 1 15 0x2 0x0>; /* PB15 periph B */
  125. };
  126. };
  127. uart1 {
  128. pinctrl_uart1: uart1-0 {
  129. atmel,pins =
  130. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  131. 1 5 0x1 0x0>; /* PB5 periph A */
  132. };
  133. pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  134. atmel,pins =
  135. <3 16 0x1 0x0 /* PD16 periph A */
  136. 3 17 0x1 0x0>; /* PD17 periph A */
  137. };
  138. };
  139. uart2 {
  140. pinctrl_uart2: uart2-0 {
  141. atmel,pins =
  142. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  143. 1 7 0x1 0x0>; /* PB7 periph A */
  144. };
  145. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  146. atmel,pins =
  147. <2 9 0x2 0x0 /* PC9 periph B */
  148. 2 11 0x2 0x0>; /* PC11 periph B */
  149. };
  150. };
  151. uart3 {
  152. pinctrl_uart3: uart3-0 {
  153. atmel,pins =
  154. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  155. 1 9 0x1 0x0>; /* PB8 periph A */
  156. };
  157. pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  158. atmel,pins =
  159. <0 23 0x2 0x0 /* PA23 periph B */
  160. 0 24 0x2 0x0>; /* PA24 periph B */
  161. };
  162. };
  163. nand {
  164. pinctrl_nand: nand-0 {
  165. atmel,pins =
  166. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  167. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  168. };
  169. };
  170. macb {
  171. pinctrl_macb_rmii: macb_rmii-0 {
  172. atmel,pins =
  173. <0 10 0x1 0x0 /* PA10 periph A */
  174. 0 11 0x1 0x0 /* PA11 periph A */
  175. 0 12 0x1 0x0 /* PA12 periph A */
  176. 0 13 0x1 0x0 /* PA13 periph A */
  177. 0 14 0x1 0x0 /* PA14 periph A */
  178. 0 15 0x1 0x0 /* PA15 periph A */
  179. 0 16 0x1 0x0 /* PA16 periph A */
  180. 0 17 0x1 0x0 /* PA17 periph A */
  181. 0 18 0x1 0x0 /* PA18 periph A */
  182. 0 19 0x1 0x0>; /* PA19 periph A */
  183. };
  184. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  185. atmel,pins =
  186. <0 6 0x2 0x0 /* PA6 periph B */
  187. 0 7 0x2 0x0 /* PA7 periph B */
  188. 0 8 0x2 0x0 /* PA8 periph B */
  189. 0 9 0x2 0x0 /* PA9 periph B */
  190. 0 27 0x2 0x0 /* PA27 periph B */
  191. 0 28 0x2 0x0 /* PA28 periph B */
  192. 0 29 0x2 0x0 /* PA29 periph B */
  193. 0 30 0x2 0x0>; /* PA30 periph B */
  194. };
  195. };
  196. pioA: gpio@fffff200 {
  197. compatible = "atmel,at91rm9200-gpio";
  198. reg = <0xfffff200 0x200>;
  199. interrupts = <2 4 1>;
  200. #gpio-cells = <2>;
  201. gpio-controller;
  202. interrupt-controller;
  203. #interrupt-cells = <2>;
  204. };
  205. pioB: gpio@fffff400 {
  206. compatible = "atmel,at91rm9200-gpio";
  207. reg = <0xfffff400 0x200>;
  208. interrupts = <3 4 1>;
  209. #gpio-cells = <2>;
  210. gpio-controller;
  211. interrupt-controller;
  212. #interrupt-cells = <2>;
  213. };
  214. pioC: gpio@fffff600 {
  215. compatible = "atmel,at91rm9200-gpio";
  216. reg = <0xfffff600 0x200>;
  217. interrupts = <4 4 1>;
  218. #gpio-cells = <2>;
  219. gpio-controller;
  220. interrupt-controller;
  221. #interrupt-cells = <2>;
  222. };
  223. pioD: gpio@fffff800 {
  224. compatible = "atmel,at91rm9200-gpio";
  225. reg = <0xfffff800 0x200>;
  226. interrupts = <5 4 1>;
  227. #gpio-cells = <2>;
  228. gpio-controller;
  229. interrupt-controller;
  230. #interrupt-cells = <2>;
  231. };
  232. pioE: gpio@fffffa00 {
  233. compatible = "atmel,at91rm9200-gpio";
  234. reg = <0xfffffa00 0x200>;
  235. interrupts = <5 4 1>;
  236. #gpio-cells = <2>;
  237. gpio-controller;
  238. interrupt-controller;
  239. #interrupt-cells = <2>;
  240. };
  241. };
  242. dbgu: serial@ffffee00 {
  243. compatible = "atmel,at91sam9260-usart";
  244. reg = <0xffffee00 0x200>;
  245. interrupts = <1 4 7>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_dbgu>;
  248. status = "disabled";
  249. };
  250. usart0: serial@fff8c000 {
  251. compatible = "atmel,at91sam9260-usart";
  252. reg = <0xfff8c000 0x200>;
  253. interrupts = <7 4 5>;
  254. atmel,use-dma-rx;
  255. atmel,use-dma-tx;
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_uart0>;
  258. status = "disabled";
  259. };
  260. usart1: serial@fff90000 {
  261. compatible = "atmel,at91sam9260-usart";
  262. reg = <0xfff90000 0x200>;
  263. interrupts = <8 4 5>;
  264. atmel,use-dma-rx;
  265. atmel,use-dma-tx;
  266. pinctrl-names = "default";
  267. pinctrl-0 = <&pinctrl_uart1>;
  268. status = "disabled";
  269. };
  270. usart2: serial@fff94000 {
  271. compatible = "atmel,at91sam9260-usart";
  272. reg = <0xfff94000 0x200>;
  273. interrupts = <9 4 5>;
  274. atmel,use-dma-rx;
  275. atmel,use-dma-tx;
  276. pinctrl-names = "default";
  277. pinctrl-0 = <&pinctrl_uart2>;
  278. status = "disabled";
  279. };
  280. usart3: serial@fff98000 {
  281. compatible = "atmel,at91sam9260-usart";
  282. reg = <0xfff98000 0x200>;
  283. interrupts = <10 4 5>;
  284. atmel,use-dma-rx;
  285. atmel,use-dma-tx;
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_uart3>;
  288. status = "disabled";
  289. };
  290. macb0: ethernet@fffbc000 {
  291. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  292. reg = <0xfffbc000 0x100>;
  293. interrupts = <25 4 3>;
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_macb_rmii>;
  296. status = "disabled";
  297. };
  298. i2c0: i2c@fff84000 {
  299. compatible = "atmel,at91sam9g10-i2c";
  300. reg = <0xfff84000 0x100>;
  301. interrupts = <12 4 6>;
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304. status = "disabled";
  305. };
  306. i2c1: i2c@fff88000 {
  307. compatible = "atmel,at91sam9g10-i2c";
  308. reg = <0xfff88000 0x100>;
  309. interrupts = <13 4 6>;
  310. #address-cells = <1>;
  311. #size-cells = <0>;
  312. status = "disabled";
  313. };
  314. adc0: adc@fffb0000 {
  315. compatible = "atmel,at91sam9260-adc";
  316. reg = <0xfffb0000 0x100>;
  317. interrupts = <20 4 0>;
  318. atmel,adc-use-external-triggers;
  319. atmel,adc-channels-used = <0xff>;
  320. atmel,adc-vref = <3300>;
  321. atmel,adc-num-channels = <8>;
  322. atmel,adc-startup-time = <40>;
  323. atmel,adc-channel-base = <0x30>;
  324. atmel,adc-drdy-mask = <0x10000>;
  325. atmel,adc-status-register = <0x1c>;
  326. atmel,adc-trigger-register = <0x08>;
  327. trigger@0 {
  328. trigger-name = "external-rising";
  329. trigger-value = <0x1>;
  330. trigger-external;
  331. };
  332. trigger@1 {
  333. trigger-name = "external-falling";
  334. trigger-value = <0x2>;
  335. trigger-external;
  336. };
  337. trigger@2 {
  338. trigger-name = "external-any";
  339. trigger-value = <0x3>;
  340. trigger-external;
  341. };
  342. trigger@3 {
  343. trigger-name = "continuous";
  344. trigger-value = <0x6>;
  345. };
  346. };
  347. };
  348. nand0: nand@40000000 {
  349. compatible = "atmel,at91rm9200-nand";
  350. #address-cells = <1>;
  351. #size-cells = <1>;
  352. reg = <0x40000000 0x10000000
  353. 0xffffe200 0x200
  354. >;
  355. atmel,nand-addr-offset = <21>;
  356. atmel,nand-cmd-offset = <22>;
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&pinctrl_nand>;
  359. gpios = <&pioC 8 0
  360. &pioC 14 0
  361. 0
  362. >;
  363. status = "disabled";
  364. };
  365. usb0: ohci@00700000 {
  366. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  367. reg = <0x00700000 0x100000>;
  368. interrupts = <22 4 2>;
  369. status = "disabled";
  370. };
  371. usb1: ehci@00800000 {
  372. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  373. reg = <0x00800000 0x100000>;
  374. interrupts = <22 4 2>;
  375. status = "disabled";
  376. };
  377. };
  378. i2c@0 {
  379. compatible = "i2c-gpio";
  380. gpios = <&pioA 20 0 /* sda */
  381. &pioA 21 0 /* scl */
  382. >;
  383. i2c-gpio,sda-open-drain;
  384. i2c-gpio,scl-open-drain;
  385. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  386. #address-cells = <1>;
  387. #size-cells = <0>;
  388. status = "disabled";
  389. };
  390. };