vmwgfx_kms.c 48 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. if (handle) {
  92. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  93. handle, &surface);
  94. if (!ret) {
  95. if (!surface->snooper.image) {
  96. DRM_ERROR("surface not suitable for cursor\n");
  97. return -EINVAL;
  98. }
  99. } else {
  100. ret = vmw_user_dmabuf_lookup(tfile,
  101. handle, &dmabuf);
  102. if (ret) {
  103. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  104. return -EINVAL;
  105. }
  106. }
  107. }
  108. /* takedown old cursor */
  109. if (du->cursor_surface) {
  110. du->cursor_surface->snooper.crtc = NULL;
  111. vmw_surface_unreference(&du->cursor_surface);
  112. }
  113. if (du->cursor_dmabuf)
  114. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  115. /* setup new image */
  116. if (surface) {
  117. /* vmw_user_surface_lookup takes one reference */
  118. du->cursor_surface = surface;
  119. du->cursor_surface->snooper.crtc = crtc;
  120. du->cursor_age = du->cursor_surface->snooper.age;
  121. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  122. 64, 64, du->hotspot_x, du->hotspot_y);
  123. } else if (dmabuf) {
  124. struct ttm_bo_kmap_obj map;
  125. unsigned long kmap_offset;
  126. unsigned long kmap_num;
  127. void *virtual;
  128. bool dummy;
  129. /* vmw_user_surface_lookup takes one reference */
  130. du->cursor_dmabuf = dmabuf;
  131. kmap_offset = 0;
  132. kmap_num = (64*64*4) >> PAGE_SHIFT;
  133. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  134. if (unlikely(ret != 0)) {
  135. DRM_ERROR("reserve failed\n");
  136. return -EINVAL;
  137. }
  138. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  139. if (unlikely(ret != 0))
  140. goto err_unreserve;
  141. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  142. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  143. du->hotspot_x, du->hotspot_y);
  144. ttm_bo_kunmap(&map);
  145. err_unreserve:
  146. ttm_bo_unreserve(&dmabuf->base);
  147. } else {
  148. vmw_cursor_update_position(dev_priv, false, 0, 0);
  149. return 0;
  150. }
  151. vmw_cursor_update_position(dev_priv, true,
  152. du->cursor_x + du->hotspot_x,
  153. du->cursor_y + du->hotspot_y);
  154. return 0;
  155. }
  156. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  157. {
  158. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  159. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  160. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  161. du->cursor_x = x + crtc->x;
  162. du->cursor_y = y + crtc->y;
  163. vmw_cursor_update_position(dev_priv, shown,
  164. du->cursor_x + du->hotspot_x,
  165. du->cursor_y + du->hotspot_y);
  166. return 0;
  167. }
  168. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  169. struct ttm_object_file *tfile,
  170. struct ttm_buffer_object *bo,
  171. SVGA3dCmdHeader *header)
  172. {
  173. struct ttm_bo_kmap_obj map;
  174. unsigned long kmap_offset;
  175. unsigned long kmap_num;
  176. SVGA3dCopyBox *box;
  177. unsigned box_count;
  178. void *virtual;
  179. bool dummy;
  180. struct vmw_dma_cmd {
  181. SVGA3dCmdHeader header;
  182. SVGA3dCmdSurfaceDMA dma;
  183. } *cmd;
  184. int ret;
  185. cmd = container_of(header, struct vmw_dma_cmd, header);
  186. /* No snooper installed */
  187. if (!srf->snooper.image)
  188. return;
  189. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  190. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  191. return;
  192. }
  193. if (cmd->header.size < 64) {
  194. DRM_ERROR("at least one full copy box must be given\n");
  195. return;
  196. }
  197. box = (SVGA3dCopyBox *)&cmd[1];
  198. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  199. sizeof(SVGA3dCopyBox);
  200. if (cmd->dma.guest.pitch != (64 * 4) ||
  201. cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  202. box->x != 0 || box->y != 0 || box->z != 0 ||
  203. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  204. box->w != 64 || box->h != 64 || box->d != 1 ||
  205. box_count != 1) {
  206. /* TODO handle none page aligned offsets */
  207. /* TODO handle partial uploads and pitch != 256 */
  208. /* TODO handle more then one copy (size != 64) */
  209. DRM_ERROR("lazy programmer, can't handle weird stuff\n");
  210. return;
  211. }
  212. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  213. kmap_num = (64*64*4) >> PAGE_SHIFT;
  214. ret = ttm_bo_reserve(bo, true, false, false, 0);
  215. if (unlikely(ret != 0)) {
  216. DRM_ERROR("reserve failed\n");
  217. return;
  218. }
  219. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  220. if (unlikely(ret != 0))
  221. goto err_unreserve;
  222. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  223. memcpy(srf->snooper.image, virtual, 64*64*4);
  224. srf->snooper.age++;
  225. /* we can't call this function from this function since execbuf has
  226. * reserved fifo space.
  227. *
  228. * if (srf->snooper.crtc)
  229. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  230. * srf->snooper.image, 64, 64,
  231. * du->hotspot_x, du->hotspot_y);
  232. */
  233. ttm_bo_kunmap(&map);
  234. err_unreserve:
  235. ttm_bo_unreserve(bo);
  236. }
  237. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  238. {
  239. struct drm_device *dev = dev_priv->dev;
  240. struct vmw_display_unit *du;
  241. struct drm_crtc *crtc;
  242. mutex_lock(&dev->mode_config.mutex);
  243. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  244. du = vmw_crtc_to_du(crtc);
  245. if (!du->cursor_surface ||
  246. du->cursor_age == du->cursor_surface->snooper.age)
  247. continue;
  248. du->cursor_age = du->cursor_surface->snooper.age;
  249. vmw_cursor_update_image(dev_priv,
  250. du->cursor_surface->snooper.image,
  251. 64, 64, du->hotspot_x, du->hotspot_y);
  252. }
  253. mutex_unlock(&dev->mode_config.mutex);
  254. }
  255. /*
  256. * Generic framebuffer code
  257. */
  258. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  259. struct drm_file *file_priv,
  260. unsigned int *handle)
  261. {
  262. if (handle)
  263. handle = 0;
  264. return 0;
  265. }
  266. /*
  267. * Surface framebuffer code
  268. */
  269. #define vmw_framebuffer_to_vfbs(x) \
  270. container_of(x, struct vmw_framebuffer_surface, base.base)
  271. struct vmw_framebuffer_surface {
  272. struct vmw_framebuffer base;
  273. struct vmw_surface *surface;
  274. struct vmw_dma_buffer *buffer;
  275. struct list_head head;
  276. struct drm_master *master;
  277. };
  278. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  279. {
  280. struct vmw_framebuffer_surface *vfbs =
  281. vmw_framebuffer_to_vfbs(framebuffer);
  282. struct vmw_master *vmaster = vmw_master(vfbs->master);
  283. mutex_lock(&vmaster->fb_surf_mutex);
  284. list_del(&vfbs->head);
  285. mutex_unlock(&vmaster->fb_surf_mutex);
  286. drm_master_put(&vfbs->master);
  287. drm_framebuffer_cleanup(framebuffer);
  288. vmw_surface_unreference(&vfbs->surface);
  289. ttm_base_object_unref(&vfbs->base.user_obj);
  290. kfree(vfbs);
  291. }
  292. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  293. struct drm_file *file_priv,
  294. struct vmw_framebuffer *framebuffer,
  295. unsigned flags, unsigned color,
  296. struct drm_clip_rect *clips,
  297. unsigned num_clips, int inc)
  298. {
  299. struct drm_clip_rect *clips_ptr;
  300. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  301. struct drm_crtc *crtc;
  302. size_t fifo_size;
  303. int i, num_units;
  304. int ret = 0; /* silence warning */
  305. int left, right, top, bottom;
  306. struct {
  307. SVGA3dCmdHeader header;
  308. SVGA3dCmdBlitSurfaceToScreen body;
  309. } *cmd;
  310. SVGASignedRect *blits;
  311. num_units = 0;
  312. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  313. head) {
  314. if (crtc->fb != &framebuffer->base)
  315. continue;
  316. units[num_units++] = vmw_crtc_to_du(crtc);
  317. }
  318. BUG_ON(!clips || !num_clips);
  319. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  320. cmd = kzalloc(fifo_size, GFP_KERNEL);
  321. if (unlikely(cmd == NULL)) {
  322. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  323. return -ENOMEM;
  324. }
  325. left = clips->x1;
  326. right = clips->x2;
  327. top = clips->y1;
  328. bottom = clips->y2;
  329. clips_ptr = clips;
  330. for (i = 1; i < num_clips; i++, clips_ptr += inc) {
  331. left = min_t(int, left, (int)clips_ptr->x1);
  332. right = max_t(int, right, (int)clips_ptr->x2);
  333. top = min_t(int, top, (int)clips_ptr->y1);
  334. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  335. }
  336. /* only need to do this once */
  337. memset(cmd, 0, fifo_size);
  338. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  339. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  340. cmd->body.srcRect.left = left;
  341. cmd->body.srcRect.right = right;
  342. cmd->body.srcRect.top = top;
  343. cmd->body.srcRect.bottom = bottom;
  344. clips_ptr = clips;
  345. blits = (SVGASignedRect *)&cmd[1];
  346. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  347. blits[i].left = clips_ptr->x1 - left;
  348. blits[i].right = clips_ptr->x2 - left;
  349. blits[i].top = clips_ptr->y1 - top;
  350. blits[i].bottom = clips_ptr->y2 - top;
  351. }
  352. /* do per unit writing, reuse fifo for each */
  353. for (i = 0; i < num_units; i++) {
  354. struct vmw_display_unit *unit = units[i];
  355. int clip_x1 = left - unit->crtc.x;
  356. int clip_y1 = top - unit->crtc.y;
  357. int clip_x2 = right - unit->crtc.x;
  358. int clip_y2 = bottom - unit->crtc.y;
  359. /* skip any crtcs that misses the clip region */
  360. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  361. clip_y1 >= unit->crtc.mode.vdisplay ||
  362. clip_x2 <= 0 || clip_y2 <= 0)
  363. continue;
  364. /* need to reset sid as it is changed by execbuf */
  365. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  366. cmd->body.destScreenId = unit->unit;
  367. /*
  368. * The blit command is a lot more resilient then the
  369. * readback command when it comes to clip rects. So its
  370. * okay to go out of bounds.
  371. */
  372. cmd->body.destRect.left = clip_x1;
  373. cmd->body.destRect.right = clip_x2;
  374. cmd->body.destRect.top = clip_y1;
  375. cmd->body.destRect.bottom = clip_y2;
  376. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  377. fifo_size, 0, NULL);
  378. if (unlikely(ret != 0))
  379. break;
  380. }
  381. kfree(cmd);
  382. return ret;
  383. }
  384. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  385. struct drm_file *file_priv,
  386. unsigned flags, unsigned color,
  387. struct drm_clip_rect *clips,
  388. unsigned num_clips)
  389. {
  390. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  391. struct vmw_master *vmaster = vmw_master(file_priv->master);
  392. struct vmw_framebuffer_surface *vfbs =
  393. vmw_framebuffer_to_vfbs(framebuffer);
  394. struct drm_clip_rect norect;
  395. int ret, inc = 1;
  396. if (unlikely(vfbs->master != file_priv->master))
  397. return -EINVAL;
  398. /* Require ScreenObject support for 3D */
  399. if (!dev_priv->sou_priv)
  400. return -EINVAL;
  401. ret = ttm_read_lock(&vmaster->lock, true);
  402. if (unlikely(ret != 0))
  403. return ret;
  404. if (!num_clips) {
  405. num_clips = 1;
  406. clips = &norect;
  407. norect.x1 = norect.y1 = 0;
  408. norect.x2 = framebuffer->width;
  409. norect.y2 = framebuffer->height;
  410. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  411. num_clips /= 2;
  412. inc = 2; /* skip source rects */
  413. }
  414. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  415. flags, color,
  416. clips, num_clips, inc);
  417. ttm_read_unlock(&vmaster->lock);
  418. return 0;
  419. }
  420. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  421. .destroy = vmw_framebuffer_surface_destroy,
  422. .dirty = vmw_framebuffer_surface_dirty,
  423. .create_handle = vmw_framebuffer_create_handle,
  424. };
  425. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  426. struct drm_file *file_priv,
  427. struct vmw_surface *surface,
  428. struct vmw_framebuffer **out,
  429. const struct drm_mode_fb_cmd
  430. *mode_cmd)
  431. {
  432. struct drm_device *dev = dev_priv->dev;
  433. struct vmw_framebuffer_surface *vfbs;
  434. enum SVGA3dSurfaceFormat format;
  435. struct vmw_master *vmaster = vmw_master(file_priv->master);
  436. int ret;
  437. /* 3D is only supported on HWv8 hosts which supports screen objects */
  438. if (!dev_priv->sou_priv)
  439. return -ENOSYS;
  440. /*
  441. * Sanity checks.
  442. */
  443. if (unlikely(surface->mip_levels[0] != 1 ||
  444. surface->num_sizes != 1 ||
  445. surface->sizes[0].width < mode_cmd->width ||
  446. surface->sizes[0].height < mode_cmd->height ||
  447. surface->sizes[0].depth != 1)) {
  448. DRM_ERROR("Incompatible surface dimensions "
  449. "for requested mode.\n");
  450. return -EINVAL;
  451. }
  452. switch (mode_cmd->depth) {
  453. case 32:
  454. format = SVGA3D_A8R8G8B8;
  455. break;
  456. case 24:
  457. format = SVGA3D_X8R8G8B8;
  458. break;
  459. case 16:
  460. format = SVGA3D_R5G6B5;
  461. break;
  462. case 15:
  463. format = SVGA3D_A1R5G5B5;
  464. break;
  465. case 8:
  466. format = SVGA3D_LUMINANCE8;
  467. break;
  468. default:
  469. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  470. return -EINVAL;
  471. }
  472. if (unlikely(format != surface->format)) {
  473. DRM_ERROR("Invalid surface format for requested mode.\n");
  474. return -EINVAL;
  475. }
  476. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  477. if (!vfbs) {
  478. ret = -ENOMEM;
  479. goto out_err1;
  480. }
  481. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  482. &vmw_framebuffer_surface_funcs);
  483. if (ret)
  484. goto out_err2;
  485. if (!vmw_surface_reference(surface)) {
  486. DRM_ERROR("failed to reference surface %p\n", surface);
  487. goto out_err3;
  488. }
  489. /* XXX get the first 3 from the surface info */
  490. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  491. vfbs->base.base.pitch = mode_cmd->pitch;
  492. vfbs->base.base.depth = mode_cmd->depth;
  493. vfbs->base.base.width = mode_cmd->width;
  494. vfbs->base.base.height = mode_cmd->height;
  495. vfbs->surface = surface;
  496. vfbs->base.user_handle = mode_cmd->handle;
  497. vfbs->master = drm_master_get(file_priv->master);
  498. mutex_lock(&vmaster->fb_surf_mutex);
  499. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  500. mutex_unlock(&vmaster->fb_surf_mutex);
  501. *out = &vfbs->base;
  502. return 0;
  503. out_err3:
  504. drm_framebuffer_cleanup(&vfbs->base.base);
  505. out_err2:
  506. kfree(vfbs);
  507. out_err1:
  508. return ret;
  509. }
  510. /*
  511. * Dmabuf framebuffer code
  512. */
  513. #define vmw_framebuffer_to_vfbd(x) \
  514. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  515. struct vmw_framebuffer_dmabuf {
  516. struct vmw_framebuffer base;
  517. struct vmw_dma_buffer *buffer;
  518. };
  519. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  520. {
  521. struct vmw_framebuffer_dmabuf *vfbd =
  522. vmw_framebuffer_to_vfbd(framebuffer);
  523. drm_framebuffer_cleanup(framebuffer);
  524. vmw_dmabuf_unreference(&vfbd->buffer);
  525. ttm_base_object_unref(&vfbd->base.user_obj);
  526. kfree(vfbd);
  527. }
  528. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  529. struct vmw_framebuffer *framebuffer,
  530. unsigned flags, unsigned color,
  531. struct drm_clip_rect *clips,
  532. unsigned num_clips, int increment)
  533. {
  534. size_t fifo_size;
  535. int i;
  536. struct {
  537. uint32_t header;
  538. SVGAFifoCmdUpdate body;
  539. } *cmd;
  540. fifo_size = sizeof(*cmd) * num_clips;
  541. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  542. if (unlikely(cmd == NULL)) {
  543. DRM_ERROR("Fifo reserve failed.\n");
  544. return -ENOMEM;
  545. }
  546. memset(cmd, 0, fifo_size);
  547. for (i = 0; i < num_clips; i++, clips += increment) {
  548. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  549. cmd[i].body.x = cpu_to_le32(clips->x1);
  550. cmd[i].body.y = cpu_to_le32(clips->y1);
  551. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  552. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  553. }
  554. vmw_fifo_commit(dev_priv, fifo_size);
  555. return 0;
  556. }
  557. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  558. struct vmw_private *dev_priv,
  559. struct vmw_framebuffer *framebuffer)
  560. {
  561. int depth = framebuffer->base.depth;
  562. size_t fifo_size;
  563. int ret;
  564. struct {
  565. uint32_t header;
  566. SVGAFifoCmdDefineGMRFB body;
  567. } *cmd;
  568. /* Emulate RGBA support, contrary to svga_reg.h this is not
  569. * supported by hosts. This is only a problem if we are reading
  570. * this value later and expecting what we uploaded back.
  571. */
  572. if (depth == 32)
  573. depth = 24;
  574. fifo_size = sizeof(*cmd);
  575. cmd = kmalloc(fifo_size, GFP_KERNEL);
  576. if (unlikely(cmd == NULL)) {
  577. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  578. return -ENOMEM;
  579. }
  580. memset(cmd, 0, fifo_size);
  581. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  582. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  583. cmd->body.format.colorDepth = depth;
  584. cmd->body.format.reserved = 0;
  585. cmd->body.bytesPerLine = framebuffer->base.pitch;
  586. cmd->body.ptr.gmrId = framebuffer->user_handle;
  587. cmd->body.ptr.offset = 0;
  588. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  589. fifo_size, 0, NULL);
  590. kfree(cmd);
  591. return ret;
  592. }
  593. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  594. struct vmw_private *dev_priv,
  595. struct vmw_framebuffer *framebuffer,
  596. unsigned flags, unsigned color,
  597. struct drm_clip_rect *clips,
  598. unsigned num_clips, int increment)
  599. {
  600. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  601. struct drm_clip_rect *clips_ptr;
  602. int i, k, num_units, ret;
  603. struct drm_crtc *crtc;
  604. size_t fifo_size;
  605. struct {
  606. uint32_t header;
  607. SVGAFifoCmdBlitGMRFBToScreen body;
  608. } *blits;
  609. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  610. if (unlikely(ret != 0))
  611. return ret; /* define_gmrfb prints warnings */
  612. fifo_size = sizeof(*blits) * num_clips;
  613. blits = kmalloc(fifo_size, GFP_KERNEL);
  614. if (unlikely(blits == NULL)) {
  615. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  616. return -ENOMEM;
  617. }
  618. num_units = 0;
  619. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  620. if (crtc->fb != &framebuffer->base)
  621. continue;
  622. units[num_units++] = vmw_crtc_to_du(crtc);
  623. }
  624. for (k = 0; k < num_units; k++) {
  625. struct vmw_display_unit *unit = units[k];
  626. int hit_num = 0;
  627. clips_ptr = clips;
  628. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  629. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  630. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  631. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  632. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  633. /* skip any crtcs that misses the clip region */
  634. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  635. clip_y1 >= unit->crtc.mode.vdisplay ||
  636. clip_x2 <= 0 || clip_y2 <= 0)
  637. continue;
  638. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  639. blits[hit_num].body.destScreenId = unit->unit;
  640. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  641. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  642. blits[hit_num].body.destRect.left = clip_x1;
  643. blits[hit_num].body.destRect.top = clip_y1;
  644. blits[hit_num].body.destRect.right = clip_x2;
  645. blits[hit_num].body.destRect.bottom = clip_y2;
  646. hit_num++;
  647. }
  648. /* no clips hit the crtc */
  649. if (hit_num == 0)
  650. continue;
  651. fifo_size = sizeof(*blits) * hit_num;
  652. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  653. fifo_size, 0, NULL);
  654. if (unlikely(ret != 0))
  655. break;
  656. }
  657. kfree(blits);
  658. return ret;
  659. }
  660. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  661. struct drm_file *file_priv,
  662. unsigned flags, unsigned color,
  663. struct drm_clip_rect *clips,
  664. unsigned num_clips)
  665. {
  666. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  667. struct vmw_master *vmaster = vmw_master(file_priv->master);
  668. struct vmw_framebuffer_dmabuf *vfbd =
  669. vmw_framebuffer_to_vfbd(framebuffer);
  670. struct drm_clip_rect norect;
  671. int ret, increment = 1;
  672. ret = ttm_read_lock(&vmaster->lock, true);
  673. if (unlikely(ret != 0))
  674. return ret;
  675. if (!num_clips) {
  676. num_clips = 1;
  677. clips = &norect;
  678. norect.x1 = norect.y1 = 0;
  679. norect.x2 = framebuffer->width;
  680. norect.y2 = framebuffer->height;
  681. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  682. num_clips /= 2;
  683. increment = 2;
  684. }
  685. if (dev_priv->ldu_priv) {
  686. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  687. flags, color,
  688. clips, num_clips, increment);
  689. } else {
  690. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  691. flags, color,
  692. clips, num_clips, increment);
  693. }
  694. ttm_read_unlock(&vmaster->lock);
  695. return ret;
  696. }
  697. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  698. .destroy = vmw_framebuffer_dmabuf_destroy,
  699. .dirty = vmw_framebuffer_dmabuf_dirty,
  700. .create_handle = vmw_framebuffer_create_handle,
  701. };
  702. /**
  703. * Pin the dmabuffer to the start of vram.
  704. */
  705. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  706. {
  707. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  708. struct vmw_framebuffer_dmabuf *vfbd =
  709. vmw_framebuffer_to_vfbd(&vfb->base);
  710. int ret;
  711. /* This code should not be used with screen objects */
  712. BUG_ON(dev_priv->sou_priv);
  713. vmw_overlay_pause_all(dev_priv);
  714. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  715. vmw_overlay_resume_all(dev_priv);
  716. WARN_ON(ret != 0);
  717. return 0;
  718. }
  719. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  720. {
  721. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  722. struct vmw_framebuffer_dmabuf *vfbd =
  723. vmw_framebuffer_to_vfbd(&vfb->base);
  724. if (!vfbd->buffer) {
  725. WARN_ON(!vfbd->buffer);
  726. return 0;
  727. }
  728. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  729. }
  730. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  731. struct vmw_dma_buffer *dmabuf,
  732. struct vmw_framebuffer **out,
  733. const struct drm_mode_fb_cmd
  734. *mode_cmd)
  735. {
  736. struct drm_device *dev = dev_priv->dev;
  737. struct vmw_framebuffer_dmabuf *vfbd;
  738. unsigned int requested_size;
  739. int ret;
  740. requested_size = mode_cmd->height * mode_cmd->pitch;
  741. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  742. DRM_ERROR("Screen buffer object size is too small "
  743. "for requested mode.\n");
  744. return -EINVAL;
  745. }
  746. /* Limited framebuffer color depth support for screen objects */
  747. if (dev_priv->sou_priv) {
  748. switch (mode_cmd->depth) {
  749. case 32:
  750. case 24:
  751. /* Only support 32 bpp for 32 and 24 depth fbs */
  752. if (mode_cmd->bpp == 32)
  753. break;
  754. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  755. mode_cmd->depth, mode_cmd->bpp);
  756. return -EINVAL;
  757. case 16:
  758. case 15:
  759. /* Only support 16 bpp for 16 and 15 depth fbs */
  760. if (mode_cmd->bpp == 16)
  761. break;
  762. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  763. mode_cmd->depth, mode_cmd->bpp);
  764. return -EINVAL;
  765. default:
  766. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  767. return -EINVAL;
  768. }
  769. }
  770. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  771. if (!vfbd) {
  772. ret = -ENOMEM;
  773. goto out_err1;
  774. }
  775. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  776. &vmw_framebuffer_dmabuf_funcs);
  777. if (ret)
  778. goto out_err2;
  779. if (!vmw_dmabuf_reference(dmabuf)) {
  780. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  781. goto out_err3;
  782. }
  783. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  784. vfbd->base.base.pitch = mode_cmd->pitch;
  785. vfbd->base.base.depth = mode_cmd->depth;
  786. vfbd->base.base.width = mode_cmd->width;
  787. vfbd->base.base.height = mode_cmd->height;
  788. if (!dev_priv->sou_priv) {
  789. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  790. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  791. }
  792. vfbd->base.dmabuf = true;
  793. vfbd->buffer = dmabuf;
  794. vfbd->base.user_handle = mode_cmd->handle;
  795. *out = &vfbd->base;
  796. return 0;
  797. out_err3:
  798. drm_framebuffer_cleanup(&vfbd->base.base);
  799. out_err2:
  800. kfree(vfbd);
  801. out_err1:
  802. return ret;
  803. }
  804. /*
  805. * Generic Kernel modesetting functions
  806. */
  807. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  808. struct drm_file *file_priv,
  809. struct drm_mode_fb_cmd *mode_cmd)
  810. {
  811. struct vmw_private *dev_priv = vmw_priv(dev);
  812. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  813. struct vmw_framebuffer *vfb = NULL;
  814. struct vmw_surface *surface = NULL;
  815. struct vmw_dma_buffer *bo = NULL;
  816. struct ttm_base_object *user_obj;
  817. u64 required_size;
  818. int ret;
  819. /**
  820. * This code should be conditioned on Screen Objects not being used.
  821. * If screen objects are used, we can allocate a GMR to hold the
  822. * requested framebuffer.
  823. */
  824. required_size = mode_cmd->pitch * mode_cmd->height;
  825. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  826. DRM_ERROR("VRAM size is too small for requested mode.\n");
  827. return ERR_PTR(-ENOMEM);
  828. }
  829. /*
  830. * Take a reference on the user object of the resource
  831. * backing the kms fb. This ensures that user-space handle
  832. * lookups on that resource will always work as long as
  833. * it's registered with a kms framebuffer. This is important,
  834. * since vmw_execbuf_process identifies resources in the
  835. * command stream using user-space handles.
  836. */
  837. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  838. if (unlikely(user_obj == NULL)) {
  839. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  840. return ERR_PTR(-ENOENT);
  841. }
  842. /**
  843. * End conditioned code.
  844. */
  845. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  846. mode_cmd->handle, &surface);
  847. if (ret)
  848. goto try_dmabuf;
  849. if (!surface->scanout)
  850. goto err_not_scanout;
  851. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  852. &vfb, mode_cmd);
  853. /* vmw_user_surface_lookup takes one ref so does new_fb */
  854. vmw_surface_unreference(&surface);
  855. if (ret) {
  856. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  857. ttm_base_object_unref(&user_obj);
  858. return ERR_PTR(ret);
  859. } else
  860. vfb->user_obj = user_obj;
  861. return &vfb->base;
  862. try_dmabuf:
  863. DRM_INFO("%s: trying buffer\n", __func__);
  864. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  865. if (ret) {
  866. DRM_ERROR("failed to find buffer: %i\n", ret);
  867. return ERR_PTR(-ENOENT);
  868. }
  869. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  870. mode_cmd);
  871. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  872. vmw_dmabuf_unreference(&bo);
  873. if (ret) {
  874. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  875. ttm_base_object_unref(&user_obj);
  876. return ERR_PTR(ret);
  877. } else
  878. vfb->user_obj = user_obj;
  879. return &vfb->base;
  880. err_not_scanout:
  881. DRM_ERROR("surface not marked as scanout\n");
  882. /* vmw_user_surface_lookup takes one ref */
  883. vmw_surface_unreference(&surface);
  884. ttm_base_object_unref(&user_obj);
  885. return ERR_PTR(-EINVAL);
  886. }
  887. static struct drm_mode_config_funcs vmw_kms_funcs = {
  888. .fb_create = vmw_kms_fb_create,
  889. };
  890. int vmw_kms_present(struct vmw_private *dev_priv,
  891. struct drm_file *file_priv,
  892. struct vmw_framebuffer *vfb,
  893. struct vmw_surface *surface,
  894. uint32_t sid,
  895. int32_t destX, int32_t destY,
  896. struct drm_vmw_rect *clips,
  897. uint32_t num_clips)
  898. {
  899. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  900. struct drm_crtc *crtc;
  901. size_t fifo_size;
  902. int i, k, num_units;
  903. int ret = 0; /* silence warning */
  904. struct {
  905. SVGA3dCmdHeader header;
  906. SVGA3dCmdBlitSurfaceToScreen body;
  907. } *cmd;
  908. SVGASignedRect *blits;
  909. num_units = 0;
  910. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  911. if (crtc->fb != &vfb->base)
  912. continue;
  913. units[num_units++] = vmw_crtc_to_du(crtc);
  914. }
  915. BUG_ON(surface == NULL);
  916. BUG_ON(!clips || !num_clips);
  917. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  918. cmd = kmalloc(fifo_size, GFP_KERNEL);
  919. if (unlikely(cmd == NULL)) {
  920. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  921. return -ENOMEM;
  922. }
  923. /* only need to do this once */
  924. memset(cmd, 0, fifo_size);
  925. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  926. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  927. cmd->body.srcRect.left = 0;
  928. cmd->body.srcRect.right = surface->sizes[0].width;
  929. cmd->body.srcRect.top = 0;
  930. cmd->body.srcRect.bottom = surface->sizes[0].height;
  931. blits = (SVGASignedRect *)&cmd[1];
  932. for (i = 0; i < num_clips; i++) {
  933. blits[i].left = clips[i].x;
  934. blits[i].right = clips[i].x + clips[i].w;
  935. blits[i].top = clips[i].y;
  936. blits[i].bottom = clips[i].y + clips[i].h;
  937. }
  938. for (k = 0; k < num_units; k++) {
  939. struct vmw_display_unit *unit = units[k];
  940. int clip_x1 = destX - unit->crtc.x;
  941. int clip_y1 = destY - unit->crtc.y;
  942. int clip_x2 = clip_x1 + surface->sizes[0].width;
  943. int clip_y2 = clip_y1 + surface->sizes[0].height;
  944. /* skip any crtcs that misses the clip region */
  945. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  946. clip_y1 >= unit->crtc.mode.vdisplay ||
  947. clip_x2 <= 0 || clip_y2 <= 0)
  948. continue;
  949. /* need to reset sid as it is changed by execbuf */
  950. cmd->body.srcImage.sid = sid;
  951. cmd->body.destScreenId = unit->unit;
  952. /*
  953. * The blit command is a lot more resilient then the
  954. * readback command when it comes to clip rects. So its
  955. * okay to go out of bounds.
  956. */
  957. cmd->body.destRect.left = clip_x1;
  958. cmd->body.destRect.right = clip_x2;
  959. cmd->body.destRect.top = clip_y1;
  960. cmd->body.destRect.bottom = clip_y2;
  961. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  962. fifo_size, 0, NULL);
  963. if (unlikely(ret != 0))
  964. break;
  965. }
  966. kfree(cmd);
  967. return ret;
  968. }
  969. int vmw_kms_readback(struct vmw_private *dev_priv,
  970. struct drm_file *file_priv,
  971. struct vmw_framebuffer *vfb,
  972. struct drm_vmw_fence_rep __user *user_fence_rep,
  973. struct drm_vmw_rect *clips,
  974. uint32_t num_clips)
  975. {
  976. struct vmw_framebuffer_dmabuf *vfbd =
  977. vmw_framebuffer_to_vfbd(&vfb->base);
  978. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  979. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  980. struct drm_crtc *crtc;
  981. size_t fifo_size;
  982. int i, k, ret, num_units, blits_pos;
  983. struct {
  984. uint32_t header;
  985. SVGAFifoCmdDefineGMRFB body;
  986. } *cmd;
  987. struct {
  988. uint32_t header;
  989. SVGAFifoCmdBlitScreenToGMRFB body;
  990. } *blits;
  991. num_units = 0;
  992. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  993. if (crtc->fb != &vfb->base)
  994. continue;
  995. units[num_units++] = vmw_crtc_to_du(crtc);
  996. }
  997. BUG_ON(dmabuf == NULL);
  998. BUG_ON(!clips || !num_clips);
  999. /* take a safe guess at fifo size */
  1000. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1001. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1002. if (unlikely(cmd == NULL)) {
  1003. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1004. return -ENOMEM;
  1005. }
  1006. memset(cmd, 0, fifo_size);
  1007. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1008. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1009. cmd->body.format.colorDepth = vfb->base.depth;
  1010. cmd->body.format.reserved = 0;
  1011. cmd->body.bytesPerLine = vfb->base.pitch;
  1012. cmd->body.ptr.gmrId = vfb->user_handle;
  1013. cmd->body.ptr.offset = 0;
  1014. blits = (void *)&cmd[1];
  1015. blits_pos = 0;
  1016. for (i = 0; i < num_units; i++) {
  1017. struct drm_vmw_rect *c = clips;
  1018. for (k = 0; k < num_clips; k++, c++) {
  1019. /* transform clip coords to crtc origin based coords */
  1020. int clip_x1 = c->x - units[i]->crtc.x;
  1021. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1022. int clip_y1 = c->y - units[i]->crtc.y;
  1023. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1024. int dest_x = c->x;
  1025. int dest_y = c->y;
  1026. /* compensate for clipping, we negate
  1027. * a negative number and add that.
  1028. */
  1029. if (clip_x1 < 0)
  1030. dest_x += -clip_x1;
  1031. if (clip_y1 < 0)
  1032. dest_y += -clip_y1;
  1033. /* clip */
  1034. clip_x1 = max(clip_x1, 0);
  1035. clip_y1 = max(clip_y1, 0);
  1036. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1037. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1038. /* and cull any rects that misses the crtc */
  1039. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1040. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1041. clip_x2 <= 0 || clip_y2 <= 0)
  1042. continue;
  1043. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1044. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1045. blits[blits_pos].body.destOrigin.x = dest_x;
  1046. blits[blits_pos].body.destOrigin.y = dest_y;
  1047. blits[blits_pos].body.srcRect.left = clip_x1;
  1048. blits[blits_pos].body.srcRect.top = clip_y1;
  1049. blits[blits_pos].body.srcRect.right = clip_x2;
  1050. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1051. blits_pos++;
  1052. }
  1053. }
  1054. /* reset size here and use calculated exact size from loops */
  1055. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1056. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1057. 0, user_fence_rep);
  1058. kfree(cmd);
  1059. return ret;
  1060. }
  1061. int vmw_kms_init(struct vmw_private *dev_priv)
  1062. {
  1063. struct drm_device *dev = dev_priv->dev;
  1064. int ret;
  1065. drm_mode_config_init(dev);
  1066. dev->mode_config.funcs = &vmw_kms_funcs;
  1067. dev->mode_config.min_width = 1;
  1068. dev->mode_config.min_height = 1;
  1069. /* assumed largest fb size */
  1070. dev->mode_config.max_width = 8192;
  1071. dev->mode_config.max_height = 8192;
  1072. ret = vmw_kms_init_screen_object_display(dev_priv);
  1073. if (ret) /* Fallback */
  1074. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1075. return 0;
  1076. }
  1077. int vmw_kms_close(struct vmw_private *dev_priv)
  1078. {
  1079. /*
  1080. * Docs says we should take the lock before calling this function
  1081. * but since it destroys encoders and our destructor calls
  1082. * drm_encoder_cleanup which takes the lock we deadlock.
  1083. */
  1084. drm_mode_config_cleanup(dev_priv->dev);
  1085. vmw_kms_close_legacy_display_system(dev_priv);
  1086. return 0;
  1087. }
  1088. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1089. struct drm_file *file_priv)
  1090. {
  1091. struct drm_vmw_cursor_bypass_arg *arg = data;
  1092. struct vmw_display_unit *du;
  1093. struct drm_mode_object *obj;
  1094. struct drm_crtc *crtc;
  1095. int ret = 0;
  1096. mutex_lock(&dev->mode_config.mutex);
  1097. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1098. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1099. du = vmw_crtc_to_du(crtc);
  1100. du->hotspot_x = arg->xhot;
  1101. du->hotspot_y = arg->yhot;
  1102. }
  1103. mutex_unlock(&dev->mode_config.mutex);
  1104. return 0;
  1105. }
  1106. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1107. if (!obj) {
  1108. ret = -EINVAL;
  1109. goto out;
  1110. }
  1111. crtc = obj_to_crtc(obj);
  1112. du = vmw_crtc_to_du(crtc);
  1113. du->hotspot_x = arg->xhot;
  1114. du->hotspot_y = arg->yhot;
  1115. out:
  1116. mutex_unlock(&dev->mode_config.mutex);
  1117. return ret;
  1118. }
  1119. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1120. unsigned width, unsigned height, unsigned pitch,
  1121. unsigned bpp, unsigned depth)
  1122. {
  1123. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1124. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1125. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1126. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1127. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1128. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1129. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1130. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1131. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1132. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1133. return -EINVAL;
  1134. }
  1135. return 0;
  1136. }
  1137. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1138. {
  1139. struct vmw_vga_topology_state *save;
  1140. uint32_t i;
  1141. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1142. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1143. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1144. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1145. vmw_priv->vga_pitchlock =
  1146. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1147. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1148. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1149. SVGA_FIFO_PITCHLOCK);
  1150. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1151. return 0;
  1152. vmw_priv->num_displays = vmw_read(vmw_priv,
  1153. SVGA_REG_NUM_GUEST_DISPLAYS);
  1154. if (vmw_priv->num_displays == 0)
  1155. vmw_priv->num_displays = 1;
  1156. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1157. save = &vmw_priv->vga_save[i];
  1158. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1159. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1160. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1161. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1162. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1163. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1164. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1165. if (i == 0 && vmw_priv->num_displays == 1 &&
  1166. save->width == 0 && save->height == 0) {
  1167. /*
  1168. * It should be fairly safe to assume that these
  1169. * values are uninitialized.
  1170. */
  1171. save->width = vmw_priv->vga_width - save->pos_x;
  1172. save->height = vmw_priv->vga_height - save->pos_y;
  1173. }
  1174. }
  1175. return 0;
  1176. }
  1177. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1178. {
  1179. struct vmw_vga_topology_state *save;
  1180. uint32_t i;
  1181. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1182. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1183. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1184. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1185. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1186. vmw_priv->vga_pitchlock);
  1187. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1188. iowrite32(vmw_priv->vga_pitchlock,
  1189. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1190. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1191. return 0;
  1192. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1193. save = &vmw_priv->vga_save[i];
  1194. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1195. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1196. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1197. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1198. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1199. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1200. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1201. }
  1202. return 0;
  1203. }
  1204. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1205. uint32_t pitch,
  1206. uint32_t height)
  1207. {
  1208. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1209. }
  1210. /**
  1211. * Function called by DRM code called with vbl_lock held.
  1212. */
  1213. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1214. {
  1215. return 0;
  1216. }
  1217. /**
  1218. * Function called by DRM code called with vbl_lock held.
  1219. */
  1220. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1221. {
  1222. return -ENOSYS;
  1223. }
  1224. /**
  1225. * Function called by DRM code called with vbl_lock held.
  1226. */
  1227. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1228. {
  1229. }
  1230. /*
  1231. * Small shared kms functions.
  1232. */
  1233. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1234. struct drm_vmw_rect *rects)
  1235. {
  1236. struct drm_device *dev = dev_priv->dev;
  1237. struct vmw_display_unit *du;
  1238. struct drm_connector *con;
  1239. mutex_lock(&dev->mode_config.mutex);
  1240. #if 0
  1241. {
  1242. unsigned int i;
  1243. DRM_INFO("%s: new layout ", __func__);
  1244. for (i = 0; i < num; i++)
  1245. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1246. rects[i].w, rects[i].h);
  1247. DRM_INFO("\n");
  1248. }
  1249. #endif
  1250. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1251. du = vmw_connector_to_du(con);
  1252. if (num > du->unit) {
  1253. du->pref_width = rects[du->unit].w;
  1254. du->pref_height = rects[du->unit].h;
  1255. du->pref_active = true;
  1256. du->gui_x = rects[du->unit].x;
  1257. du->gui_y = rects[du->unit].y;
  1258. } else {
  1259. du->pref_width = 800;
  1260. du->pref_height = 600;
  1261. du->pref_active = false;
  1262. }
  1263. con->status = vmw_du_connector_detect(con, true);
  1264. }
  1265. mutex_unlock(&dev->mode_config.mutex);
  1266. return 0;
  1267. }
  1268. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1269. {
  1270. }
  1271. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1272. {
  1273. }
  1274. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1275. u16 *r, u16 *g, u16 *b,
  1276. uint32_t start, uint32_t size)
  1277. {
  1278. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1279. int i;
  1280. for (i = 0; i < size; i++) {
  1281. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1282. r[i], g[i], b[i]);
  1283. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1284. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1285. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1286. }
  1287. }
  1288. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1289. {
  1290. }
  1291. void vmw_du_connector_save(struct drm_connector *connector)
  1292. {
  1293. }
  1294. void vmw_du_connector_restore(struct drm_connector *connector)
  1295. {
  1296. }
  1297. enum drm_connector_status
  1298. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1299. {
  1300. uint32_t num_displays;
  1301. struct drm_device *dev = connector->dev;
  1302. struct vmw_private *dev_priv = vmw_priv(dev);
  1303. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1304. mutex_lock(&dev_priv->hw_mutex);
  1305. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1306. mutex_unlock(&dev_priv->hw_mutex);
  1307. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1308. du->pref_active) ?
  1309. connector_status_connected : connector_status_disconnected);
  1310. }
  1311. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1312. /* 640x480@60Hz */
  1313. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1314. 752, 800, 0, 480, 489, 492, 525, 0,
  1315. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1316. /* 800x600@60Hz */
  1317. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1318. 968, 1056, 0, 600, 601, 605, 628, 0,
  1319. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1320. /* 1024x768@60Hz */
  1321. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1322. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1323. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1324. /* 1152x864@75Hz */
  1325. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1326. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1327. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1328. /* 1280x768@60Hz */
  1329. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1330. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1331. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1332. /* 1280x800@60Hz */
  1333. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1334. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1335. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1336. /* 1280x960@60Hz */
  1337. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1338. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1339. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1340. /* 1280x1024@60Hz */
  1341. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1342. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1343. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1344. /* 1360x768@60Hz */
  1345. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1346. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1347. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1348. /* 1440x1050@60Hz */
  1349. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1350. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1351. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1352. /* 1440x900@60Hz */
  1353. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1354. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1355. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1356. /* 1600x1200@60Hz */
  1357. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1358. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1360. /* 1680x1050@60Hz */
  1361. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1362. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1363. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1364. /* 1792x1344@60Hz */
  1365. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1366. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1367. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1368. /* 1853x1392@60Hz */
  1369. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1370. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1371. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1372. /* 1920x1200@60Hz */
  1373. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1374. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1375. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1376. /* 1920x1440@60Hz */
  1377. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1378. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1379. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1380. /* 2560x1600@60Hz */
  1381. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1382. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1383. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1384. /* Terminate */
  1385. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1386. };
  1387. /**
  1388. * vmw_guess_mode_timing - Provide fake timings for a
  1389. * 60Hz vrefresh mode.
  1390. *
  1391. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1392. * members filled in.
  1393. */
  1394. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1395. {
  1396. mode->hsync_start = mode->hdisplay + 50;
  1397. mode->hsync_end = mode->hsync_start + 50;
  1398. mode->htotal = mode->hsync_end + 50;
  1399. mode->vsync_start = mode->vdisplay + 50;
  1400. mode->vsync_end = mode->vsync_start + 50;
  1401. mode->vtotal = mode->vsync_end + 50;
  1402. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1403. mode->vrefresh = drm_mode_vrefresh(mode);
  1404. }
  1405. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1406. uint32_t max_width, uint32_t max_height)
  1407. {
  1408. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1409. struct drm_device *dev = connector->dev;
  1410. struct vmw_private *dev_priv = vmw_priv(dev);
  1411. struct drm_display_mode *mode = NULL;
  1412. struct drm_display_mode *bmode;
  1413. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1414. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1415. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1416. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1417. };
  1418. int i;
  1419. /* Add preferred mode */
  1420. {
  1421. mode = drm_mode_duplicate(dev, &prefmode);
  1422. if (!mode)
  1423. return 0;
  1424. mode->hdisplay = du->pref_width;
  1425. mode->vdisplay = du->pref_height;
  1426. vmw_guess_mode_timing(mode);
  1427. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1428. mode->vdisplay)) {
  1429. drm_mode_probed_add(connector, mode);
  1430. if (du->pref_mode) {
  1431. list_del_init(&du->pref_mode->head);
  1432. drm_mode_destroy(dev, du->pref_mode);
  1433. }
  1434. du->pref_mode = mode;
  1435. }
  1436. }
  1437. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1438. bmode = &vmw_kms_connector_builtin[i];
  1439. if (bmode->hdisplay > max_width ||
  1440. bmode->vdisplay > max_height)
  1441. continue;
  1442. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1443. bmode->vdisplay))
  1444. continue;
  1445. mode = drm_mode_duplicate(dev, bmode);
  1446. if (!mode)
  1447. return 0;
  1448. mode->vrefresh = drm_mode_vrefresh(mode);
  1449. drm_mode_probed_add(connector, mode);
  1450. }
  1451. drm_mode_connector_list_update(connector);
  1452. return 1;
  1453. }
  1454. int vmw_du_connector_set_property(struct drm_connector *connector,
  1455. struct drm_property *property,
  1456. uint64_t val)
  1457. {
  1458. return 0;
  1459. }
  1460. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1461. struct drm_file *file_priv)
  1462. {
  1463. struct vmw_private *dev_priv = vmw_priv(dev);
  1464. struct drm_vmw_update_layout_arg *arg =
  1465. (struct drm_vmw_update_layout_arg *)data;
  1466. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1467. void __user *user_rects;
  1468. struct drm_vmw_rect *rects;
  1469. unsigned rects_size;
  1470. int ret;
  1471. int i;
  1472. struct drm_mode_config *mode_config = &dev->mode_config;
  1473. ret = ttm_read_lock(&vmaster->lock, true);
  1474. if (unlikely(ret != 0))
  1475. return ret;
  1476. if (!arg->num_outputs) {
  1477. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1478. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1479. goto out_unlock;
  1480. }
  1481. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1482. rects = kzalloc(rects_size, GFP_KERNEL);
  1483. if (unlikely(!rects)) {
  1484. ret = -ENOMEM;
  1485. goto out_unlock;
  1486. }
  1487. user_rects = (void __user *)(unsigned long)arg->rects;
  1488. ret = copy_from_user(rects, user_rects, rects_size);
  1489. if (unlikely(ret != 0)) {
  1490. DRM_ERROR("Failed to get rects.\n");
  1491. ret = -EFAULT;
  1492. goto out_free;
  1493. }
  1494. for (i = 0; i < arg->num_outputs; ++i) {
  1495. if (rects->x < 0 ||
  1496. rects->y < 0 ||
  1497. rects->x + rects->w > mode_config->max_width ||
  1498. rects->y + rects->h > mode_config->max_height) {
  1499. DRM_ERROR("Invalid GUI layout.\n");
  1500. ret = -EINVAL;
  1501. goto out_free;
  1502. }
  1503. }
  1504. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1505. out_free:
  1506. kfree(rects);
  1507. out_unlock:
  1508. ttm_read_unlock(&vmaster->lock);
  1509. return ret;
  1510. }