sdhci.c 34 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.11"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static const struct pci_device_id pci_ids[] __devinitdata = {
  24. /* handle any SD host controller */
  25. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  26. { /* end: all zeroes */ },
  27. };
  28. MODULE_DEVICE_TABLE(pci, pci_ids);
  29. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  30. static void sdhci_finish_data(struct sdhci_host *);
  31. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  32. static void sdhci_finish_command(struct sdhci_host *);
  33. static void sdhci_dumpregs(struct sdhci_host *host)
  34. {
  35. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  36. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  37. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  38. readw(host->ioaddr + SDHCI_HOST_VERSION));
  39. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  40. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  41. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  42. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  43. readl(host->ioaddr + SDHCI_ARGUMENT),
  44. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  45. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  46. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  47. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  48. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  49. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  50. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  51. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  52. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  53. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  54. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  55. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  56. readl(host->ioaddr + SDHCI_INT_STATUS));
  57. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  58. readl(host->ioaddr + SDHCI_INT_ENABLE),
  59. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  60. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  61. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  62. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  63. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  64. readl(host->ioaddr + SDHCI_CAPABILITIES),
  65. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  66. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  67. }
  68. /*****************************************************************************\
  69. * *
  70. * Low level functions *
  71. * *
  72. \*****************************************************************************/
  73. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  74. {
  75. unsigned long timeout;
  76. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  77. if (mask & SDHCI_RESET_ALL)
  78. host->clock = 0;
  79. /* Wait max 100 ms */
  80. timeout = 100;
  81. /* hw clears the bit when it's done */
  82. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  83. if (timeout == 0) {
  84. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  85. "Please report this to " BUGMAIL ".\n",
  86. mmc_hostname(host->mmc), (int)mask);
  87. sdhci_dumpregs(host);
  88. return;
  89. }
  90. timeout--;
  91. mdelay(1);
  92. }
  93. }
  94. static void sdhci_init(struct sdhci_host *host)
  95. {
  96. u32 intmask;
  97. sdhci_reset(host, SDHCI_RESET_ALL);
  98. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  99. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  100. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  101. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  102. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  103. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. }
  107. static void sdhci_activate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl |= SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. static void sdhci_deactivate_led(struct sdhci_host *host)
  115. {
  116. u8 ctrl;
  117. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  118. ctrl &= ~SDHCI_CTRL_LED;
  119. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  120. }
  121. /*****************************************************************************\
  122. * *
  123. * Core functions *
  124. * *
  125. \*****************************************************************************/
  126. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  127. {
  128. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  129. return host->mapped_sg + host->cur_sg->offset;
  130. }
  131. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  132. {
  133. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  134. }
  135. static inline int sdhci_next_sg(struct sdhci_host* host)
  136. {
  137. /*
  138. * Skip to next SG entry.
  139. */
  140. host->cur_sg++;
  141. host->num_sg--;
  142. /*
  143. * Any entries left?
  144. */
  145. if (host->num_sg > 0) {
  146. host->offset = 0;
  147. host->remain = host->cur_sg->length;
  148. }
  149. return host->num_sg;
  150. }
  151. static void sdhci_read_block_pio(struct sdhci_host *host)
  152. {
  153. int blksize, chunk_remain;
  154. u32 data;
  155. char *buffer;
  156. int size;
  157. DBG("PIO reading\n");
  158. blksize = host->data->blksz;
  159. chunk_remain = 0;
  160. data = 0;
  161. buffer = sdhci_kmap_sg(host) + host->offset;
  162. while (blksize) {
  163. if (chunk_remain == 0) {
  164. data = readl(host->ioaddr + SDHCI_BUFFER);
  165. chunk_remain = min(blksize, 4);
  166. }
  167. size = min(host->size, host->remain);
  168. size = min(size, chunk_remain);
  169. chunk_remain -= size;
  170. blksize -= size;
  171. host->offset += size;
  172. host->remain -= size;
  173. host->size -= size;
  174. while (size) {
  175. *buffer = data & 0xFF;
  176. buffer++;
  177. data >>= 8;
  178. size--;
  179. }
  180. if (host->remain == 0) {
  181. sdhci_kunmap_sg(host);
  182. if (sdhci_next_sg(host) == 0) {
  183. BUG_ON(blksize != 0);
  184. return;
  185. }
  186. buffer = sdhci_kmap_sg(host);
  187. }
  188. }
  189. sdhci_kunmap_sg(host);
  190. }
  191. static void sdhci_write_block_pio(struct sdhci_host *host)
  192. {
  193. int blksize, chunk_remain;
  194. u32 data;
  195. char *buffer;
  196. int bytes, size;
  197. DBG("PIO writing\n");
  198. blksize = host->data->blksz;
  199. chunk_remain = 4;
  200. data = 0;
  201. bytes = 0;
  202. buffer = sdhci_kmap_sg(host) + host->offset;
  203. while (blksize) {
  204. size = min(host->size, host->remain);
  205. size = min(size, chunk_remain);
  206. chunk_remain -= size;
  207. blksize -= size;
  208. host->offset += size;
  209. host->remain -= size;
  210. host->size -= size;
  211. while (size) {
  212. data >>= 8;
  213. data |= (u32)*buffer << 24;
  214. buffer++;
  215. size--;
  216. }
  217. if (chunk_remain == 0) {
  218. writel(data, host->ioaddr + SDHCI_BUFFER);
  219. chunk_remain = min(blksize, 4);
  220. }
  221. if (host->remain == 0) {
  222. sdhci_kunmap_sg(host);
  223. if (sdhci_next_sg(host) == 0) {
  224. BUG_ON(blksize != 0);
  225. return;
  226. }
  227. buffer = sdhci_kmap_sg(host);
  228. }
  229. }
  230. sdhci_kunmap_sg(host);
  231. }
  232. static void sdhci_transfer_pio(struct sdhci_host *host)
  233. {
  234. u32 mask;
  235. BUG_ON(!host->data);
  236. if (host->size == 0)
  237. return;
  238. if (host->data->flags & MMC_DATA_READ)
  239. mask = SDHCI_DATA_AVAILABLE;
  240. else
  241. mask = SDHCI_SPACE_AVAILABLE;
  242. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  243. if (host->data->flags & MMC_DATA_READ)
  244. sdhci_read_block_pio(host);
  245. else
  246. sdhci_write_block_pio(host);
  247. if (host->size == 0)
  248. break;
  249. BUG_ON(host->num_sg == 0);
  250. }
  251. DBG("PIO transfer complete.\n");
  252. }
  253. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  254. {
  255. u8 count;
  256. unsigned target_timeout, current_timeout;
  257. WARN_ON(host->data);
  258. if (data == NULL)
  259. return;
  260. DBG("blksz %04x blks %04x flags %08x\n",
  261. data->blksz, data->blocks, data->flags);
  262. DBG("tsac %d ms nsac %d clk\n",
  263. data->timeout_ns / 1000000, data->timeout_clks);
  264. /* Sanity checks */
  265. BUG_ON(data->blksz * data->blocks > 524288);
  266. BUG_ON(data->blksz > host->max_block);
  267. BUG_ON(data->blocks > 65535);
  268. /* timeout in us */
  269. target_timeout = data->timeout_ns / 1000 +
  270. data->timeout_clks / host->clock;
  271. /*
  272. * Figure out needed cycles.
  273. * We do this in steps in order to fit inside a 32 bit int.
  274. * The first step is the minimum timeout, which will have a
  275. * minimum resolution of 6 bits:
  276. * (1) 2^13*1000 > 2^22,
  277. * (2) host->timeout_clk < 2^16
  278. * =>
  279. * (1) / (2) > 2^6
  280. */
  281. count = 0;
  282. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  283. while (current_timeout < target_timeout) {
  284. count++;
  285. current_timeout <<= 1;
  286. if (count >= 0xF)
  287. break;
  288. }
  289. if (count >= 0xF) {
  290. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  291. mmc_hostname(host->mmc));
  292. count = 0xE;
  293. }
  294. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  295. if (host->flags & SDHCI_USE_DMA) {
  296. int count;
  297. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  298. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  299. BUG_ON(count != 1);
  300. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  301. } else {
  302. host->size = data->blksz * data->blocks;
  303. host->cur_sg = data->sg;
  304. host->num_sg = data->sg_len;
  305. host->offset = 0;
  306. host->remain = host->cur_sg->length;
  307. }
  308. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  309. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  310. host->ioaddr + SDHCI_BLOCK_SIZE);
  311. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  312. }
  313. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  314. struct mmc_data *data)
  315. {
  316. u16 mode;
  317. WARN_ON(host->data);
  318. if (data == NULL)
  319. return;
  320. mode = SDHCI_TRNS_BLK_CNT_EN;
  321. if (data->blocks > 1)
  322. mode |= SDHCI_TRNS_MULTI;
  323. if (data->flags & MMC_DATA_READ)
  324. mode |= SDHCI_TRNS_READ;
  325. if (host->flags & SDHCI_USE_DMA)
  326. mode |= SDHCI_TRNS_DMA;
  327. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  328. }
  329. static void sdhci_finish_data(struct sdhci_host *host)
  330. {
  331. struct mmc_data *data;
  332. u16 blocks;
  333. BUG_ON(!host->data);
  334. data = host->data;
  335. host->data = NULL;
  336. if (host->flags & SDHCI_USE_DMA) {
  337. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  338. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  339. }
  340. /*
  341. * Controller doesn't count down when in single block mode.
  342. */
  343. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  344. blocks = 0;
  345. else
  346. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  347. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  348. if ((data->error == MMC_ERR_NONE) && blocks) {
  349. printk(KERN_ERR "%s: Controller signalled completion even "
  350. "though there were blocks left. Please report this "
  351. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  352. data->error = MMC_ERR_FAILED;
  353. }
  354. if (host->size != 0) {
  355. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  356. "Please report this to " BUGMAIL ".\n",
  357. mmc_hostname(host->mmc), host->size);
  358. data->error = MMC_ERR_FAILED;
  359. }
  360. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  361. if (data->stop) {
  362. /*
  363. * The controller needs a reset of internal state machines
  364. * upon error conditions.
  365. */
  366. if (data->error != MMC_ERR_NONE) {
  367. sdhci_reset(host, SDHCI_RESET_CMD);
  368. sdhci_reset(host, SDHCI_RESET_DATA);
  369. }
  370. sdhci_send_command(host, data->stop);
  371. } else
  372. tasklet_schedule(&host->finish_tasklet);
  373. }
  374. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  375. {
  376. int flags;
  377. u32 mask;
  378. unsigned long timeout;
  379. WARN_ON(host->cmd);
  380. DBG("Sending cmd (%x)\n", cmd->opcode);
  381. /* Wait max 10 ms */
  382. timeout = 10;
  383. mask = SDHCI_CMD_INHIBIT;
  384. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  385. mask |= SDHCI_DATA_INHIBIT;
  386. /* We shouldn't wait for data inihibit for stop commands, even
  387. though they might use busy signaling */
  388. if (host->mrq->data && (cmd == host->mrq->data->stop))
  389. mask &= ~SDHCI_DATA_INHIBIT;
  390. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  391. if (timeout == 0) {
  392. printk(KERN_ERR "%s: Controller never released "
  393. "inhibit bit(s). Please report this to "
  394. BUGMAIL ".\n", mmc_hostname(host->mmc));
  395. sdhci_dumpregs(host);
  396. cmd->error = MMC_ERR_FAILED;
  397. tasklet_schedule(&host->finish_tasklet);
  398. return;
  399. }
  400. timeout--;
  401. mdelay(1);
  402. }
  403. mod_timer(&host->timer, jiffies + 10 * HZ);
  404. host->cmd = cmd;
  405. sdhci_prepare_data(host, cmd->data);
  406. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  407. sdhci_set_transfer_mode(host, cmd->data);
  408. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  409. printk(KERN_ERR "%s: Unsupported response type! "
  410. "Please report this to " BUGMAIL ".\n",
  411. mmc_hostname(host->mmc));
  412. cmd->error = MMC_ERR_INVALID;
  413. tasklet_schedule(&host->finish_tasklet);
  414. return;
  415. }
  416. if (!(cmd->flags & MMC_RSP_PRESENT))
  417. flags = SDHCI_CMD_RESP_NONE;
  418. else if (cmd->flags & MMC_RSP_136)
  419. flags = SDHCI_CMD_RESP_LONG;
  420. else if (cmd->flags & MMC_RSP_BUSY)
  421. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  422. else
  423. flags = SDHCI_CMD_RESP_SHORT;
  424. if (cmd->flags & MMC_RSP_CRC)
  425. flags |= SDHCI_CMD_CRC;
  426. if (cmd->flags & MMC_RSP_OPCODE)
  427. flags |= SDHCI_CMD_INDEX;
  428. if (cmd->data)
  429. flags |= SDHCI_CMD_DATA;
  430. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  431. host->ioaddr + SDHCI_COMMAND);
  432. }
  433. static void sdhci_finish_command(struct sdhci_host *host)
  434. {
  435. int i;
  436. BUG_ON(host->cmd == NULL);
  437. if (host->cmd->flags & MMC_RSP_PRESENT) {
  438. if (host->cmd->flags & MMC_RSP_136) {
  439. /* CRC is stripped so we need to do some shifting. */
  440. for (i = 0;i < 4;i++) {
  441. host->cmd->resp[i] = readl(host->ioaddr +
  442. SDHCI_RESPONSE + (3-i)*4) << 8;
  443. if (i != 3)
  444. host->cmd->resp[i] |=
  445. readb(host->ioaddr +
  446. SDHCI_RESPONSE + (3-i)*4-1);
  447. }
  448. } else {
  449. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  450. }
  451. }
  452. host->cmd->error = MMC_ERR_NONE;
  453. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  454. if (host->cmd->data)
  455. host->data = host->cmd->data;
  456. else
  457. tasklet_schedule(&host->finish_tasklet);
  458. host->cmd = NULL;
  459. }
  460. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  461. {
  462. int div;
  463. u16 clk;
  464. unsigned long timeout;
  465. if (clock == host->clock)
  466. return;
  467. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  468. if (clock == 0)
  469. goto out;
  470. for (div = 1;div < 256;div *= 2) {
  471. if ((host->max_clk / div) <= clock)
  472. break;
  473. }
  474. div >>= 1;
  475. clk = div << SDHCI_DIVIDER_SHIFT;
  476. clk |= SDHCI_CLOCK_INT_EN;
  477. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  478. /* Wait max 10 ms */
  479. timeout = 10;
  480. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  481. & SDHCI_CLOCK_INT_STABLE)) {
  482. if (timeout == 0) {
  483. printk(KERN_ERR "%s: Internal clock never stabilised. "
  484. "Please report this to " BUGMAIL ".\n",
  485. mmc_hostname(host->mmc));
  486. sdhci_dumpregs(host);
  487. return;
  488. }
  489. timeout--;
  490. mdelay(1);
  491. }
  492. clk |= SDHCI_CLOCK_CARD_EN;
  493. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  494. out:
  495. host->clock = clock;
  496. }
  497. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  498. {
  499. u8 pwr;
  500. if (host->power == power)
  501. return;
  502. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  503. if (power == (unsigned short)-1)
  504. goto out;
  505. pwr = SDHCI_POWER_ON;
  506. switch (power) {
  507. case MMC_VDD_170:
  508. case MMC_VDD_180:
  509. case MMC_VDD_190:
  510. pwr |= SDHCI_POWER_180;
  511. break;
  512. case MMC_VDD_290:
  513. case MMC_VDD_300:
  514. case MMC_VDD_310:
  515. pwr |= SDHCI_POWER_300;
  516. break;
  517. case MMC_VDD_320:
  518. case MMC_VDD_330:
  519. case MMC_VDD_340:
  520. pwr |= SDHCI_POWER_330;
  521. break;
  522. default:
  523. BUG();
  524. }
  525. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  526. out:
  527. host->power = power;
  528. }
  529. /*****************************************************************************\
  530. * *
  531. * MMC callbacks *
  532. * *
  533. \*****************************************************************************/
  534. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  535. {
  536. struct sdhci_host *host;
  537. unsigned long flags;
  538. host = mmc_priv(mmc);
  539. spin_lock_irqsave(&host->lock, flags);
  540. WARN_ON(host->mrq != NULL);
  541. sdhci_activate_led(host);
  542. host->mrq = mrq;
  543. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  544. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  545. tasklet_schedule(&host->finish_tasklet);
  546. } else
  547. sdhci_send_command(host, mrq->cmd);
  548. spin_unlock_irqrestore(&host->lock, flags);
  549. }
  550. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  551. {
  552. struct sdhci_host *host;
  553. unsigned long flags;
  554. u8 ctrl;
  555. host = mmc_priv(mmc);
  556. spin_lock_irqsave(&host->lock, flags);
  557. /*
  558. * Reset the chip on each power off.
  559. * Should clear out any weird states.
  560. */
  561. if (ios->power_mode == MMC_POWER_OFF) {
  562. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  563. sdhci_init(host);
  564. }
  565. sdhci_set_clock(host, ios->clock);
  566. if (ios->power_mode == MMC_POWER_OFF)
  567. sdhci_set_power(host, -1);
  568. else
  569. sdhci_set_power(host, ios->vdd);
  570. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  571. if (ios->bus_width == MMC_BUS_WIDTH_4)
  572. ctrl |= SDHCI_CTRL_4BITBUS;
  573. else
  574. ctrl &= ~SDHCI_CTRL_4BITBUS;
  575. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  576. spin_unlock_irqrestore(&host->lock, flags);
  577. }
  578. static int sdhci_get_ro(struct mmc_host *mmc)
  579. {
  580. struct sdhci_host *host;
  581. unsigned long flags;
  582. int present;
  583. host = mmc_priv(mmc);
  584. spin_lock_irqsave(&host->lock, flags);
  585. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  586. spin_unlock_irqrestore(&host->lock, flags);
  587. return !(present & SDHCI_WRITE_PROTECT);
  588. }
  589. static struct mmc_host_ops sdhci_ops = {
  590. .request = sdhci_request,
  591. .set_ios = sdhci_set_ios,
  592. .get_ro = sdhci_get_ro,
  593. };
  594. /*****************************************************************************\
  595. * *
  596. * Tasklets *
  597. * *
  598. \*****************************************************************************/
  599. static void sdhci_tasklet_card(unsigned long param)
  600. {
  601. struct sdhci_host *host;
  602. unsigned long flags;
  603. host = (struct sdhci_host*)param;
  604. spin_lock_irqsave(&host->lock, flags);
  605. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  606. if (host->mrq) {
  607. printk(KERN_ERR "%s: Card removed during transfer!\n",
  608. mmc_hostname(host->mmc));
  609. printk(KERN_ERR "%s: Resetting controller.\n",
  610. mmc_hostname(host->mmc));
  611. sdhci_reset(host, SDHCI_RESET_CMD);
  612. sdhci_reset(host, SDHCI_RESET_DATA);
  613. host->mrq->cmd->error = MMC_ERR_FAILED;
  614. tasklet_schedule(&host->finish_tasklet);
  615. }
  616. }
  617. spin_unlock_irqrestore(&host->lock, flags);
  618. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  619. }
  620. static void sdhci_tasklet_finish(unsigned long param)
  621. {
  622. struct sdhci_host *host;
  623. unsigned long flags;
  624. struct mmc_request *mrq;
  625. host = (struct sdhci_host*)param;
  626. spin_lock_irqsave(&host->lock, flags);
  627. del_timer(&host->timer);
  628. mrq = host->mrq;
  629. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  630. /*
  631. * The controller needs a reset of internal state machines
  632. * upon error conditions.
  633. */
  634. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  635. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  636. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  637. sdhci_reset(host, SDHCI_RESET_CMD);
  638. sdhci_reset(host, SDHCI_RESET_DATA);
  639. }
  640. host->mrq = NULL;
  641. host->cmd = NULL;
  642. host->data = NULL;
  643. sdhci_deactivate_led(host);
  644. spin_unlock_irqrestore(&host->lock, flags);
  645. mmc_request_done(host->mmc, mrq);
  646. }
  647. static void sdhci_timeout_timer(unsigned long data)
  648. {
  649. struct sdhci_host *host;
  650. unsigned long flags;
  651. host = (struct sdhci_host*)data;
  652. spin_lock_irqsave(&host->lock, flags);
  653. if (host->mrq) {
  654. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  655. "Please report this to " BUGMAIL ".\n",
  656. mmc_hostname(host->mmc));
  657. sdhci_dumpregs(host);
  658. if (host->data) {
  659. host->data->error = MMC_ERR_TIMEOUT;
  660. sdhci_finish_data(host);
  661. } else {
  662. if (host->cmd)
  663. host->cmd->error = MMC_ERR_TIMEOUT;
  664. else
  665. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  666. tasklet_schedule(&host->finish_tasklet);
  667. }
  668. }
  669. spin_unlock_irqrestore(&host->lock, flags);
  670. }
  671. /*****************************************************************************\
  672. * *
  673. * Interrupt handling *
  674. * *
  675. \*****************************************************************************/
  676. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  677. {
  678. BUG_ON(intmask == 0);
  679. if (!host->cmd) {
  680. printk(KERN_ERR "%s: Got command interrupt even though no "
  681. "command operation was in progress.\n",
  682. mmc_hostname(host->mmc));
  683. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  684. mmc_hostname(host->mmc));
  685. sdhci_dumpregs(host);
  686. return;
  687. }
  688. if (intmask & SDHCI_INT_RESPONSE)
  689. sdhci_finish_command(host);
  690. else {
  691. if (intmask & SDHCI_INT_TIMEOUT)
  692. host->cmd->error = MMC_ERR_TIMEOUT;
  693. else if (intmask & SDHCI_INT_CRC)
  694. host->cmd->error = MMC_ERR_BADCRC;
  695. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  696. host->cmd->error = MMC_ERR_FAILED;
  697. else
  698. host->cmd->error = MMC_ERR_INVALID;
  699. tasklet_schedule(&host->finish_tasklet);
  700. }
  701. }
  702. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  703. {
  704. BUG_ON(intmask == 0);
  705. if (!host->data) {
  706. /*
  707. * A data end interrupt is sent together with the response
  708. * for the stop command.
  709. */
  710. if (intmask & SDHCI_INT_DATA_END)
  711. return;
  712. printk(KERN_ERR "%s: Got data interrupt even though no "
  713. "data operation was in progress.\n",
  714. mmc_hostname(host->mmc));
  715. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  716. mmc_hostname(host->mmc));
  717. sdhci_dumpregs(host);
  718. return;
  719. }
  720. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  721. host->data->error = MMC_ERR_TIMEOUT;
  722. else if (intmask & SDHCI_INT_DATA_CRC)
  723. host->data->error = MMC_ERR_BADCRC;
  724. else if (intmask & SDHCI_INT_DATA_END_BIT)
  725. host->data->error = MMC_ERR_FAILED;
  726. if (host->data->error != MMC_ERR_NONE)
  727. sdhci_finish_data(host);
  728. else {
  729. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  730. sdhci_transfer_pio(host);
  731. if (intmask & SDHCI_INT_DATA_END)
  732. sdhci_finish_data(host);
  733. }
  734. }
  735. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  736. {
  737. irqreturn_t result;
  738. struct sdhci_host* host = dev_id;
  739. u32 intmask;
  740. spin_lock(&host->lock);
  741. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  742. if (!intmask) {
  743. result = IRQ_NONE;
  744. goto out;
  745. }
  746. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  747. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  748. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  749. host->ioaddr + SDHCI_INT_STATUS);
  750. tasklet_schedule(&host->card_tasklet);
  751. }
  752. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  753. if (intmask & SDHCI_INT_CMD_MASK) {
  754. writel(intmask & SDHCI_INT_CMD_MASK,
  755. host->ioaddr + SDHCI_INT_STATUS);
  756. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  757. }
  758. if (intmask & SDHCI_INT_DATA_MASK) {
  759. writel(intmask & SDHCI_INT_DATA_MASK,
  760. host->ioaddr + SDHCI_INT_STATUS);
  761. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  762. }
  763. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  764. if (intmask & SDHCI_INT_BUS_POWER) {
  765. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  766. mmc_hostname(host->mmc));
  767. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  768. }
  769. intmask &= SDHCI_INT_BUS_POWER;
  770. if (intmask) {
  771. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  772. "report this to " BUGMAIL ".\n",
  773. mmc_hostname(host->mmc), intmask);
  774. sdhci_dumpregs(host);
  775. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  776. }
  777. result = IRQ_HANDLED;
  778. out:
  779. spin_unlock(&host->lock);
  780. return result;
  781. }
  782. /*****************************************************************************\
  783. * *
  784. * Suspend/resume *
  785. * *
  786. \*****************************************************************************/
  787. #ifdef CONFIG_PM
  788. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  789. {
  790. struct sdhci_chip *chip;
  791. int i, ret;
  792. chip = pci_get_drvdata(pdev);
  793. if (!chip)
  794. return 0;
  795. DBG("Suspending...\n");
  796. for (i = 0;i < chip->num_slots;i++) {
  797. if (!chip->hosts[i])
  798. continue;
  799. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  800. if (ret) {
  801. for (i--;i >= 0;i--)
  802. mmc_resume_host(chip->hosts[i]->mmc);
  803. return ret;
  804. }
  805. }
  806. pci_save_state(pdev);
  807. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  808. pci_disable_device(pdev);
  809. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  810. return 0;
  811. }
  812. static int sdhci_resume (struct pci_dev *pdev)
  813. {
  814. struct sdhci_chip *chip;
  815. int i, ret;
  816. chip = pci_get_drvdata(pdev);
  817. if (!chip)
  818. return 0;
  819. DBG("Resuming...\n");
  820. pci_set_power_state(pdev, PCI_D0);
  821. pci_restore_state(pdev);
  822. pci_enable_device(pdev);
  823. for (i = 0;i < chip->num_slots;i++) {
  824. if (!chip->hosts[i])
  825. continue;
  826. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  827. pci_set_master(pdev);
  828. sdhci_init(chip->hosts[i]);
  829. ret = mmc_resume_host(chip->hosts[i]->mmc);
  830. if (ret)
  831. return ret;
  832. }
  833. return 0;
  834. }
  835. #else /* CONFIG_PM */
  836. #define sdhci_suspend NULL
  837. #define sdhci_resume NULL
  838. #endif /* CONFIG_PM */
  839. /*****************************************************************************\
  840. * *
  841. * Device probing/removal *
  842. * *
  843. \*****************************************************************************/
  844. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  845. {
  846. int ret;
  847. unsigned int version;
  848. struct sdhci_chip *chip;
  849. struct mmc_host *mmc;
  850. struct sdhci_host *host;
  851. u8 first_bar;
  852. unsigned int caps;
  853. chip = pci_get_drvdata(pdev);
  854. BUG_ON(!chip);
  855. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  856. if (ret)
  857. return ret;
  858. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  859. if (first_bar > 5) {
  860. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  861. return -ENODEV;
  862. }
  863. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  864. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  865. return -ENODEV;
  866. }
  867. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  868. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  869. return -ENODEV;
  870. }
  871. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  872. if (!mmc)
  873. return -ENOMEM;
  874. host = mmc_priv(mmc);
  875. host->mmc = mmc;
  876. host->bar = first_bar + slot;
  877. host->addr = pci_resource_start(pdev, host->bar);
  878. host->irq = pdev->irq;
  879. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  880. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  881. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  882. if (ret)
  883. goto free;
  884. host->ioaddr = ioremap_nocache(host->addr,
  885. pci_resource_len(pdev, host->bar));
  886. if (!host->ioaddr) {
  887. ret = -ENOMEM;
  888. goto release;
  889. }
  890. sdhci_reset(host, SDHCI_RESET_ALL);
  891. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  892. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  893. if (version != 0) {
  894. printk(KERN_ERR "%s: Unknown controller version (%d). "
  895. "Cowardly refusing to continue.\n", host->slot_descr,
  896. version);
  897. ret = -ENODEV;
  898. goto unmap;
  899. }
  900. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  901. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  902. host->flags |= SDHCI_USE_DMA;
  903. if (host->flags & SDHCI_USE_DMA) {
  904. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  905. printk(KERN_WARNING "%s: No suitable DMA available. "
  906. "Falling back to PIO.\n", host->slot_descr);
  907. host->flags &= ~SDHCI_USE_DMA;
  908. }
  909. }
  910. if (host->flags & SDHCI_USE_DMA)
  911. pci_set_master(pdev);
  912. else /* XXX: Hack to get MMC layer to avoid highmem */
  913. pdev->dma_mask = 0;
  914. host->max_clk =
  915. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  916. if (host->max_clk == 0) {
  917. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  918. "frequency.\n", host->slot_descr);
  919. ret = -ENODEV;
  920. goto unmap;
  921. }
  922. host->max_clk *= 1000000;
  923. host->timeout_clk =
  924. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  925. if (host->timeout_clk == 0) {
  926. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  927. "frequency.\n", host->slot_descr);
  928. ret = -ENODEV;
  929. goto unmap;
  930. }
  931. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  932. host->timeout_clk *= 1000;
  933. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  934. if (host->max_block >= 3) {
  935. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  936. host->slot_descr);
  937. ret = -ENODEV;
  938. goto unmap;
  939. }
  940. host->max_block = 512 << host->max_block;
  941. /*
  942. * Set host parameters.
  943. */
  944. mmc->ops = &sdhci_ops;
  945. mmc->f_min = host->max_clk / 256;
  946. mmc->f_max = host->max_clk;
  947. mmc->caps = MMC_CAP_4_BIT_DATA;
  948. mmc->ocr_avail = 0;
  949. if (caps & SDHCI_CAN_VDD_330)
  950. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  951. else if (caps & SDHCI_CAN_VDD_300)
  952. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  953. else if (caps & SDHCI_CAN_VDD_180)
  954. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  955. if (mmc->ocr_avail == 0) {
  956. printk(KERN_ERR "%s: Hardware doesn't report any "
  957. "support voltages.\n", host->slot_descr);
  958. ret = -ENODEV;
  959. goto unmap;
  960. }
  961. spin_lock_init(&host->lock);
  962. /*
  963. * Maximum number of segments. Hardware cannot do scatter lists.
  964. */
  965. if (host->flags & SDHCI_USE_DMA)
  966. mmc->max_hw_segs = 1;
  967. else
  968. mmc->max_hw_segs = 16;
  969. mmc->max_phys_segs = 16;
  970. /*
  971. * Maximum number of sectors in one transfer. Limited by DMA boundary
  972. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  973. */
  974. mmc->max_sectors = 1024;
  975. /*
  976. * Maximum segment size. Could be one segment with the maximum number
  977. * of sectors.
  978. */
  979. mmc->max_seg_size = mmc->max_sectors * 512;
  980. /*
  981. * Init tasklets.
  982. */
  983. tasklet_init(&host->card_tasklet,
  984. sdhci_tasklet_card, (unsigned long)host);
  985. tasklet_init(&host->finish_tasklet,
  986. sdhci_tasklet_finish, (unsigned long)host);
  987. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  988. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  989. host->slot_descr, host);
  990. if (ret)
  991. goto untasklet;
  992. sdhci_init(host);
  993. #ifdef CONFIG_MMC_DEBUG
  994. sdhci_dumpregs(host);
  995. #endif
  996. host->chip = chip;
  997. chip->hosts[slot] = host;
  998. mmc_add_host(mmc);
  999. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1000. host->addr, host->irq,
  1001. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1002. return 0;
  1003. untasklet:
  1004. tasklet_kill(&host->card_tasklet);
  1005. tasklet_kill(&host->finish_tasklet);
  1006. unmap:
  1007. iounmap(host->ioaddr);
  1008. release:
  1009. pci_release_region(pdev, host->bar);
  1010. free:
  1011. mmc_free_host(mmc);
  1012. return ret;
  1013. }
  1014. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1015. {
  1016. struct sdhci_chip *chip;
  1017. struct mmc_host *mmc;
  1018. struct sdhci_host *host;
  1019. chip = pci_get_drvdata(pdev);
  1020. host = chip->hosts[slot];
  1021. mmc = host->mmc;
  1022. chip->hosts[slot] = NULL;
  1023. mmc_remove_host(mmc);
  1024. sdhci_reset(host, SDHCI_RESET_ALL);
  1025. free_irq(host->irq, host);
  1026. del_timer_sync(&host->timer);
  1027. tasklet_kill(&host->card_tasklet);
  1028. tasklet_kill(&host->finish_tasklet);
  1029. iounmap(host->ioaddr);
  1030. pci_release_region(pdev, host->bar);
  1031. mmc_free_host(mmc);
  1032. }
  1033. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1034. const struct pci_device_id *ent)
  1035. {
  1036. int ret, i;
  1037. u8 slots, rev;
  1038. struct sdhci_chip *chip;
  1039. BUG_ON(pdev == NULL);
  1040. BUG_ON(ent == NULL);
  1041. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1042. printk(KERN_INFO DRIVER_NAME
  1043. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1044. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1045. (int)rev);
  1046. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1047. if (ret)
  1048. return ret;
  1049. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1050. DBG("found %d slot(s)\n", slots);
  1051. if (slots == 0)
  1052. return -ENODEV;
  1053. ret = pci_enable_device(pdev);
  1054. if (ret)
  1055. return ret;
  1056. chip = kzalloc(sizeof(struct sdhci_chip) +
  1057. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1058. if (!chip) {
  1059. ret = -ENOMEM;
  1060. goto err;
  1061. }
  1062. chip->pdev = pdev;
  1063. chip->num_slots = slots;
  1064. pci_set_drvdata(pdev, chip);
  1065. for (i = 0;i < slots;i++) {
  1066. ret = sdhci_probe_slot(pdev, i);
  1067. if (ret) {
  1068. for (i--;i >= 0;i--)
  1069. sdhci_remove_slot(pdev, i);
  1070. goto free;
  1071. }
  1072. }
  1073. return 0;
  1074. free:
  1075. pci_set_drvdata(pdev, NULL);
  1076. kfree(chip);
  1077. err:
  1078. pci_disable_device(pdev);
  1079. return ret;
  1080. }
  1081. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1082. {
  1083. int i;
  1084. struct sdhci_chip *chip;
  1085. chip = pci_get_drvdata(pdev);
  1086. if (chip) {
  1087. for (i = 0;i < chip->num_slots;i++)
  1088. sdhci_remove_slot(pdev, i);
  1089. pci_set_drvdata(pdev, NULL);
  1090. kfree(chip);
  1091. }
  1092. pci_disable_device(pdev);
  1093. }
  1094. static struct pci_driver sdhci_driver = {
  1095. .name = DRIVER_NAME,
  1096. .id_table = pci_ids,
  1097. .probe = sdhci_probe,
  1098. .remove = __devexit_p(sdhci_remove),
  1099. .suspend = sdhci_suspend,
  1100. .resume = sdhci_resume,
  1101. };
  1102. /*****************************************************************************\
  1103. * *
  1104. * Driver init/exit *
  1105. * *
  1106. \*****************************************************************************/
  1107. static int __init sdhci_drv_init(void)
  1108. {
  1109. printk(KERN_INFO DRIVER_NAME
  1110. ": Secure Digital Host Controller Interface driver, "
  1111. DRIVER_VERSION "\n");
  1112. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1113. return pci_register_driver(&sdhci_driver);
  1114. }
  1115. static void __exit sdhci_drv_exit(void)
  1116. {
  1117. DBG("Exiting\n");
  1118. pci_unregister_driver(&sdhci_driver);
  1119. }
  1120. module_init(sdhci_drv_init);
  1121. module_exit(sdhci_drv_exit);
  1122. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1123. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1124. MODULE_VERSION(DRIVER_VERSION);
  1125. MODULE_LICENSE("GPL");