attach.c 8.4 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include "ath5k.h"
  23. #include "reg.h"
  24. #include "debug.h"
  25. #include "base.h"
  26. /**
  27. * ath5k_hw_post - Power On Self Test helper function
  28. *
  29. * @ah: The &struct ath5k_hw
  30. */
  31. static int ath5k_hw_post(struct ath5k_hw *ah)
  32. {
  33. int i, c;
  34. u16 cur_reg;
  35. u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
  36. u32 var_pattern;
  37. u32 static_pattern[4] = {
  38. 0x55555555, 0xaaaaaaaa,
  39. 0x66666666, 0x99999999
  40. };
  41. u32 init_val;
  42. u32 cur_val;
  43. for (c = 0; c < 2; c++) {
  44. cur_reg = regs[c];
  45. /* Save previous value */
  46. init_val = ath5k_hw_reg_read(ah, cur_reg);
  47. for (i = 0; i < 256; i++) {
  48. var_pattern = i << 16 | i;
  49. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  50. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  51. if (cur_val != var_pattern) {
  52. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  53. return -EAGAIN;
  54. }
  55. /* Found on ndiswrapper dumps */
  56. var_pattern = 0x0039080f;
  57. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  58. }
  59. for (i = 0; i < 4; i++) {
  60. var_pattern = static_pattern[i];
  61. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  62. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  63. if (cur_val != var_pattern) {
  64. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  65. return -EAGAIN;
  66. }
  67. /* Found on ndiswrapper dumps */
  68. var_pattern = 0x003b080f;
  69. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  70. }
  71. /* Restore previous value */
  72. ath5k_hw_reg_write(ah, init_val, cur_reg);
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ath5k_hw_attach - Check if hw is supported and init the needed structs
  78. *
  79. * @sc: The &struct ath5k_softc we got from the driver's attach function
  80. * @mac_version: The mac version id (check out ath5k.h) based on pci id
  81. *
  82. * Check if the device is supported, perform a POST and initialize the needed
  83. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  84. * -ENODEV if the device is not supported or prints an error msg if something
  85. * else went wrong.
  86. */
  87. struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
  88. {
  89. struct ath5k_hw *ah;
  90. struct pci_dev *pdev = sc->pdev;
  91. u8 mac[ETH_ALEN];
  92. int ret;
  93. u32 srev;
  94. /*If we passed the test malloc a ath5k_hw struct*/
  95. ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
  96. if (ah == NULL) {
  97. ret = -ENOMEM;
  98. ATH5K_ERR(sc, "out of memory\n");
  99. goto err;
  100. }
  101. ah->ah_sc = sc;
  102. ah->ah_iobase = sc->iobase;
  103. /*
  104. * HW information
  105. */
  106. ah->ah_op_mode = NL80211_IFTYPE_STATION;
  107. ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
  108. ah->ah_turbo = false;
  109. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  110. ah->ah_imr = 0;
  111. ah->ah_atim_window = 0;
  112. ah->ah_aifs = AR5K_TUNE_AIFS;
  113. ah->ah_cw_min = AR5K_TUNE_CWMIN;
  114. ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
  115. ah->ah_software_retry = false;
  116. ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
  117. /*
  118. * Set the mac revision based on the pci id
  119. */
  120. ah->ah_version = mac_version;
  121. /*Fill the ath5k_hw struct with the needed functions*/
  122. ret = ath5k_hw_init_desc_functions(ah);
  123. if (ret)
  124. goto err_free;
  125. /* Bring device out of sleep and reset it's units */
  126. ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
  127. if (ret)
  128. goto err_free;
  129. /* Get MAC, PHY and RADIO revisions */
  130. srev = ath5k_hw_reg_read(ah, AR5K_SREV);
  131. ah->ah_mac_srev = srev;
  132. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  133. ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
  134. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  135. 0xffffffff;
  136. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  137. CHANNEL_5GHZ);
  138. if (ah->ah_version == AR5K_AR5210)
  139. ah->ah_radio_2ghz_revision = 0;
  140. else
  141. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  142. CHANNEL_2GHZ);
  143. /* Return on unsuported chips (unsupported eeprom etc) */
  144. if ((srev >= AR5K_SREV_VER_AR5416) &&
  145. (srev < AR5K_SREV_VER_AR2425)) {
  146. ATH5K_ERR(sc, "Device not yet supported.\n");
  147. ret = -ENODEV;
  148. goto err_free;
  149. } else if (srev == AR5K_SREV_VER_AR2425) {
  150. ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
  151. }
  152. /* Identify single chip solutions */
  153. if (((srev <= AR5K_SREV_VER_AR5414) &&
  154. (srev >= AR5K_SREV_VER_AR2413)) ||
  155. (srev == AR5K_SREV_VER_AR2425)) {
  156. ah->ah_single_chip = true;
  157. } else {
  158. ah->ah_single_chip = false;
  159. }
  160. /* Single chip radio */
  161. if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
  162. ah->ah_radio_2ghz_revision = 0;
  163. /* Identify the radio chip*/
  164. if (ah->ah_version == AR5K_AR5210) {
  165. ah->ah_radio = AR5K_RF5110;
  166. /*
  167. * Register returns 0x0/0x04 for radio revision
  168. * so ath5k_hw_radio_revision doesn't parse the value
  169. * correctly. For now we are based on mac's srev to
  170. * identify RF2425 radio.
  171. */
  172. } else if (srev == AR5K_SREV_VER_AR2425) {
  173. ah->ah_radio = AR5K_RF2425;
  174. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
  175. } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
  176. ah->ah_radio = AR5K_RF5111;
  177. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
  178. } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
  179. ah->ah_radio = AR5K_RF5112;
  180. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
  181. } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
  182. ah->ah_radio = AR5K_RF2413;
  183. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
  184. } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
  185. ah->ah_radio = AR5K_RF5413;
  186. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
  187. } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
  188. /* AR5424 */
  189. if (srev >= AR5K_SREV_VER_AR5424) {
  190. ah->ah_radio = AR5K_RF5413;
  191. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
  192. /* AR2424 */
  193. } else {
  194. ah->ah_radio = AR5K_RF2413; /* For testing */
  195. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
  196. }
  197. }
  198. ah->ah_phy = AR5K_PHY(0);
  199. /*
  200. * Write PCI-E power save settings
  201. */
  202. if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
  203. ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
  204. ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
  205. ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
  206. ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
  207. ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
  208. ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
  209. ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
  210. ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
  211. ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
  212. ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
  213. }
  214. /*
  215. * POST
  216. */
  217. ret = ath5k_hw_post(ah);
  218. if (ret)
  219. goto err_free;
  220. /* Write AR5K_PCICFG_UNK on 2112B and later chips */
  221. if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
  222. srev > AR5K_SREV_VER_AR2413) {
  223. ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG);
  224. }
  225. /*
  226. * Get card capabilities, values, ...
  227. */
  228. ret = ath5k_eeprom_init(ah);
  229. if (ret) {
  230. ATH5K_ERR(sc, "unable to init EEPROM\n");
  231. goto err_free;
  232. }
  233. /* Get misc capabilities */
  234. ret = ath5k_hw_set_capabilities(ah);
  235. if (ret) {
  236. ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
  237. sc->pdev->device);
  238. goto err_free;
  239. }
  240. /* Get MAC address */
  241. ret = ath5k_eeprom_read_mac(ah, mac);
  242. if (ret) {
  243. ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
  244. sc->pdev->device);
  245. goto err_free;
  246. }
  247. ath5k_hw_set_lladdr(ah, mac);
  248. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  249. memset(ah->ah_bssid, 0xff, ETH_ALEN);
  250. ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
  251. ath5k_hw_set_opmode(ah);
  252. ath5k_hw_set_rfgain_opt(ah);
  253. return ah;
  254. err_free:
  255. kfree(ah);
  256. err:
  257. return ERR_PTR(ret);
  258. }
  259. /**
  260. * ath5k_hw_detach - Free the ath5k_hw struct
  261. *
  262. * @ah: The &struct ath5k_hw
  263. */
  264. void ath5k_hw_detach(struct ath5k_hw *ah)
  265. {
  266. ATH5K_TRACE(ah->ah_sc);
  267. __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
  268. if (ah->ah_rf_banks != NULL)
  269. kfree(ah->ah_rf_banks);
  270. /* assume interrupts are down */
  271. kfree(ah);
  272. }