hdmi.c 35 KB

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  1. /*
  2. * Copyright (C) 2012 Avionic Design GmbH
  3. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/debugfs.h>
  11. #include <linux/gpio.h>
  12. #include <linux/hdmi.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/clk/tegra.h>
  18. #include <drm/drm_edid.h>
  19. #include "hdmi.h"
  20. #include "drm.h"
  21. #include "dc.h"
  22. #include "host1x_client.h"
  23. struct tegra_hdmi {
  24. struct host1x_client client;
  25. struct tegra_output output;
  26. struct device *dev;
  27. struct regulator *vdd;
  28. struct regulator *pll;
  29. void __iomem *regs;
  30. unsigned int irq;
  31. struct clk *clk_parent;
  32. struct clk *clk;
  33. unsigned int audio_source;
  34. unsigned int audio_freq;
  35. bool stereo;
  36. bool dvi;
  37. struct drm_info_list *debugfs_files;
  38. struct drm_minor *minor;
  39. struct dentry *debugfs;
  40. };
  41. static inline struct tegra_hdmi *
  42. host1x_client_to_hdmi(struct host1x_client *client)
  43. {
  44. return container_of(client, struct tegra_hdmi, client);
  45. }
  46. static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  47. {
  48. return container_of(output, struct tegra_hdmi, output);
  49. }
  50. #define HDMI_AUDIOCLK_FREQ 216000000
  51. #define HDMI_REKEY_DEFAULT 56
  52. enum {
  53. AUTO = 0,
  54. SPDIF,
  55. HDA,
  56. };
  57. static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
  58. unsigned long reg)
  59. {
  60. return readl(hdmi->regs + (reg << 2));
  61. }
  62. static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
  63. unsigned long reg)
  64. {
  65. writel(val, hdmi->regs + (reg << 2));
  66. }
  67. struct tegra_hdmi_audio_config {
  68. unsigned int pclk;
  69. unsigned int n;
  70. unsigned int cts;
  71. unsigned int aval;
  72. };
  73. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
  74. { 25200000, 4096, 25200, 24000 },
  75. { 27000000, 4096, 27000, 24000 },
  76. { 74250000, 4096, 74250, 24000 },
  77. { 148500000, 4096, 148500, 24000 },
  78. { 0, 0, 0, 0 },
  79. };
  80. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
  81. { 25200000, 5880, 26250, 25000 },
  82. { 27000000, 5880, 28125, 25000 },
  83. { 74250000, 4704, 61875, 20000 },
  84. { 148500000, 4704, 123750, 20000 },
  85. { 0, 0, 0, 0 },
  86. };
  87. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
  88. { 25200000, 6144, 25200, 24000 },
  89. { 27000000, 6144, 27000, 24000 },
  90. { 74250000, 6144, 74250, 24000 },
  91. { 148500000, 6144, 148500, 24000 },
  92. { 0, 0, 0, 0 },
  93. };
  94. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
  95. { 25200000, 11760, 26250, 25000 },
  96. { 27000000, 11760, 28125, 25000 },
  97. { 74250000, 9408, 61875, 20000 },
  98. { 148500000, 9408, 123750, 20000 },
  99. { 0, 0, 0, 0 },
  100. };
  101. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
  102. { 25200000, 12288, 25200, 24000 },
  103. { 27000000, 12288, 27000, 24000 },
  104. { 74250000, 12288, 74250, 24000 },
  105. { 148500000, 12288, 148500, 24000 },
  106. { 0, 0, 0, 0 },
  107. };
  108. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
  109. { 25200000, 23520, 26250, 25000 },
  110. { 27000000, 23520, 28125, 25000 },
  111. { 74250000, 18816, 61875, 20000 },
  112. { 148500000, 18816, 123750, 20000 },
  113. { 0, 0, 0, 0 },
  114. };
  115. static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
  116. { 25200000, 24576, 25200, 24000 },
  117. { 27000000, 24576, 27000, 24000 },
  118. { 74250000, 24576, 74250, 24000 },
  119. { 148500000, 24576, 148500, 24000 },
  120. { 0, 0, 0, 0 },
  121. };
  122. struct tmds_config {
  123. unsigned int pclk;
  124. u32 pll0;
  125. u32 pll1;
  126. u32 pe_current;
  127. u32 drive_current;
  128. };
  129. static const struct tmds_config tegra2_tmds_config[] = {
  130. { /* slow pixel clock modes */
  131. .pclk = 27000000,
  132. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  133. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
  134. SOR_PLL_TX_REG_LOAD(3),
  135. .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
  136. .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
  137. PE_CURRENT1(PE_CURRENT_0_0_mA) |
  138. PE_CURRENT2(PE_CURRENT_0_0_mA) |
  139. PE_CURRENT3(PE_CURRENT_0_0_mA),
  140. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
  141. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
  142. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
  143. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
  144. },
  145. { /* high pixel clock modes */
  146. .pclk = UINT_MAX,
  147. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  148. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
  149. SOR_PLL_TX_REG_LOAD(3),
  150. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  151. .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
  152. PE_CURRENT1(PE_CURRENT_6_0_mA) |
  153. PE_CURRENT2(PE_CURRENT_6_0_mA) |
  154. PE_CURRENT3(PE_CURRENT_6_0_mA),
  155. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
  156. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
  157. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
  158. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
  159. },
  160. };
  161. static const struct tmds_config tegra3_tmds_config[] = {
  162. { /* 480p modes */
  163. .pclk = 27000000,
  164. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  165. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
  166. SOR_PLL_TX_REG_LOAD(0),
  167. .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
  168. .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
  169. PE_CURRENT1(PE_CURRENT_0_0_mA) |
  170. PE_CURRENT2(PE_CURRENT_0_0_mA) |
  171. PE_CURRENT3(PE_CURRENT_0_0_mA),
  172. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  173. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  174. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  175. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  176. }, { /* 720p modes */
  177. .pclk = 74250000,
  178. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  179. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
  180. SOR_PLL_TX_REG_LOAD(0),
  181. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  182. .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
  183. PE_CURRENT1(PE_CURRENT_5_0_mA) |
  184. PE_CURRENT2(PE_CURRENT_5_0_mA) |
  185. PE_CURRENT3(PE_CURRENT_5_0_mA),
  186. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  187. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  188. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  189. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  190. }, { /* 1080p modes */
  191. .pclk = UINT_MAX,
  192. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  193. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
  194. SOR_PLL_TX_REG_LOAD(0),
  195. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  196. .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
  197. PE_CURRENT1(PE_CURRENT_5_0_mA) |
  198. PE_CURRENT2(PE_CURRENT_5_0_mA) |
  199. PE_CURRENT3(PE_CURRENT_5_0_mA),
  200. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  201. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  202. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  203. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  204. },
  205. };
  206. static const struct tegra_hdmi_audio_config *
  207. tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
  208. {
  209. const struct tegra_hdmi_audio_config *table;
  210. switch (audio_freq) {
  211. case 32000:
  212. table = tegra_hdmi_audio_32k;
  213. break;
  214. case 44100:
  215. table = tegra_hdmi_audio_44_1k;
  216. break;
  217. case 48000:
  218. table = tegra_hdmi_audio_48k;
  219. break;
  220. case 88200:
  221. table = tegra_hdmi_audio_88_2k;
  222. break;
  223. case 96000:
  224. table = tegra_hdmi_audio_96k;
  225. break;
  226. case 176400:
  227. table = tegra_hdmi_audio_176_4k;
  228. break;
  229. case 192000:
  230. table = tegra_hdmi_audio_192k;
  231. break;
  232. default:
  233. return NULL;
  234. }
  235. while (table->pclk) {
  236. if (table->pclk == pclk)
  237. return table;
  238. table++;
  239. }
  240. return NULL;
  241. }
  242. static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
  243. {
  244. const unsigned int freqs[] = {
  245. 32000, 44100, 48000, 88200, 96000, 176400, 192000
  246. };
  247. unsigned int i;
  248. for (i = 0; i < ARRAY_SIZE(freqs); i++) {
  249. unsigned int f = freqs[i];
  250. unsigned int eight_half;
  251. unsigned long value;
  252. unsigned int delta;
  253. if (f > 96000)
  254. delta = 2;
  255. else if (f > 480000)
  256. delta = 6;
  257. else
  258. delta = 9;
  259. eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
  260. value = AUDIO_FS_LOW(eight_half - delta) |
  261. AUDIO_FS_HIGH(eight_half + delta);
  262. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
  263. }
  264. }
  265. static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
  266. {
  267. struct device_node *node = hdmi->dev->of_node;
  268. const struct tegra_hdmi_audio_config *config;
  269. unsigned int offset = 0;
  270. unsigned long value;
  271. switch (hdmi->audio_source) {
  272. case HDA:
  273. value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
  274. break;
  275. case SPDIF:
  276. value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
  277. break;
  278. default:
  279. value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
  280. break;
  281. }
  282. if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
  283. value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
  284. AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
  285. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
  286. } else {
  287. value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
  288. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
  289. value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
  290. AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
  291. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
  292. }
  293. config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
  294. if (!config) {
  295. dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
  296. hdmi->audio_freq, pclk);
  297. return -EINVAL;
  298. }
  299. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
  300. value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
  301. AUDIO_N_VALUE(config->n - 1);
  302. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
  303. tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
  304. HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
  305. value = ACR_SUBPACK_CTS(config->cts);
  306. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
  307. value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
  308. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
  309. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
  310. value &= ~AUDIO_N_RESETF;
  311. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
  312. if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
  313. switch (hdmi->audio_freq) {
  314. case 32000:
  315. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
  316. break;
  317. case 44100:
  318. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
  319. break;
  320. case 48000:
  321. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
  322. break;
  323. case 88200:
  324. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
  325. break;
  326. case 96000:
  327. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
  328. break;
  329. case 176400:
  330. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
  331. break;
  332. case 192000:
  333. offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
  334. break;
  335. }
  336. tegra_hdmi_writel(hdmi, config->aval, offset);
  337. }
  338. tegra_hdmi_setup_audio_fs_tables(hdmi);
  339. return 0;
  340. }
  341. static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
  342. {
  343. unsigned long value = 0;
  344. size_t i;
  345. for (i = size; i > 0; i--)
  346. value = (value << 8) | ptr[i - 1];
  347. return value;
  348. }
  349. static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
  350. size_t size)
  351. {
  352. const u8 *ptr = data;
  353. unsigned long offset;
  354. unsigned long value;
  355. size_t i, j;
  356. switch (ptr[0]) {
  357. case HDMI_INFOFRAME_TYPE_AVI:
  358. offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
  359. break;
  360. case HDMI_INFOFRAME_TYPE_AUDIO:
  361. offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
  362. break;
  363. case HDMI_INFOFRAME_TYPE_VENDOR:
  364. offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
  365. break;
  366. default:
  367. dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
  368. ptr[0]);
  369. return;
  370. }
  371. value = INFOFRAME_HEADER_TYPE(ptr[0]) |
  372. INFOFRAME_HEADER_VERSION(ptr[1]) |
  373. INFOFRAME_HEADER_LEN(ptr[2]);
  374. tegra_hdmi_writel(hdmi, value, offset);
  375. offset++;
  376. /*
  377. * Each subpack contains 7 bytes, divided into:
  378. * - subpack_low: bytes 0 - 3
  379. * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
  380. */
  381. for (i = 3, j = 0; i < size; i += 7, j += 8) {
  382. size_t rem = size - i, num = min_t(size_t, rem, 4);
  383. value = tegra_hdmi_subpack(&ptr[i], num);
  384. tegra_hdmi_writel(hdmi, value, offset++);
  385. num = min_t(size_t, rem - num, 3);
  386. value = tegra_hdmi_subpack(&ptr[i + 4], num);
  387. tegra_hdmi_writel(hdmi, value, offset++);
  388. }
  389. }
  390. static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
  391. struct drm_display_mode *mode)
  392. {
  393. struct hdmi_avi_infoframe frame;
  394. u8 buffer[17];
  395. ssize_t err;
  396. if (hdmi->dvi) {
  397. tegra_hdmi_writel(hdmi, 0,
  398. HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  399. return;
  400. }
  401. err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
  402. if (err < 0) {
  403. dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
  404. return;
  405. }
  406. err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  407. if (err < 0) {
  408. dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
  409. return;
  410. }
  411. tegra_hdmi_write_infopack(hdmi, buffer, err);
  412. tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
  413. HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  414. }
  415. static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
  416. {
  417. struct hdmi_audio_infoframe frame;
  418. u8 buffer[14];
  419. ssize_t err;
  420. if (hdmi->dvi) {
  421. tegra_hdmi_writel(hdmi, 0,
  422. HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  423. return;
  424. }
  425. err = hdmi_audio_infoframe_init(&frame);
  426. if (err < 0) {
  427. dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n",
  428. err);
  429. return;
  430. }
  431. frame.channels = 2;
  432. err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
  433. if (err < 0) {
  434. dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
  435. err);
  436. return;
  437. }
  438. /*
  439. * The audio infoframe has only one set of subpack registers, so the
  440. * infoframe needs to be truncated. One set of subpack registers can
  441. * contain 7 bytes. Including the 3 byte header only the first 10
  442. * bytes can be programmed.
  443. */
  444. tegra_hdmi_write_infopack(hdmi, buffer, min(10, err));
  445. tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
  446. HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  447. }
  448. static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
  449. {
  450. struct hdmi_vendor_infoframe frame;
  451. unsigned long value;
  452. u8 buffer[10];
  453. ssize_t err;
  454. if (!hdmi->stereo) {
  455. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  456. value &= ~GENERIC_CTRL_ENABLE;
  457. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  458. return;
  459. }
  460. hdmi_vendor_infoframe_init(&frame);
  461. frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
  462. err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
  463. if (err < 0) {
  464. dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
  465. err);
  466. return;
  467. }
  468. tegra_hdmi_write_infopack(hdmi, buffer, err);
  469. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  470. value |= GENERIC_CTRL_ENABLE;
  471. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  472. }
  473. static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
  474. const struct tmds_config *tmds)
  475. {
  476. unsigned long value;
  477. tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
  478. tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
  479. tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
  480. value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
  481. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
  482. }
  483. static int tegra_output_hdmi_enable(struct tegra_output *output)
  484. {
  485. unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
  486. struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
  487. struct drm_display_mode *mode = &dc->base.mode;
  488. struct tegra_hdmi *hdmi = to_hdmi(output);
  489. struct device_node *node = hdmi->dev->of_node;
  490. unsigned int pulse_start, div82, pclk;
  491. const struct tmds_config *tmds;
  492. unsigned int num_tmds;
  493. unsigned long value;
  494. int retries = 1000;
  495. int err;
  496. pclk = mode->clock * 1000;
  497. h_sync_width = mode->hsync_end - mode->hsync_start;
  498. h_back_porch = mode->htotal - mode->hsync_end;
  499. h_front_porch = mode->hsync_start - mode->hdisplay;
  500. err = regulator_enable(hdmi->vdd);
  501. if (err < 0) {
  502. dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
  503. return err;
  504. }
  505. err = regulator_enable(hdmi->pll);
  506. if (err < 0) {
  507. dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
  508. return err;
  509. }
  510. /*
  511. * This assumes that the display controller will divide its parent
  512. * clock by 2 to generate the pixel clock.
  513. */
  514. err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
  515. if (err < 0) {
  516. dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
  517. return err;
  518. }
  519. err = clk_set_rate(hdmi->clk, pclk);
  520. if (err < 0)
  521. return err;
  522. err = clk_enable(hdmi->clk);
  523. if (err < 0) {
  524. dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
  525. return err;
  526. }
  527. tegra_periph_reset_assert(hdmi->clk);
  528. usleep_range(1000, 2000);
  529. tegra_periph_reset_deassert(hdmi->clk);
  530. tegra_dc_writel(dc, VSYNC_H_POSITION(1),
  531. DC_DISP_DISP_TIMING_OPTIONS);
  532. tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
  533. DC_DISP_DISP_COLOR_CONTROL);
  534. /* video_preamble uses h_pulse2 */
  535. pulse_start = 1 + h_sync_width + h_back_porch - 10;
  536. tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
  537. value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
  538. PULSE_LAST_END_A;
  539. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
  540. value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
  541. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
  542. value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
  543. VSYNC_WINDOW_ENABLE;
  544. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
  545. if (dc->pipe)
  546. value = HDMI_SRC_DISPLAYB;
  547. else
  548. value = HDMI_SRC_DISPLAYA;
  549. if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
  550. (mode->vdisplay == 576)))
  551. tegra_hdmi_writel(hdmi,
  552. value | ARM_VIDEO_RANGE_FULL,
  553. HDMI_NV_PDISP_INPUT_CONTROL);
  554. else
  555. tegra_hdmi_writel(hdmi,
  556. value | ARM_VIDEO_RANGE_LIMITED,
  557. HDMI_NV_PDISP_INPUT_CONTROL);
  558. div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
  559. value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
  560. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
  561. if (!hdmi->dvi) {
  562. err = tegra_hdmi_setup_audio(hdmi, pclk);
  563. if (err < 0)
  564. hdmi->dvi = true;
  565. }
  566. if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
  567. /*
  568. * TODO: add ELD support
  569. */
  570. }
  571. rekey = HDMI_REKEY_DEFAULT;
  572. value = HDMI_CTRL_REKEY(rekey);
  573. value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
  574. h_front_porch - rekey - 18) / 32);
  575. if (!hdmi->dvi)
  576. value |= HDMI_CTRL_ENABLE;
  577. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
  578. if (hdmi->dvi)
  579. tegra_hdmi_writel(hdmi, 0x0,
  580. HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  581. else
  582. tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
  583. HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  584. tegra_hdmi_setup_avi_infoframe(hdmi, mode);
  585. tegra_hdmi_setup_audio_infoframe(hdmi);
  586. tegra_hdmi_setup_stereo_infoframe(hdmi);
  587. /* TMDS CONFIG */
  588. if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
  589. num_tmds = ARRAY_SIZE(tegra3_tmds_config);
  590. tmds = tegra3_tmds_config;
  591. } else {
  592. num_tmds = ARRAY_SIZE(tegra2_tmds_config);
  593. tmds = tegra2_tmds_config;
  594. }
  595. for (i = 0; i < num_tmds; i++) {
  596. if (pclk <= tmds[i].pclk) {
  597. tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
  598. break;
  599. }
  600. }
  601. tegra_hdmi_writel(hdmi,
  602. SOR_SEQ_CTL_PU_PC(0) |
  603. SOR_SEQ_PU_PC_ALT(0) |
  604. SOR_SEQ_PD_PC(8) |
  605. SOR_SEQ_PD_PC_ALT(8),
  606. HDMI_NV_PDISP_SOR_SEQ_CTL);
  607. value = SOR_SEQ_INST_WAIT_TIME(1) |
  608. SOR_SEQ_INST_WAIT_UNITS_VSYNC |
  609. SOR_SEQ_INST_HALT |
  610. SOR_SEQ_INST_PIN_A_LOW |
  611. SOR_SEQ_INST_PIN_B_LOW |
  612. SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
  613. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
  614. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
  615. value = 0x1c800;
  616. value &= ~SOR_CSTM_ROTCLK(~0);
  617. value |= SOR_CSTM_ROTCLK(2);
  618. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
  619. tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
  620. tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
  621. tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
  622. /* start SOR */
  623. tegra_hdmi_writel(hdmi,
  624. SOR_PWR_NORMAL_STATE_PU |
  625. SOR_PWR_NORMAL_START_NORMAL |
  626. SOR_PWR_SAFE_STATE_PD |
  627. SOR_PWR_SETTING_NEW_TRIGGER,
  628. HDMI_NV_PDISP_SOR_PWR);
  629. tegra_hdmi_writel(hdmi,
  630. SOR_PWR_NORMAL_STATE_PU |
  631. SOR_PWR_NORMAL_START_NORMAL |
  632. SOR_PWR_SAFE_STATE_PD |
  633. SOR_PWR_SETTING_NEW_DONE,
  634. HDMI_NV_PDISP_SOR_PWR);
  635. do {
  636. BUG_ON(--retries < 0);
  637. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
  638. } while (value & SOR_PWR_SETTING_NEW_PENDING);
  639. value = SOR_STATE_ASY_CRCMODE_COMPLETE |
  640. SOR_STATE_ASY_OWNER_HEAD0 |
  641. SOR_STATE_ASY_SUBOWNER_BOTH |
  642. SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
  643. SOR_STATE_ASY_DEPOL_POS;
  644. /* setup sync polarities */
  645. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  646. value |= SOR_STATE_ASY_HSYNCPOL_POS;
  647. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  648. value |= SOR_STATE_ASY_HSYNCPOL_NEG;
  649. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  650. value |= SOR_STATE_ASY_VSYNCPOL_POS;
  651. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  652. value |= SOR_STATE_ASY_VSYNCPOL_NEG;
  653. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
  654. value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
  655. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
  656. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
  657. tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
  658. tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
  659. HDMI_NV_PDISP_SOR_STATE1);
  660. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
  661. tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
  662. value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
  663. PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
  664. tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
  665. value = DISP_CTRL_MODE_C_DISPLAY;
  666. tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
  667. tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
  668. tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
  669. /* TODO: add HDCP support */
  670. return 0;
  671. }
  672. static int tegra_output_hdmi_disable(struct tegra_output *output)
  673. {
  674. struct tegra_hdmi *hdmi = to_hdmi(output);
  675. tegra_periph_reset_assert(hdmi->clk);
  676. clk_disable(hdmi->clk);
  677. regulator_disable(hdmi->pll);
  678. regulator_disable(hdmi->vdd);
  679. return 0;
  680. }
  681. static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
  682. struct clk *clk, unsigned long pclk)
  683. {
  684. struct tegra_hdmi *hdmi = to_hdmi(output);
  685. struct clk *base;
  686. int err;
  687. err = clk_set_parent(clk, hdmi->clk_parent);
  688. if (err < 0) {
  689. dev_err(output->dev, "failed to set parent: %d\n", err);
  690. return err;
  691. }
  692. base = clk_get_parent(hdmi->clk_parent);
  693. /*
  694. * This assumes that the parent clock is pll_d_out0 or pll_d2_out
  695. * respectively, each of which divides the base pll_d by 2.
  696. */
  697. err = clk_set_rate(base, pclk * 2);
  698. if (err < 0)
  699. dev_err(output->dev,
  700. "failed to set base clock rate to %lu Hz\n",
  701. pclk * 2);
  702. return 0;
  703. }
  704. static int tegra_output_hdmi_check_mode(struct tegra_output *output,
  705. struct drm_display_mode *mode,
  706. enum drm_mode_status *status)
  707. {
  708. struct tegra_hdmi *hdmi = to_hdmi(output);
  709. unsigned long pclk = mode->clock * 1000;
  710. struct clk *parent;
  711. long err;
  712. parent = clk_get_parent(hdmi->clk_parent);
  713. err = clk_round_rate(parent, pclk * 4);
  714. if (err < 0)
  715. *status = MODE_NOCLOCK;
  716. else
  717. *status = MODE_OK;
  718. return 0;
  719. }
  720. static const struct tegra_output_ops hdmi_ops = {
  721. .enable = tegra_output_hdmi_enable,
  722. .disable = tegra_output_hdmi_disable,
  723. .setup_clock = tegra_output_hdmi_setup_clock,
  724. .check_mode = tegra_output_hdmi_check_mode,
  725. };
  726. static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
  727. {
  728. struct drm_info_node *node = s->private;
  729. struct tegra_hdmi *hdmi = node->info_ent->data;
  730. int err;
  731. err = clk_enable(hdmi->clk);
  732. if (err)
  733. return err;
  734. #define DUMP_REG(name) \
  735. seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
  736. tegra_hdmi_readl(hdmi, name))
  737. DUMP_REG(HDMI_CTXSW);
  738. DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
  739. DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
  740. DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
  741. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
  742. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
  743. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
  744. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
  745. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
  746. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
  747. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
  748. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
  749. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
  750. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
  751. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
  752. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
  753. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
  754. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
  755. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
  756. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
  757. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
  758. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
  759. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
  760. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
  761. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
  762. DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
  763. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
  764. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
  765. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
  766. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
  767. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  768. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
  769. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
  770. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
  771. DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
  772. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  773. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
  774. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
  775. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
  776. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
  777. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
  778. DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
  779. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  780. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
  781. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
  782. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
  783. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
  784. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
  785. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
  786. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
  787. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
  788. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
  789. DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
  790. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
  791. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
  792. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
  793. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
  794. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
  795. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
  796. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
  797. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
  798. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
  799. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
  800. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
  801. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
  802. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
  803. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
  804. DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
  805. DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
  806. DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
  807. DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
  808. DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
  809. DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
  810. DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
  811. DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
  812. DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
  813. DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
  814. DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
  815. DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
  816. DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
  817. DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
  818. DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
  819. DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
  820. DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
  821. DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
  822. DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
  823. DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
  824. DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
  825. DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
  826. DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
  827. DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
  828. DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
  829. DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
  830. DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
  831. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
  832. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
  833. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
  834. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
  835. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
  836. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
  837. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
  838. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
  839. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
  840. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
  841. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
  842. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
  843. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
  844. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
  845. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
  846. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
  847. DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
  848. DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
  849. DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
  850. DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
  851. DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
  852. DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
  853. DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
  854. DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
  855. DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
  856. DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
  857. DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
  858. DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
  859. DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
  860. DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
  861. DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
  862. DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
  863. DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
  864. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
  865. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
  866. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
  867. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
  868. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
  869. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
  870. DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
  871. DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
  872. DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
  873. DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
  874. DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
  875. DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
  876. DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
  877. DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
  878. DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
  879. DUMP_REG(HDMI_NV_PDISP_SCRATCH);
  880. DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
  881. DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
  882. DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
  883. DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
  884. DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
  885. DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
  886. DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
  887. DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
  888. DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
  889. DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
  890. DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
  891. DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
  892. DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
  893. DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
  894. #undef DUMP_REG
  895. clk_disable(hdmi->clk);
  896. return 0;
  897. }
  898. static struct drm_info_list debugfs_files[] = {
  899. { "regs", tegra_hdmi_show_regs, 0, NULL },
  900. };
  901. static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
  902. struct drm_minor *minor)
  903. {
  904. unsigned int i;
  905. int err;
  906. hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
  907. if (!hdmi->debugfs)
  908. return -ENOMEM;
  909. hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
  910. GFP_KERNEL);
  911. if (!hdmi->debugfs_files) {
  912. err = -ENOMEM;
  913. goto remove;
  914. }
  915. for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
  916. hdmi->debugfs_files[i].data = hdmi;
  917. err = drm_debugfs_create_files(hdmi->debugfs_files,
  918. ARRAY_SIZE(debugfs_files),
  919. hdmi->debugfs, minor);
  920. if (err < 0)
  921. goto free;
  922. hdmi->minor = minor;
  923. return 0;
  924. free:
  925. kfree(hdmi->debugfs_files);
  926. hdmi->debugfs_files = NULL;
  927. remove:
  928. debugfs_remove(hdmi->debugfs);
  929. hdmi->debugfs = NULL;
  930. return err;
  931. }
  932. static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
  933. {
  934. drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
  935. hdmi->minor);
  936. hdmi->minor = NULL;
  937. kfree(hdmi->debugfs_files);
  938. hdmi->debugfs_files = NULL;
  939. debugfs_remove(hdmi->debugfs);
  940. hdmi->debugfs = NULL;
  941. return 0;
  942. }
  943. static int tegra_hdmi_drm_init(struct host1x_client *client,
  944. struct drm_device *drm)
  945. {
  946. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  947. int err;
  948. hdmi->output.type = TEGRA_OUTPUT_HDMI;
  949. hdmi->output.dev = client->dev;
  950. hdmi->output.ops = &hdmi_ops;
  951. err = tegra_output_init(drm, &hdmi->output);
  952. if (err < 0) {
  953. dev_err(client->dev, "output setup failed: %d\n", err);
  954. return err;
  955. }
  956. if (IS_ENABLED(CONFIG_DEBUG_FS)) {
  957. err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
  958. if (err < 0)
  959. dev_err(client->dev, "debugfs setup failed: %d\n", err);
  960. }
  961. return 0;
  962. }
  963. static int tegra_hdmi_drm_exit(struct host1x_client *client)
  964. {
  965. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  966. int err;
  967. if (IS_ENABLED(CONFIG_DEBUG_FS)) {
  968. err = tegra_hdmi_debugfs_exit(hdmi);
  969. if (err < 0)
  970. dev_err(client->dev, "debugfs cleanup failed: %d\n",
  971. err);
  972. }
  973. err = tegra_output_disable(&hdmi->output);
  974. if (err < 0) {
  975. dev_err(client->dev, "output failed to disable: %d\n", err);
  976. return err;
  977. }
  978. err = tegra_output_exit(&hdmi->output);
  979. if (err < 0) {
  980. dev_err(client->dev, "output cleanup failed: %d\n", err);
  981. return err;
  982. }
  983. return 0;
  984. }
  985. static const struct host1x_client_ops hdmi_client_ops = {
  986. .drm_init = tegra_hdmi_drm_init,
  987. .drm_exit = tegra_hdmi_drm_exit,
  988. };
  989. static int tegra_hdmi_probe(struct platform_device *pdev)
  990. {
  991. struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
  992. struct tegra_hdmi *hdmi;
  993. struct resource *regs;
  994. int err;
  995. hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
  996. if (!hdmi)
  997. return -ENOMEM;
  998. hdmi->dev = &pdev->dev;
  999. hdmi->audio_source = AUTO;
  1000. hdmi->audio_freq = 44100;
  1001. hdmi->stereo = false;
  1002. hdmi->dvi = false;
  1003. hdmi->clk = devm_clk_get(&pdev->dev, NULL);
  1004. if (IS_ERR(hdmi->clk)) {
  1005. dev_err(&pdev->dev, "failed to get clock\n");
  1006. return PTR_ERR(hdmi->clk);
  1007. }
  1008. err = clk_prepare(hdmi->clk);
  1009. if (err < 0)
  1010. return err;
  1011. hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
  1012. if (IS_ERR(hdmi->clk_parent))
  1013. return PTR_ERR(hdmi->clk_parent);
  1014. err = clk_prepare(hdmi->clk_parent);
  1015. if (err < 0)
  1016. return err;
  1017. err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
  1018. if (err < 0) {
  1019. dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
  1020. return err;
  1021. }
  1022. hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
  1023. if (IS_ERR(hdmi->vdd)) {
  1024. dev_err(&pdev->dev, "failed to get VDD regulator\n");
  1025. return PTR_ERR(hdmi->vdd);
  1026. }
  1027. hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
  1028. if (IS_ERR(hdmi->pll)) {
  1029. dev_err(&pdev->dev, "failed to get PLL regulator\n");
  1030. return PTR_ERR(hdmi->pll);
  1031. }
  1032. hdmi->output.dev = &pdev->dev;
  1033. err = tegra_output_parse_dt(&hdmi->output);
  1034. if (err < 0)
  1035. return err;
  1036. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1037. if (!regs)
  1038. return -ENXIO;
  1039. hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
  1040. if (IS_ERR(hdmi->regs))
  1041. return PTR_ERR(hdmi->regs);
  1042. err = platform_get_irq(pdev, 0);
  1043. if (err < 0)
  1044. return err;
  1045. hdmi->irq = err;
  1046. hdmi->client.ops = &hdmi_client_ops;
  1047. INIT_LIST_HEAD(&hdmi->client.list);
  1048. hdmi->client.dev = &pdev->dev;
  1049. err = host1x_register_client(host1x, &hdmi->client);
  1050. if (err < 0) {
  1051. dev_err(&pdev->dev, "failed to register host1x client: %d\n",
  1052. err);
  1053. return err;
  1054. }
  1055. platform_set_drvdata(pdev, hdmi);
  1056. return 0;
  1057. }
  1058. static int tegra_hdmi_remove(struct platform_device *pdev)
  1059. {
  1060. struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
  1061. struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
  1062. int err;
  1063. err = host1x_unregister_client(host1x, &hdmi->client);
  1064. if (err < 0) {
  1065. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  1066. err);
  1067. return err;
  1068. }
  1069. clk_unprepare(hdmi->clk_parent);
  1070. clk_unprepare(hdmi->clk);
  1071. return 0;
  1072. }
  1073. static struct of_device_id tegra_hdmi_of_match[] = {
  1074. { .compatible = "nvidia,tegra30-hdmi", },
  1075. { .compatible = "nvidia,tegra20-hdmi", },
  1076. { },
  1077. };
  1078. struct platform_driver tegra_hdmi_driver = {
  1079. .driver = {
  1080. .name = "tegra-hdmi",
  1081. .owner = THIS_MODULE,
  1082. .of_match_table = tegra_hdmi_of_match,
  1083. },
  1084. .probe = tegra_hdmi_probe,
  1085. .remove = tegra_hdmi_remove,
  1086. };