si.c 201 KB

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <linux/slab.h>
  26. #include <linux/module.h>
  27. #include <drm/drmP.h>
  28. #include "radeon.h"
  29. #include "radeon_asic.h"
  30. #include <drm/radeon_drm.h>
  31. #include "sid.h"
  32. #include "atom.h"
  33. #include "si_blit_shaders.h"
  34. #include "clearstate_si.h"
  35. #include "radeon_ucode.h"
  36. MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
  37. MODULE_FIRMWARE("radeon/TAHITI_me.bin");
  38. MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
  39. MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
  40. MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
  41. MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
  42. MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
  43. MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
  44. MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
  45. MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
  46. MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
  47. MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
  48. MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
  49. MODULE_FIRMWARE("radeon/VERDE_me.bin");
  50. MODULE_FIRMWARE("radeon/VERDE_ce.bin");
  51. MODULE_FIRMWARE("radeon/VERDE_mc.bin");
  52. MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
  53. MODULE_FIRMWARE("radeon/VERDE_smc.bin");
  54. MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
  55. MODULE_FIRMWARE("radeon/OLAND_me.bin");
  56. MODULE_FIRMWARE("radeon/OLAND_ce.bin");
  57. MODULE_FIRMWARE("radeon/OLAND_mc.bin");
  58. MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
  59. MODULE_FIRMWARE("radeon/OLAND_smc.bin");
  60. MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
  61. MODULE_FIRMWARE("radeon/HAINAN_me.bin");
  62. MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
  63. MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
  64. MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
  65. MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
  66. static void si_pcie_gen3_enable(struct radeon_device *rdev);
  67. static void si_program_aspm(struct radeon_device *rdev);
  68. extern void sumo_rlc_fini(struct radeon_device *rdev);
  69. extern int sumo_rlc_init(struct radeon_device *rdev);
  70. extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  71. extern void r600_ih_ring_fini(struct radeon_device *rdev);
  72. extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  73. extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  74. extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  75. extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
  76. extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
  77. extern bool evergreen_is_display_hung(struct radeon_device *rdev);
  78. extern void si_dma_vm_set_page(struct radeon_device *rdev,
  79. struct radeon_ib *ib,
  80. uint64_t pe,
  81. uint64_t addr, unsigned count,
  82. uint32_t incr, uint32_t flags);
  83. static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
  84. bool enable);
  85. static const u32 verde_rlc_save_restore_register_list[] =
  86. {
  87. (0x8000 << 16) | (0x98f4 >> 2),
  88. 0x00000000,
  89. (0x8040 << 16) | (0x98f4 >> 2),
  90. 0x00000000,
  91. (0x8000 << 16) | (0xe80 >> 2),
  92. 0x00000000,
  93. (0x8040 << 16) | (0xe80 >> 2),
  94. 0x00000000,
  95. (0x8000 << 16) | (0x89bc >> 2),
  96. 0x00000000,
  97. (0x8040 << 16) | (0x89bc >> 2),
  98. 0x00000000,
  99. (0x8000 << 16) | (0x8c1c >> 2),
  100. 0x00000000,
  101. (0x8040 << 16) | (0x8c1c >> 2),
  102. 0x00000000,
  103. (0x9c00 << 16) | (0x98f0 >> 2),
  104. 0x00000000,
  105. (0x9c00 << 16) | (0xe7c >> 2),
  106. 0x00000000,
  107. (0x8000 << 16) | (0x9148 >> 2),
  108. 0x00000000,
  109. (0x8040 << 16) | (0x9148 >> 2),
  110. 0x00000000,
  111. (0x9c00 << 16) | (0x9150 >> 2),
  112. 0x00000000,
  113. (0x9c00 << 16) | (0x897c >> 2),
  114. 0x00000000,
  115. (0x9c00 << 16) | (0x8d8c >> 2),
  116. 0x00000000,
  117. (0x9c00 << 16) | (0xac54 >> 2),
  118. 0X00000000,
  119. 0x3,
  120. (0x9c00 << 16) | (0x98f8 >> 2),
  121. 0x00000000,
  122. (0x9c00 << 16) | (0x9910 >> 2),
  123. 0x00000000,
  124. (0x9c00 << 16) | (0x9914 >> 2),
  125. 0x00000000,
  126. (0x9c00 << 16) | (0x9918 >> 2),
  127. 0x00000000,
  128. (0x9c00 << 16) | (0x991c >> 2),
  129. 0x00000000,
  130. (0x9c00 << 16) | (0x9920 >> 2),
  131. 0x00000000,
  132. (0x9c00 << 16) | (0x9924 >> 2),
  133. 0x00000000,
  134. (0x9c00 << 16) | (0x9928 >> 2),
  135. 0x00000000,
  136. (0x9c00 << 16) | (0x992c >> 2),
  137. 0x00000000,
  138. (0x9c00 << 16) | (0x9930 >> 2),
  139. 0x00000000,
  140. (0x9c00 << 16) | (0x9934 >> 2),
  141. 0x00000000,
  142. (0x9c00 << 16) | (0x9938 >> 2),
  143. 0x00000000,
  144. (0x9c00 << 16) | (0x993c >> 2),
  145. 0x00000000,
  146. (0x9c00 << 16) | (0x9940 >> 2),
  147. 0x00000000,
  148. (0x9c00 << 16) | (0x9944 >> 2),
  149. 0x00000000,
  150. (0x9c00 << 16) | (0x9948 >> 2),
  151. 0x00000000,
  152. (0x9c00 << 16) | (0x994c >> 2),
  153. 0x00000000,
  154. (0x9c00 << 16) | (0x9950 >> 2),
  155. 0x00000000,
  156. (0x9c00 << 16) | (0x9954 >> 2),
  157. 0x00000000,
  158. (0x9c00 << 16) | (0x9958 >> 2),
  159. 0x00000000,
  160. (0x9c00 << 16) | (0x995c >> 2),
  161. 0x00000000,
  162. (0x9c00 << 16) | (0x9960 >> 2),
  163. 0x00000000,
  164. (0x9c00 << 16) | (0x9964 >> 2),
  165. 0x00000000,
  166. (0x9c00 << 16) | (0x9968 >> 2),
  167. 0x00000000,
  168. (0x9c00 << 16) | (0x996c >> 2),
  169. 0x00000000,
  170. (0x9c00 << 16) | (0x9970 >> 2),
  171. 0x00000000,
  172. (0x9c00 << 16) | (0x9974 >> 2),
  173. 0x00000000,
  174. (0x9c00 << 16) | (0x9978 >> 2),
  175. 0x00000000,
  176. (0x9c00 << 16) | (0x997c >> 2),
  177. 0x00000000,
  178. (0x9c00 << 16) | (0x9980 >> 2),
  179. 0x00000000,
  180. (0x9c00 << 16) | (0x9984 >> 2),
  181. 0x00000000,
  182. (0x9c00 << 16) | (0x9988 >> 2),
  183. 0x00000000,
  184. (0x9c00 << 16) | (0x998c >> 2),
  185. 0x00000000,
  186. (0x9c00 << 16) | (0x8c00 >> 2),
  187. 0x00000000,
  188. (0x9c00 << 16) | (0x8c14 >> 2),
  189. 0x00000000,
  190. (0x9c00 << 16) | (0x8c04 >> 2),
  191. 0x00000000,
  192. (0x9c00 << 16) | (0x8c08 >> 2),
  193. 0x00000000,
  194. (0x8000 << 16) | (0x9b7c >> 2),
  195. 0x00000000,
  196. (0x8040 << 16) | (0x9b7c >> 2),
  197. 0x00000000,
  198. (0x8000 << 16) | (0xe84 >> 2),
  199. 0x00000000,
  200. (0x8040 << 16) | (0xe84 >> 2),
  201. 0x00000000,
  202. (0x8000 << 16) | (0x89c0 >> 2),
  203. 0x00000000,
  204. (0x8040 << 16) | (0x89c0 >> 2),
  205. 0x00000000,
  206. (0x8000 << 16) | (0x914c >> 2),
  207. 0x00000000,
  208. (0x8040 << 16) | (0x914c >> 2),
  209. 0x00000000,
  210. (0x8000 << 16) | (0x8c20 >> 2),
  211. 0x00000000,
  212. (0x8040 << 16) | (0x8c20 >> 2),
  213. 0x00000000,
  214. (0x8000 << 16) | (0x9354 >> 2),
  215. 0x00000000,
  216. (0x8040 << 16) | (0x9354 >> 2),
  217. 0x00000000,
  218. (0x9c00 << 16) | (0x9060 >> 2),
  219. 0x00000000,
  220. (0x9c00 << 16) | (0x9364 >> 2),
  221. 0x00000000,
  222. (0x9c00 << 16) | (0x9100 >> 2),
  223. 0x00000000,
  224. (0x9c00 << 16) | (0x913c >> 2),
  225. 0x00000000,
  226. (0x8000 << 16) | (0x90e0 >> 2),
  227. 0x00000000,
  228. (0x8000 << 16) | (0x90e4 >> 2),
  229. 0x00000000,
  230. (0x8000 << 16) | (0x90e8 >> 2),
  231. 0x00000000,
  232. (0x8040 << 16) | (0x90e0 >> 2),
  233. 0x00000000,
  234. (0x8040 << 16) | (0x90e4 >> 2),
  235. 0x00000000,
  236. (0x8040 << 16) | (0x90e8 >> 2),
  237. 0x00000000,
  238. (0x9c00 << 16) | (0x8bcc >> 2),
  239. 0x00000000,
  240. (0x9c00 << 16) | (0x8b24 >> 2),
  241. 0x00000000,
  242. (0x9c00 << 16) | (0x88c4 >> 2),
  243. 0x00000000,
  244. (0x9c00 << 16) | (0x8e50 >> 2),
  245. 0x00000000,
  246. (0x9c00 << 16) | (0x8c0c >> 2),
  247. 0x00000000,
  248. (0x9c00 << 16) | (0x8e58 >> 2),
  249. 0x00000000,
  250. (0x9c00 << 16) | (0x8e5c >> 2),
  251. 0x00000000,
  252. (0x9c00 << 16) | (0x9508 >> 2),
  253. 0x00000000,
  254. (0x9c00 << 16) | (0x950c >> 2),
  255. 0x00000000,
  256. (0x9c00 << 16) | (0x9494 >> 2),
  257. 0x00000000,
  258. (0x9c00 << 16) | (0xac0c >> 2),
  259. 0x00000000,
  260. (0x9c00 << 16) | (0xac10 >> 2),
  261. 0x00000000,
  262. (0x9c00 << 16) | (0xac14 >> 2),
  263. 0x00000000,
  264. (0x9c00 << 16) | (0xae00 >> 2),
  265. 0x00000000,
  266. (0x9c00 << 16) | (0xac08 >> 2),
  267. 0x00000000,
  268. (0x9c00 << 16) | (0x88d4 >> 2),
  269. 0x00000000,
  270. (0x9c00 << 16) | (0x88c8 >> 2),
  271. 0x00000000,
  272. (0x9c00 << 16) | (0x88cc >> 2),
  273. 0x00000000,
  274. (0x9c00 << 16) | (0x89b0 >> 2),
  275. 0x00000000,
  276. (0x9c00 << 16) | (0x8b10 >> 2),
  277. 0x00000000,
  278. (0x9c00 << 16) | (0x8a14 >> 2),
  279. 0x00000000,
  280. (0x9c00 << 16) | (0x9830 >> 2),
  281. 0x00000000,
  282. (0x9c00 << 16) | (0x9834 >> 2),
  283. 0x00000000,
  284. (0x9c00 << 16) | (0x9838 >> 2),
  285. 0x00000000,
  286. (0x9c00 << 16) | (0x9a10 >> 2),
  287. 0x00000000,
  288. (0x8000 << 16) | (0x9870 >> 2),
  289. 0x00000000,
  290. (0x8000 << 16) | (0x9874 >> 2),
  291. 0x00000000,
  292. (0x8001 << 16) | (0x9870 >> 2),
  293. 0x00000000,
  294. (0x8001 << 16) | (0x9874 >> 2),
  295. 0x00000000,
  296. (0x8040 << 16) | (0x9870 >> 2),
  297. 0x00000000,
  298. (0x8040 << 16) | (0x9874 >> 2),
  299. 0x00000000,
  300. (0x8041 << 16) | (0x9870 >> 2),
  301. 0x00000000,
  302. (0x8041 << 16) | (0x9874 >> 2),
  303. 0x00000000,
  304. 0x00000000
  305. };
  306. static const u32 tahiti_golden_rlc_registers[] =
  307. {
  308. 0xc424, 0xffffffff, 0x00601005,
  309. 0xc47c, 0xffffffff, 0x10104040,
  310. 0xc488, 0xffffffff, 0x0100000a,
  311. 0xc314, 0xffffffff, 0x00000800,
  312. 0xc30c, 0xffffffff, 0x800000f4,
  313. 0xf4a8, 0xffffffff, 0x00000000
  314. };
  315. static const u32 tahiti_golden_registers[] =
  316. {
  317. 0x9a10, 0x00010000, 0x00018208,
  318. 0x9830, 0xffffffff, 0x00000000,
  319. 0x9834, 0xf00fffff, 0x00000400,
  320. 0x9838, 0x0002021c, 0x00020200,
  321. 0xc78, 0x00000080, 0x00000000,
  322. 0xd030, 0x000300c0, 0x00800040,
  323. 0xd830, 0x000300c0, 0x00800040,
  324. 0x5bb0, 0x000000f0, 0x00000070,
  325. 0x5bc0, 0x00200000, 0x50100000,
  326. 0x7030, 0x31000311, 0x00000011,
  327. 0x277c, 0x00000003, 0x000007ff,
  328. 0x240c, 0x000007ff, 0x00000000,
  329. 0x8a14, 0xf000001f, 0x00000007,
  330. 0x8b24, 0xffffffff, 0x00ffffff,
  331. 0x8b10, 0x0000ff0f, 0x00000000,
  332. 0x28a4c, 0x07ffffff, 0x4e000000,
  333. 0x28350, 0x3f3f3fff, 0x2a00126a,
  334. 0x30, 0x000000ff, 0x0040,
  335. 0x34, 0x00000040, 0x00004040,
  336. 0x9100, 0x07ffffff, 0x03000000,
  337. 0x8e88, 0x01ff1f3f, 0x00000000,
  338. 0x8e84, 0x01ff1f3f, 0x00000000,
  339. 0x9060, 0x0000007f, 0x00000020,
  340. 0x9508, 0x00010000, 0x00010000,
  341. 0xac14, 0x00000200, 0x000002fb,
  342. 0xac10, 0xffffffff, 0x0000543b,
  343. 0xac0c, 0xffffffff, 0xa9210876,
  344. 0x88d0, 0xffffffff, 0x000fff40,
  345. 0x88d4, 0x0000001f, 0x00000010,
  346. 0x1410, 0x20000000, 0x20fffed8,
  347. 0x15c0, 0x000c0fc0, 0x000c0400
  348. };
  349. static const u32 tahiti_golden_registers2[] =
  350. {
  351. 0xc64, 0x00000001, 0x00000001
  352. };
  353. static const u32 pitcairn_golden_rlc_registers[] =
  354. {
  355. 0xc424, 0xffffffff, 0x00601004,
  356. 0xc47c, 0xffffffff, 0x10102020,
  357. 0xc488, 0xffffffff, 0x01000020,
  358. 0xc314, 0xffffffff, 0x00000800,
  359. 0xc30c, 0xffffffff, 0x800000a4
  360. };
  361. static const u32 pitcairn_golden_registers[] =
  362. {
  363. 0x9a10, 0x00010000, 0x00018208,
  364. 0x9830, 0xffffffff, 0x00000000,
  365. 0x9834, 0xf00fffff, 0x00000400,
  366. 0x9838, 0x0002021c, 0x00020200,
  367. 0xc78, 0x00000080, 0x00000000,
  368. 0xd030, 0x000300c0, 0x00800040,
  369. 0xd830, 0x000300c0, 0x00800040,
  370. 0x5bb0, 0x000000f0, 0x00000070,
  371. 0x5bc0, 0x00200000, 0x50100000,
  372. 0x7030, 0x31000311, 0x00000011,
  373. 0x2ae4, 0x00073ffe, 0x000022a2,
  374. 0x240c, 0x000007ff, 0x00000000,
  375. 0x8a14, 0xf000001f, 0x00000007,
  376. 0x8b24, 0xffffffff, 0x00ffffff,
  377. 0x8b10, 0x0000ff0f, 0x00000000,
  378. 0x28a4c, 0x07ffffff, 0x4e000000,
  379. 0x28350, 0x3f3f3fff, 0x2a00126a,
  380. 0x30, 0x000000ff, 0x0040,
  381. 0x34, 0x00000040, 0x00004040,
  382. 0x9100, 0x07ffffff, 0x03000000,
  383. 0x9060, 0x0000007f, 0x00000020,
  384. 0x9508, 0x00010000, 0x00010000,
  385. 0xac14, 0x000003ff, 0x000000f7,
  386. 0xac10, 0xffffffff, 0x00000000,
  387. 0xac0c, 0xffffffff, 0x32761054,
  388. 0x88d4, 0x0000001f, 0x00000010,
  389. 0x15c0, 0x000c0fc0, 0x000c0400
  390. };
  391. static const u32 verde_golden_rlc_registers[] =
  392. {
  393. 0xc424, 0xffffffff, 0x033f1005,
  394. 0xc47c, 0xffffffff, 0x10808020,
  395. 0xc488, 0xffffffff, 0x00800008,
  396. 0xc314, 0xffffffff, 0x00001000,
  397. 0xc30c, 0xffffffff, 0x80010014
  398. };
  399. static const u32 verde_golden_registers[] =
  400. {
  401. 0x9a10, 0x00010000, 0x00018208,
  402. 0x9830, 0xffffffff, 0x00000000,
  403. 0x9834, 0xf00fffff, 0x00000400,
  404. 0x9838, 0x0002021c, 0x00020200,
  405. 0xc78, 0x00000080, 0x00000000,
  406. 0xd030, 0x000300c0, 0x00800040,
  407. 0xd030, 0x000300c0, 0x00800040,
  408. 0xd830, 0x000300c0, 0x00800040,
  409. 0xd830, 0x000300c0, 0x00800040,
  410. 0x5bb0, 0x000000f0, 0x00000070,
  411. 0x5bc0, 0x00200000, 0x50100000,
  412. 0x7030, 0x31000311, 0x00000011,
  413. 0x2ae4, 0x00073ffe, 0x000022a2,
  414. 0x2ae4, 0x00073ffe, 0x000022a2,
  415. 0x2ae4, 0x00073ffe, 0x000022a2,
  416. 0x240c, 0x000007ff, 0x00000000,
  417. 0x240c, 0x000007ff, 0x00000000,
  418. 0x240c, 0x000007ff, 0x00000000,
  419. 0x8a14, 0xf000001f, 0x00000007,
  420. 0x8a14, 0xf000001f, 0x00000007,
  421. 0x8a14, 0xf000001f, 0x00000007,
  422. 0x8b24, 0xffffffff, 0x00ffffff,
  423. 0x8b10, 0x0000ff0f, 0x00000000,
  424. 0x28a4c, 0x07ffffff, 0x4e000000,
  425. 0x28350, 0x3f3f3fff, 0x0000124a,
  426. 0x28350, 0x3f3f3fff, 0x0000124a,
  427. 0x28350, 0x3f3f3fff, 0x0000124a,
  428. 0x30, 0x000000ff, 0x0040,
  429. 0x34, 0x00000040, 0x00004040,
  430. 0x9100, 0x07ffffff, 0x03000000,
  431. 0x9100, 0x07ffffff, 0x03000000,
  432. 0x8e88, 0x01ff1f3f, 0x00000000,
  433. 0x8e88, 0x01ff1f3f, 0x00000000,
  434. 0x8e88, 0x01ff1f3f, 0x00000000,
  435. 0x8e84, 0x01ff1f3f, 0x00000000,
  436. 0x8e84, 0x01ff1f3f, 0x00000000,
  437. 0x8e84, 0x01ff1f3f, 0x00000000,
  438. 0x9060, 0x0000007f, 0x00000020,
  439. 0x9508, 0x00010000, 0x00010000,
  440. 0xac14, 0x000003ff, 0x00000003,
  441. 0xac14, 0x000003ff, 0x00000003,
  442. 0xac14, 0x000003ff, 0x00000003,
  443. 0xac10, 0xffffffff, 0x00000000,
  444. 0xac10, 0xffffffff, 0x00000000,
  445. 0xac10, 0xffffffff, 0x00000000,
  446. 0xac0c, 0xffffffff, 0x00001032,
  447. 0xac0c, 0xffffffff, 0x00001032,
  448. 0xac0c, 0xffffffff, 0x00001032,
  449. 0x88d4, 0x0000001f, 0x00000010,
  450. 0x88d4, 0x0000001f, 0x00000010,
  451. 0x88d4, 0x0000001f, 0x00000010,
  452. 0x15c0, 0x000c0fc0, 0x000c0400
  453. };
  454. static const u32 oland_golden_rlc_registers[] =
  455. {
  456. 0xc424, 0xffffffff, 0x00601005,
  457. 0xc47c, 0xffffffff, 0x10104040,
  458. 0xc488, 0xffffffff, 0x0100000a,
  459. 0xc314, 0xffffffff, 0x00000800,
  460. 0xc30c, 0xffffffff, 0x800000f4
  461. };
  462. static const u32 oland_golden_registers[] =
  463. {
  464. 0x9a10, 0x00010000, 0x00018208,
  465. 0x9830, 0xffffffff, 0x00000000,
  466. 0x9834, 0xf00fffff, 0x00000400,
  467. 0x9838, 0x0002021c, 0x00020200,
  468. 0xc78, 0x00000080, 0x00000000,
  469. 0xd030, 0x000300c0, 0x00800040,
  470. 0xd830, 0x000300c0, 0x00800040,
  471. 0x5bb0, 0x000000f0, 0x00000070,
  472. 0x5bc0, 0x00200000, 0x50100000,
  473. 0x7030, 0x31000311, 0x00000011,
  474. 0x2ae4, 0x00073ffe, 0x000022a2,
  475. 0x240c, 0x000007ff, 0x00000000,
  476. 0x8a14, 0xf000001f, 0x00000007,
  477. 0x8b24, 0xffffffff, 0x00ffffff,
  478. 0x8b10, 0x0000ff0f, 0x00000000,
  479. 0x28a4c, 0x07ffffff, 0x4e000000,
  480. 0x28350, 0x3f3f3fff, 0x00000082,
  481. 0x30, 0x000000ff, 0x0040,
  482. 0x34, 0x00000040, 0x00004040,
  483. 0x9100, 0x07ffffff, 0x03000000,
  484. 0x9060, 0x0000007f, 0x00000020,
  485. 0x9508, 0x00010000, 0x00010000,
  486. 0xac14, 0x000003ff, 0x000000f3,
  487. 0xac10, 0xffffffff, 0x00000000,
  488. 0xac0c, 0xffffffff, 0x00003210,
  489. 0x88d4, 0x0000001f, 0x00000010,
  490. 0x15c0, 0x000c0fc0, 0x000c0400
  491. };
  492. static const u32 hainan_golden_registers[] =
  493. {
  494. 0x9a10, 0x00010000, 0x00018208,
  495. 0x9830, 0xffffffff, 0x00000000,
  496. 0x9834, 0xf00fffff, 0x00000400,
  497. 0x9838, 0x0002021c, 0x00020200,
  498. 0xd0c0, 0xff000fff, 0x00000100,
  499. 0xd030, 0x000300c0, 0x00800040,
  500. 0xd8c0, 0xff000fff, 0x00000100,
  501. 0xd830, 0x000300c0, 0x00800040,
  502. 0x2ae4, 0x00073ffe, 0x000022a2,
  503. 0x240c, 0x000007ff, 0x00000000,
  504. 0x8a14, 0xf000001f, 0x00000007,
  505. 0x8b24, 0xffffffff, 0x00ffffff,
  506. 0x8b10, 0x0000ff0f, 0x00000000,
  507. 0x28a4c, 0x07ffffff, 0x4e000000,
  508. 0x28350, 0x3f3f3fff, 0x00000000,
  509. 0x30, 0x000000ff, 0x0040,
  510. 0x34, 0x00000040, 0x00004040,
  511. 0x9100, 0x03e00000, 0x03600000,
  512. 0x9060, 0x0000007f, 0x00000020,
  513. 0x9508, 0x00010000, 0x00010000,
  514. 0xac14, 0x000003ff, 0x000000f1,
  515. 0xac10, 0xffffffff, 0x00000000,
  516. 0xac0c, 0xffffffff, 0x00003210,
  517. 0x88d4, 0x0000001f, 0x00000010,
  518. 0x15c0, 0x000c0fc0, 0x000c0400
  519. };
  520. static const u32 hainan_golden_registers2[] =
  521. {
  522. 0x98f8, 0xffffffff, 0x02010001
  523. };
  524. static const u32 tahiti_mgcg_cgcg_init[] =
  525. {
  526. 0xc400, 0xffffffff, 0xfffffffc,
  527. 0x802c, 0xffffffff, 0xe0000000,
  528. 0x9a60, 0xffffffff, 0x00000100,
  529. 0x92a4, 0xffffffff, 0x00000100,
  530. 0xc164, 0xffffffff, 0x00000100,
  531. 0x9774, 0xffffffff, 0x00000100,
  532. 0x8984, 0xffffffff, 0x06000100,
  533. 0x8a18, 0xffffffff, 0x00000100,
  534. 0x92a0, 0xffffffff, 0x00000100,
  535. 0xc380, 0xffffffff, 0x00000100,
  536. 0x8b28, 0xffffffff, 0x00000100,
  537. 0x9144, 0xffffffff, 0x00000100,
  538. 0x8d88, 0xffffffff, 0x00000100,
  539. 0x8d8c, 0xffffffff, 0x00000100,
  540. 0x9030, 0xffffffff, 0x00000100,
  541. 0x9034, 0xffffffff, 0x00000100,
  542. 0x9038, 0xffffffff, 0x00000100,
  543. 0x903c, 0xffffffff, 0x00000100,
  544. 0xad80, 0xffffffff, 0x00000100,
  545. 0xac54, 0xffffffff, 0x00000100,
  546. 0x897c, 0xffffffff, 0x06000100,
  547. 0x9868, 0xffffffff, 0x00000100,
  548. 0x9510, 0xffffffff, 0x00000100,
  549. 0xaf04, 0xffffffff, 0x00000100,
  550. 0xae04, 0xffffffff, 0x00000100,
  551. 0x949c, 0xffffffff, 0x00000100,
  552. 0x802c, 0xffffffff, 0xe0000000,
  553. 0x9160, 0xffffffff, 0x00010000,
  554. 0x9164, 0xffffffff, 0x00030002,
  555. 0x9168, 0xffffffff, 0x00040007,
  556. 0x916c, 0xffffffff, 0x00060005,
  557. 0x9170, 0xffffffff, 0x00090008,
  558. 0x9174, 0xffffffff, 0x00020001,
  559. 0x9178, 0xffffffff, 0x00040003,
  560. 0x917c, 0xffffffff, 0x00000007,
  561. 0x9180, 0xffffffff, 0x00060005,
  562. 0x9184, 0xffffffff, 0x00090008,
  563. 0x9188, 0xffffffff, 0x00030002,
  564. 0x918c, 0xffffffff, 0x00050004,
  565. 0x9190, 0xffffffff, 0x00000008,
  566. 0x9194, 0xffffffff, 0x00070006,
  567. 0x9198, 0xffffffff, 0x000a0009,
  568. 0x919c, 0xffffffff, 0x00040003,
  569. 0x91a0, 0xffffffff, 0x00060005,
  570. 0x91a4, 0xffffffff, 0x00000009,
  571. 0x91a8, 0xffffffff, 0x00080007,
  572. 0x91ac, 0xffffffff, 0x000b000a,
  573. 0x91b0, 0xffffffff, 0x00050004,
  574. 0x91b4, 0xffffffff, 0x00070006,
  575. 0x91b8, 0xffffffff, 0x0008000b,
  576. 0x91bc, 0xffffffff, 0x000a0009,
  577. 0x91c0, 0xffffffff, 0x000d000c,
  578. 0x91c4, 0xffffffff, 0x00060005,
  579. 0x91c8, 0xffffffff, 0x00080007,
  580. 0x91cc, 0xffffffff, 0x0000000b,
  581. 0x91d0, 0xffffffff, 0x000a0009,
  582. 0x91d4, 0xffffffff, 0x000d000c,
  583. 0x91d8, 0xffffffff, 0x00070006,
  584. 0x91dc, 0xffffffff, 0x00090008,
  585. 0x91e0, 0xffffffff, 0x0000000c,
  586. 0x91e4, 0xffffffff, 0x000b000a,
  587. 0x91e8, 0xffffffff, 0x000e000d,
  588. 0x91ec, 0xffffffff, 0x00080007,
  589. 0x91f0, 0xffffffff, 0x000a0009,
  590. 0x91f4, 0xffffffff, 0x0000000d,
  591. 0x91f8, 0xffffffff, 0x000c000b,
  592. 0x91fc, 0xffffffff, 0x000f000e,
  593. 0x9200, 0xffffffff, 0x00090008,
  594. 0x9204, 0xffffffff, 0x000b000a,
  595. 0x9208, 0xffffffff, 0x000c000f,
  596. 0x920c, 0xffffffff, 0x000e000d,
  597. 0x9210, 0xffffffff, 0x00110010,
  598. 0x9214, 0xffffffff, 0x000a0009,
  599. 0x9218, 0xffffffff, 0x000c000b,
  600. 0x921c, 0xffffffff, 0x0000000f,
  601. 0x9220, 0xffffffff, 0x000e000d,
  602. 0x9224, 0xffffffff, 0x00110010,
  603. 0x9228, 0xffffffff, 0x000b000a,
  604. 0x922c, 0xffffffff, 0x000d000c,
  605. 0x9230, 0xffffffff, 0x00000010,
  606. 0x9234, 0xffffffff, 0x000f000e,
  607. 0x9238, 0xffffffff, 0x00120011,
  608. 0x923c, 0xffffffff, 0x000c000b,
  609. 0x9240, 0xffffffff, 0x000e000d,
  610. 0x9244, 0xffffffff, 0x00000011,
  611. 0x9248, 0xffffffff, 0x0010000f,
  612. 0x924c, 0xffffffff, 0x00130012,
  613. 0x9250, 0xffffffff, 0x000d000c,
  614. 0x9254, 0xffffffff, 0x000f000e,
  615. 0x9258, 0xffffffff, 0x00100013,
  616. 0x925c, 0xffffffff, 0x00120011,
  617. 0x9260, 0xffffffff, 0x00150014,
  618. 0x9264, 0xffffffff, 0x000e000d,
  619. 0x9268, 0xffffffff, 0x0010000f,
  620. 0x926c, 0xffffffff, 0x00000013,
  621. 0x9270, 0xffffffff, 0x00120011,
  622. 0x9274, 0xffffffff, 0x00150014,
  623. 0x9278, 0xffffffff, 0x000f000e,
  624. 0x927c, 0xffffffff, 0x00110010,
  625. 0x9280, 0xffffffff, 0x00000014,
  626. 0x9284, 0xffffffff, 0x00130012,
  627. 0x9288, 0xffffffff, 0x00160015,
  628. 0x928c, 0xffffffff, 0x0010000f,
  629. 0x9290, 0xffffffff, 0x00120011,
  630. 0x9294, 0xffffffff, 0x00000015,
  631. 0x9298, 0xffffffff, 0x00140013,
  632. 0x929c, 0xffffffff, 0x00170016,
  633. 0x9150, 0xffffffff, 0x96940200,
  634. 0x8708, 0xffffffff, 0x00900100,
  635. 0xc478, 0xffffffff, 0x00000080,
  636. 0xc404, 0xffffffff, 0x0020003f,
  637. 0x30, 0xffffffff, 0x0000001c,
  638. 0x34, 0x000f0000, 0x000f0000,
  639. 0x160c, 0xffffffff, 0x00000100,
  640. 0x1024, 0xffffffff, 0x00000100,
  641. 0x102c, 0x00000101, 0x00000000,
  642. 0x20a8, 0xffffffff, 0x00000104,
  643. 0x264c, 0x000c0000, 0x000c0000,
  644. 0x2648, 0x000c0000, 0x000c0000,
  645. 0x55e4, 0xff000fff, 0x00000100,
  646. 0x55e8, 0x00000001, 0x00000001,
  647. 0x2f50, 0x00000001, 0x00000001,
  648. 0x30cc, 0xc0000fff, 0x00000104,
  649. 0xc1e4, 0x00000001, 0x00000001,
  650. 0xd0c0, 0xfffffff0, 0x00000100,
  651. 0xd8c0, 0xfffffff0, 0x00000100
  652. };
  653. static const u32 pitcairn_mgcg_cgcg_init[] =
  654. {
  655. 0xc400, 0xffffffff, 0xfffffffc,
  656. 0x802c, 0xffffffff, 0xe0000000,
  657. 0x9a60, 0xffffffff, 0x00000100,
  658. 0x92a4, 0xffffffff, 0x00000100,
  659. 0xc164, 0xffffffff, 0x00000100,
  660. 0x9774, 0xffffffff, 0x00000100,
  661. 0x8984, 0xffffffff, 0x06000100,
  662. 0x8a18, 0xffffffff, 0x00000100,
  663. 0x92a0, 0xffffffff, 0x00000100,
  664. 0xc380, 0xffffffff, 0x00000100,
  665. 0x8b28, 0xffffffff, 0x00000100,
  666. 0x9144, 0xffffffff, 0x00000100,
  667. 0x8d88, 0xffffffff, 0x00000100,
  668. 0x8d8c, 0xffffffff, 0x00000100,
  669. 0x9030, 0xffffffff, 0x00000100,
  670. 0x9034, 0xffffffff, 0x00000100,
  671. 0x9038, 0xffffffff, 0x00000100,
  672. 0x903c, 0xffffffff, 0x00000100,
  673. 0xad80, 0xffffffff, 0x00000100,
  674. 0xac54, 0xffffffff, 0x00000100,
  675. 0x897c, 0xffffffff, 0x06000100,
  676. 0x9868, 0xffffffff, 0x00000100,
  677. 0x9510, 0xffffffff, 0x00000100,
  678. 0xaf04, 0xffffffff, 0x00000100,
  679. 0xae04, 0xffffffff, 0x00000100,
  680. 0x949c, 0xffffffff, 0x00000100,
  681. 0x802c, 0xffffffff, 0xe0000000,
  682. 0x9160, 0xffffffff, 0x00010000,
  683. 0x9164, 0xffffffff, 0x00030002,
  684. 0x9168, 0xffffffff, 0x00040007,
  685. 0x916c, 0xffffffff, 0x00060005,
  686. 0x9170, 0xffffffff, 0x00090008,
  687. 0x9174, 0xffffffff, 0x00020001,
  688. 0x9178, 0xffffffff, 0x00040003,
  689. 0x917c, 0xffffffff, 0x00000007,
  690. 0x9180, 0xffffffff, 0x00060005,
  691. 0x9184, 0xffffffff, 0x00090008,
  692. 0x9188, 0xffffffff, 0x00030002,
  693. 0x918c, 0xffffffff, 0x00050004,
  694. 0x9190, 0xffffffff, 0x00000008,
  695. 0x9194, 0xffffffff, 0x00070006,
  696. 0x9198, 0xffffffff, 0x000a0009,
  697. 0x919c, 0xffffffff, 0x00040003,
  698. 0x91a0, 0xffffffff, 0x00060005,
  699. 0x91a4, 0xffffffff, 0x00000009,
  700. 0x91a8, 0xffffffff, 0x00080007,
  701. 0x91ac, 0xffffffff, 0x000b000a,
  702. 0x91b0, 0xffffffff, 0x00050004,
  703. 0x91b4, 0xffffffff, 0x00070006,
  704. 0x91b8, 0xffffffff, 0x0008000b,
  705. 0x91bc, 0xffffffff, 0x000a0009,
  706. 0x91c0, 0xffffffff, 0x000d000c,
  707. 0x9200, 0xffffffff, 0x00090008,
  708. 0x9204, 0xffffffff, 0x000b000a,
  709. 0x9208, 0xffffffff, 0x000c000f,
  710. 0x920c, 0xffffffff, 0x000e000d,
  711. 0x9210, 0xffffffff, 0x00110010,
  712. 0x9214, 0xffffffff, 0x000a0009,
  713. 0x9218, 0xffffffff, 0x000c000b,
  714. 0x921c, 0xffffffff, 0x0000000f,
  715. 0x9220, 0xffffffff, 0x000e000d,
  716. 0x9224, 0xffffffff, 0x00110010,
  717. 0x9228, 0xffffffff, 0x000b000a,
  718. 0x922c, 0xffffffff, 0x000d000c,
  719. 0x9230, 0xffffffff, 0x00000010,
  720. 0x9234, 0xffffffff, 0x000f000e,
  721. 0x9238, 0xffffffff, 0x00120011,
  722. 0x923c, 0xffffffff, 0x000c000b,
  723. 0x9240, 0xffffffff, 0x000e000d,
  724. 0x9244, 0xffffffff, 0x00000011,
  725. 0x9248, 0xffffffff, 0x0010000f,
  726. 0x924c, 0xffffffff, 0x00130012,
  727. 0x9250, 0xffffffff, 0x000d000c,
  728. 0x9254, 0xffffffff, 0x000f000e,
  729. 0x9258, 0xffffffff, 0x00100013,
  730. 0x925c, 0xffffffff, 0x00120011,
  731. 0x9260, 0xffffffff, 0x00150014,
  732. 0x9150, 0xffffffff, 0x96940200,
  733. 0x8708, 0xffffffff, 0x00900100,
  734. 0xc478, 0xffffffff, 0x00000080,
  735. 0xc404, 0xffffffff, 0x0020003f,
  736. 0x30, 0xffffffff, 0x0000001c,
  737. 0x34, 0x000f0000, 0x000f0000,
  738. 0x160c, 0xffffffff, 0x00000100,
  739. 0x1024, 0xffffffff, 0x00000100,
  740. 0x102c, 0x00000101, 0x00000000,
  741. 0x20a8, 0xffffffff, 0x00000104,
  742. 0x55e4, 0xff000fff, 0x00000100,
  743. 0x55e8, 0x00000001, 0x00000001,
  744. 0x2f50, 0x00000001, 0x00000001,
  745. 0x30cc, 0xc0000fff, 0x00000104,
  746. 0xc1e4, 0x00000001, 0x00000001,
  747. 0xd0c0, 0xfffffff0, 0x00000100,
  748. 0xd8c0, 0xfffffff0, 0x00000100
  749. };
  750. static const u32 verde_mgcg_cgcg_init[] =
  751. {
  752. 0xc400, 0xffffffff, 0xfffffffc,
  753. 0x802c, 0xffffffff, 0xe0000000,
  754. 0x9a60, 0xffffffff, 0x00000100,
  755. 0x92a4, 0xffffffff, 0x00000100,
  756. 0xc164, 0xffffffff, 0x00000100,
  757. 0x9774, 0xffffffff, 0x00000100,
  758. 0x8984, 0xffffffff, 0x06000100,
  759. 0x8a18, 0xffffffff, 0x00000100,
  760. 0x92a0, 0xffffffff, 0x00000100,
  761. 0xc380, 0xffffffff, 0x00000100,
  762. 0x8b28, 0xffffffff, 0x00000100,
  763. 0x9144, 0xffffffff, 0x00000100,
  764. 0x8d88, 0xffffffff, 0x00000100,
  765. 0x8d8c, 0xffffffff, 0x00000100,
  766. 0x9030, 0xffffffff, 0x00000100,
  767. 0x9034, 0xffffffff, 0x00000100,
  768. 0x9038, 0xffffffff, 0x00000100,
  769. 0x903c, 0xffffffff, 0x00000100,
  770. 0xad80, 0xffffffff, 0x00000100,
  771. 0xac54, 0xffffffff, 0x00000100,
  772. 0x897c, 0xffffffff, 0x06000100,
  773. 0x9868, 0xffffffff, 0x00000100,
  774. 0x9510, 0xffffffff, 0x00000100,
  775. 0xaf04, 0xffffffff, 0x00000100,
  776. 0xae04, 0xffffffff, 0x00000100,
  777. 0x949c, 0xffffffff, 0x00000100,
  778. 0x802c, 0xffffffff, 0xe0000000,
  779. 0x9160, 0xffffffff, 0x00010000,
  780. 0x9164, 0xffffffff, 0x00030002,
  781. 0x9168, 0xffffffff, 0x00040007,
  782. 0x916c, 0xffffffff, 0x00060005,
  783. 0x9170, 0xffffffff, 0x00090008,
  784. 0x9174, 0xffffffff, 0x00020001,
  785. 0x9178, 0xffffffff, 0x00040003,
  786. 0x917c, 0xffffffff, 0x00000007,
  787. 0x9180, 0xffffffff, 0x00060005,
  788. 0x9184, 0xffffffff, 0x00090008,
  789. 0x9188, 0xffffffff, 0x00030002,
  790. 0x918c, 0xffffffff, 0x00050004,
  791. 0x9190, 0xffffffff, 0x00000008,
  792. 0x9194, 0xffffffff, 0x00070006,
  793. 0x9198, 0xffffffff, 0x000a0009,
  794. 0x919c, 0xffffffff, 0x00040003,
  795. 0x91a0, 0xffffffff, 0x00060005,
  796. 0x91a4, 0xffffffff, 0x00000009,
  797. 0x91a8, 0xffffffff, 0x00080007,
  798. 0x91ac, 0xffffffff, 0x000b000a,
  799. 0x91b0, 0xffffffff, 0x00050004,
  800. 0x91b4, 0xffffffff, 0x00070006,
  801. 0x91b8, 0xffffffff, 0x0008000b,
  802. 0x91bc, 0xffffffff, 0x000a0009,
  803. 0x91c0, 0xffffffff, 0x000d000c,
  804. 0x9200, 0xffffffff, 0x00090008,
  805. 0x9204, 0xffffffff, 0x000b000a,
  806. 0x9208, 0xffffffff, 0x000c000f,
  807. 0x920c, 0xffffffff, 0x000e000d,
  808. 0x9210, 0xffffffff, 0x00110010,
  809. 0x9214, 0xffffffff, 0x000a0009,
  810. 0x9218, 0xffffffff, 0x000c000b,
  811. 0x921c, 0xffffffff, 0x0000000f,
  812. 0x9220, 0xffffffff, 0x000e000d,
  813. 0x9224, 0xffffffff, 0x00110010,
  814. 0x9228, 0xffffffff, 0x000b000a,
  815. 0x922c, 0xffffffff, 0x000d000c,
  816. 0x9230, 0xffffffff, 0x00000010,
  817. 0x9234, 0xffffffff, 0x000f000e,
  818. 0x9238, 0xffffffff, 0x00120011,
  819. 0x923c, 0xffffffff, 0x000c000b,
  820. 0x9240, 0xffffffff, 0x000e000d,
  821. 0x9244, 0xffffffff, 0x00000011,
  822. 0x9248, 0xffffffff, 0x0010000f,
  823. 0x924c, 0xffffffff, 0x00130012,
  824. 0x9250, 0xffffffff, 0x000d000c,
  825. 0x9254, 0xffffffff, 0x000f000e,
  826. 0x9258, 0xffffffff, 0x00100013,
  827. 0x925c, 0xffffffff, 0x00120011,
  828. 0x9260, 0xffffffff, 0x00150014,
  829. 0x9150, 0xffffffff, 0x96940200,
  830. 0x8708, 0xffffffff, 0x00900100,
  831. 0xc478, 0xffffffff, 0x00000080,
  832. 0xc404, 0xffffffff, 0x0020003f,
  833. 0x30, 0xffffffff, 0x0000001c,
  834. 0x34, 0x000f0000, 0x000f0000,
  835. 0x160c, 0xffffffff, 0x00000100,
  836. 0x1024, 0xffffffff, 0x00000100,
  837. 0x102c, 0x00000101, 0x00000000,
  838. 0x20a8, 0xffffffff, 0x00000104,
  839. 0x264c, 0x000c0000, 0x000c0000,
  840. 0x2648, 0x000c0000, 0x000c0000,
  841. 0x55e4, 0xff000fff, 0x00000100,
  842. 0x55e8, 0x00000001, 0x00000001,
  843. 0x2f50, 0x00000001, 0x00000001,
  844. 0x30cc, 0xc0000fff, 0x00000104,
  845. 0xc1e4, 0x00000001, 0x00000001,
  846. 0xd0c0, 0xfffffff0, 0x00000100,
  847. 0xd8c0, 0xfffffff0, 0x00000100
  848. };
  849. static const u32 oland_mgcg_cgcg_init[] =
  850. {
  851. 0xc400, 0xffffffff, 0xfffffffc,
  852. 0x802c, 0xffffffff, 0xe0000000,
  853. 0x9a60, 0xffffffff, 0x00000100,
  854. 0x92a4, 0xffffffff, 0x00000100,
  855. 0xc164, 0xffffffff, 0x00000100,
  856. 0x9774, 0xffffffff, 0x00000100,
  857. 0x8984, 0xffffffff, 0x06000100,
  858. 0x8a18, 0xffffffff, 0x00000100,
  859. 0x92a0, 0xffffffff, 0x00000100,
  860. 0xc380, 0xffffffff, 0x00000100,
  861. 0x8b28, 0xffffffff, 0x00000100,
  862. 0x9144, 0xffffffff, 0x00000100,
  863. 0x8d88, 0xffffffff, 0x00000100,
  864. 0x8d8c, 0xffffffff, 0x00000100,
  865. 0x9030, 0xffffffff, 0x00000100,
  866. 0x9034, 0xffffffff, 0x00000100,
  867. 0x9038, 0xffffffff, 0x00000100,
  868. 0x903c, 0xffffffff, 0x00000100,
  869. 0xad80, 0xffffffff, 0x00000100,
  870. 0xac54, 0xffffffff, 0x00000100,
  871. 0x897c, 0xffffffff, 0x06000100,
  872. 0x9868, 0xffffffff, 0x00000100,
  873. 0x9510, 0xffffffff, 0x00000100,
  874. 0xaf04, 0xffffffff, 0x00000100,
  875. 0xae04, 0xffffffff, 0x00000100,
  876. 0x949c, 0xffffffff, 0x00000100,
  877. 0x802c, 0xffffffff, 0xe0000000,
  878. 0x9160, 0xffffffff, 0x00010000,
  879. 0x9164, 0xffffffff, 0x00030002,
  880. 0x9168, 0xffffffff, 0x00040007,
  881. 0x916c, 0xffffffff, 0x00060005,
  882. 0x9170, 0xffffffff, 0x00090008,
  883. 0x9174, 0xffffffff, 0x00020001,
  884. 0x9178, 0xffffffff, 0x00040003,
  885. 0x917c, 0xffffffff, 0x00000007,
  886. 0x9180, 0xffffffff, 0x00060005,
  887. 0x9184, 0xffffffff, 0x00090008,
  888. 0x9188, 0xffffffff, 0x00030002,
  889. 0x918c, 0xffffffff, 0x00050004,
  890. 0x9190, 0xffffffff, 0x00000008,
  891. 0x9194, 0xffffffff, 0x00070006,
  892. 0x9198, 0xffffffff, 0x000a0009,
  893. 0x919c, 0xffffffff, 0x00040003,
  894. 0x91a0, 0xffffffff, 0x00060005,
  895. 0x91a4, 0xffffffff, 0x00000009,
  896. 0x91a8, 0xffffffff, 0x00080007,
  897. 0x91ac, 0xffffffff, 0x000b000a,
  898. 0x91b0, 0xffffffff, 0x00050004,
  899. 0x91b4, 0xffffffff, 0x00070006,
  900. 0x91b8, 0xffffffff, 0x0008000b,
  901. 0x91bc, 0xffffffff, 0x000a0009,
  902. 0x91c0, 0xffffffff, 0x000d000c,
  903. 0x91c4, 0xffffffff, 0x00060005,
  904. 0x91c8, 0xffffffff, 0x00080007,
  905. 0x91cc, 0xffffffff, 0x0000000b,
  906. 0x91d0, 0xffffffff, 0x000a0009,
  907. 0x91d4, 0xffffffff, 0x000d000c,
  908. 0x9150, 0xffffffff, 0x96940200,
  909. 0x8708, 0xffffffff, 0x00900100,
  910. 0xc478, 0xffffffff, 0x00000080,
  911. 0xc404, 0xffffffff, 0x0020003f,
  912. 0x30, 0xffffffff, 0x0000001c,
  913. 0x34, 0x000f0000, 0x000f0000,
  914. 0x160c, 0xffffffff, 0x00000100,
  915. 0x1024, 0xffffffff, 0x00000100,
  916. 0x102c, 0x00000101, 0x00000000,
  917. 0x20a8, 0xffffffff, 0x00000104,
  918. 0x264c, 0x000c0000, 0x000c0000,
  919. 0x2648, 0x000c0000, 0x000c0000,
  920. 0x55e4, 0xff000fff, 0x00000100,
  921. 0x55e8, 0x00000001, 0x00000001,
  922. 0x2f50, 0x00000001, 0x00000001,
  923. 0x30cc, 0xc0000fff, 0x00000104,
  924. 0xc1e4, 0x00000001, 0x00000001,
  925. 0xd0c0, 0xfffffff0, 0x00000100,
  926. 0xd8c0, 0xfffffff0, 0x00000100
  927. };
  928. static const u32 hainan_mgcg_cgcg_init[] =
  929. {
  930. 0xc400, 0xffffffff, 0xfffffffc,
  931. 0x802c, 0xffffffff, 0xe0000000,
  932. 0x9a60, 0xffffffff, 0x00000100,
  933. 0x92a4, 0xffffffff, 0x00000100,
  934. 0xc164, 0xffffffff, 0x00000100,
  935. 0x9774, 0xffffffff, 0x00000100,
  936. 0x8984, 0xffffffff, 0x06000100,
  937. 0x8a18, 0xffffffff, 0x00000100,
  938. 0x92a0, 0xffffffff, 0x00000100,
  939. 0xc380, 0xffffffff, 0x00000100,
  940. 0x8b28, 0xffffffff, 0x00000100,
  941. 0x9144, 0xffffffff, 0x00000100,
  942. 0x8d88, 0xffffffff, 0x00000100,
  943. 0x8d8c, 0xffffffff, 0x00000100,
  944. 0x9030, 0xffffffff, 0x00000100,
  945. 0x9034, 0xffffffff, 0x00000100,
  946. 0x9038, 0xffffffff, 0x00000100,
  947. 0x903c, 0xffffffff, 0x00000100,
  948. 0xad80, 0xffffffff, 0x00000100,
  949. 0xac54, 0xffffffff, 0x00000100,
  950. 0x897c, 0xffffffff, 0x06000100,
  951. 0x9868, 0xffffffff, 0x00000100,
  952. 0x9510, 0xffffffff, 0x00000100,
  953. 0xaf04, 0xffffffff, 0x00000100,
  954. 0xae04, 0xffffffff, 0x00000100,
  955. 0x949c, 0xffffffff, 0x00000100,
  956. 0x802c, 0xffffffff, 0xe0000000,
  957. 0x9160, 0xffffffff, 0x00010000,
  958. 0x9164, 0xffffffff, 0x00030002,
  959. 0x9168, 0xffffffff, 0x00040007,
  960. 0x916c, 0xffffffff, 0x00060005,
  961. 0x9170, 0xffffffff, 0x00090008,
  962. 0x9174, 0xffffffff, 0x00020001,
  963. 0x9178, 0xffffffff, 0x00040003,
  964. 0x917c, 0xffffffff, 0x00000007,
  965. 0x9180, 0xffffffff, 0x00060005,
  966. 0x9184, 0xffffffff, 0x00090008,
  967. 0x9188, 0xffffffff, 0x00030002,
  968. 0x918c, 0xffffffff, 0x00050004,
  969. 0x9190, 0xffffffff, 0x00000008,
  970. 0x9194, 0xffffffff, 0x00070006,
  971. 0x9198, 0xffffffff, 0x000a0009,
  972. 0x919c, 0xffffffff, 0x00040003,
  973. 0x91a0, 0xffffffff, 0x00060005,
  974. 0x91a4, 0xffffffff, 0x00000009,
  975. 0x91a8, 0xffffffff, 0x00080007,
  976. 0x91ac, 0xffffffff, 0x000b000a,
  977. 0x91b0, 0xffffffff, 0x00050004,
  978. 0x91b4, 0xffffffff, 0x00070006,
  979. 0x91b8, 0xffffffff, 0x0008000b,
  980. 0x91bc, 0xffffffff, 0x000a0009,
  981. 0x91c0, 0xffffffff, 0x000d000c,
  982. 0x91c4, 0xffffffff, 0x00060005,
  983. 0x91c8, 0xffffffff, 0x00080007,
  984. 0x91cc, 0xffffffff, 0x0000000b,
  985. 0x91d0, 0xffffffff, 0x000a0009,
  986. 0x91d4, 0xffffffff, 0x000d000c,
  987. 0x9150, 0xffffffff, 0x96940200,
  988. 0x8708, 0xffffffff, 0x00900100,
  989. 0xc478, 0xffffffff, 0x00000080,
  990. 0xc404, 0xffffffff, 0x0020003f,
  991. 0x30, 0xffffffff, 0x0000001c,
  992. 0x34, 0x000f0000, 0x000f0000,
  993. 0x160c, 0xffffffff, 0x00000100,
  994. 0x1024, 0xffffffff, 0x00000100,
  995. 0x20a8, 0xffffffff, 0x00000104,
  996. 0x264c, 0x000c0000, 0x000c0000,
  997. 0x2648, 0x000c0000, 0x000c0000,
  998. 0x2f50, 0x00000001, 0x00000001,
  999. 0x30cc, 0xc0000fff, 0x00000104,
  1000. 0xc1e4, 0x00000001, 0x00000001,
  1001. 0xd0c0, 0xfffffff0, 0x00000100,
  1002. 0xd8c0, 0xfffffff0, 0x00000100
  1003. };
  1004. static u32 verde_pg_init[] =
  1005. {
  1006. 0x353c, 0xffffffff, 0x40000,
  1007. 0x3538, 0xffffffff, 0x200010ff,
  1008. 0x353c, 0xffffffff, 0x0,
  1009. 0x353c, 0xffffffff, 0x0,
  1010. 0x353c, 0xffffffff, 0x0,
  1011. 0x353c, 0xffffffff, 0x0,
  1012. 0x353c, 0xffffffff, 0x0,
  1013. 0x353c, 0xffffffff, 0x7007,
  1014. 0x3538, 0xffffffff, 0x300010ff,
  1015. 0x353c, 0xffffffff, 0x0,
  1016. 0x353c, 0xffffffff, 0x0,
  1017. 0x353c, 0xffffffff, 0x0,
  1018. 0x353c, 0xffffffff, 0x0,
  1019. 0x353c, 0xffffffff, 0x0,
  1020. 0x353c, 0xffffffff, 0x400000,
  1021. 0x3538, 0xffffffff, 0x100010ff,
  1022. 0x353c, 0xffffffff, 0x0,
  1023. 0x353c, 0xffffffff, 0x0,
  1024. 0x353c, 0xffffffff, 0x0,
  1025. 0x353c, 0xffffffff, 0x0,
  1026. 0x353c, 0xffffffff, 0x0,
  1027. 0x353c, 0xffffffff, 0x120200,
  1028. 0x3538, 0xffffffff, 0x500010ff,
  1029. 0x353c, 0xffffffff, 0x0,
  1030. 0x353c, 0xffffffff, 0x0,
  1031. 0x353c, 0xffffffff, 0x0,
  1032. 0x353c, 0xffffffff, 0x0,
  1033. 0x353c, 0xffffffff, 0x0,
  1034. 0x353c, 0xffffffff, 0x1e1e16,
  1035. 0x3538, 0xffffffff, 0x600010ff,
  1036. 0x353c, 0xffffffff, 0x0,
  1037. 0x353c, 0xffffffff, 0x0,
  1038. 0x353c, 0xffffffff, 0x0,
  1039. 0x353c, 0xffffffff, 0x0,
  1040. 0x353c, 0xffffffff, 0x0,
  1041. 0x353c, 0xffffffff, 0x171f1e,
  1042. 0x3538, 0xffffffff, 0x700010ff,
  1043. 0x353c, 0xffffffff, 0x0,
  1044. 0x353c, 0xffffffff, 0x0,
  1045. 0x353c, 0xffffffff, 0x0,
  1046. 0x353c, 0xffffffff, 0x0,
  1047. 0x353c, 0xffffffff, 0x0,
  1048. 0x353c, 0xffffffff, 0x0,
  1049. 0x3538, 0xffffffff, 0x9ff,
  1050. 0x3500, 0xffffffff, 0x0,
  1051. 0x3504, 0xffffffff, 0x10000800,
  1052. 0x3504, 0xffffffff, 0xf,
  1053. 0x3504, 0xffffffff, 0xf,
  1054. 0x3500, 0xffffffff, 0x4,
  1055. 0x3504, 0xffffffff, 0x1000051e,
  1056. 0x3504, 0xffffffff, 0xffff,
  1057. 0x3504, 0xffffffff, 0xffff,
  1058. 0x3500, 0xffffffff, 0x8,
  1059. 0x3504, 0xffffffff, 0x80500,
  1060. 0x3500, 0xffffffff, 0x12,
  1061. 0x3504, 0xffffffff, 0x9050c,
  1062. 0x3500, 0xffffffff, 0x1d,
  1063. 0x3504, 0xffffffff, 0xb052c,
  1064. 0x3500, 0xffffffff, 0x2a,
  1065. 0x3504, 0xffffffff, 0x1053e,
  1066. 0x3500, 0xffffffff, 0x2d,
  1067. 0x3504, 0xffffffff, 0x10546,
  1068. 0x3500, 0xffffffff, 0x30,
  1069. 0x3504, 0xffffffff, 0xa054e,
  1070. 0x3500, 0xffffffff, 0x3c,
  1071. 0x3504, 0xffffffff, 0x1055f,
  1072. 0x3500, 0xffffffff, 0x3f,
  1073. 0x3504, 0xffffffff, 0x10567,
  1074. 0x3500, 0xffffffff, 0x42,
  1075. 0x3504, 0xffffffff, 0x1056f,
  1076. 0x3500, 0xffffffff, 0x45,
  1077. 0x3504, 0xffffffff, 0x10572,
  1078. 0x3500, 0xffffffff, 0x48,
  1079. 0x3504, 0xffffffff, 0x20575,
  1080. 0x3500, 0xffffffff, 0x4c,
  1081. 0x3504, 0xffffffff, 0x190801,
  1082. 0x3500, 0xffffffff, 0x67,
  1083. 0x3504, 0xffffffff, 0x1082a,
  1084. 0x3500, 0xffffffff, 0x6a,
  1085. 0x3504, 0xffffffff, 0x1b082d,
  1086. 0x3500, 0xffffffff, 0x87,
  1087. 0x3504, 0xffffffff, 0x310851,
  1088. 0x3500, 0xffffffff, 0xba,
  1089. 0x3504, 0xffffffff, 0x891,
  1090. 0x3500, 0xffffffff, 0xbc,
  1091. 0x3504, 0xffffffff, 0x893,
  1092. 0x3500, 0xffffffff, 0xbe,
  1093. 0x3504, 0xffffffff, 0x20895,
  1094. 0x3500, 0xffffffff, 0xc2,
  1095. 0x3504, 0xffffffff, 0x20899,
  1096. 0x3500, 0xffffffff, 0xc6,
  1097. 0x3504, 0xffffffff, 0x2089d,
  1098. 0x3500, 0xffffffff, 0xca,
  1099. 0x3504, 0xffffffff, 0x8a1,
  1100. 0x3500, 0xffffffff, 0xcc,
  1101. 0x3504, 0xffffffff, 0x8a3,
  1102. 0x3500, 0xffffffff, 0xce,
  1103. 0x3504, 0xffffffff, 0x308a5,
  1104. 0x3500, 0xffffffff, 0xd3,
  1105. 0x3504, 0xffffffff, 0x6d08cd,
  1106. 0x3500, 0xffffffff, 0x142,
  1107. 0x3504, 0xffffffff, 0x2000095a,
  1108. 0x3504, 0xffffffff, 0x1,
  1109. 0x3500, 0xffffffff, 0x144,
  1110. 0x3504, 0xffffffff, 0x301f095b,
  1111. 0x3500, 0xffffffff, 0x165,
  1112. 0x3504, 0xffffffff, 0xc094d,
  1113. 0x3500, 0xffffffff, 0x173,
  1114. 0x3504, 0xffffffff, 0xf096d,
  1115. 0x3500, 0xffffffff, 0x184,
  1116. 0x3504, 0xffffffff, 0x15097f,
  1117. 0x3500, 0xffffffff, 0x19b,
  1118. 0x3504, 0xffffffff, 0xc0998,
  1119. 0x3500, 0xffffffff, 0x1a9,
  1120. 0x3504, 0xffffffff, 0x409a7,
  1121. 0x3500, 0xffffffff, 0x1af,
  1122. 0x3504, 0xffffffff, 0xcdc,
  1123. 0x3500, 0xffffffff, 0x1b1,
  1124. 0x3504, 0xffffffff, 0x800,
  1125. 0x3508, 0xffffffff, 0x6c9b2000,
  1126. 0x3510, 0xfc00, 0x2000,
  1127. 0x3544, 0xffffffff, 0xfc0,
  1128. 0x28d4, 0x00000100, 0x100
  1129. };
  1130. static void si_init_golden_registers(struct radeon_device *rdev)
  1131. {
  1132. switch (rdev->family) {
  1133. case CHIP_TAHITI:
  1134. radeon_program_register_sequence(rdev,
  1135. tahiti_golden_registers,
  1136. (const u32)ARRAY_SIZE(tahiti_golden_registers));
  1137. radeon_program_register_sequence(rdev,
  1138. tahiti_golden_rlc_registers,
  1139. (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
  1140. radeon_program_register_sequence(rdev,
  1141. tahiti_mgcg_cgcg_init,
  1142. (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
  1143. radeon_program_register_sequence(rdev,
  1144. tahiti_golden_registers2,
  1145. (const u32)ARRAY_SIZE(tahiti_golden_registers2));
  1146. break;
  1147. case CHIP_PITCAIRN:
  1148. radeon_program_register_sequence(rdev,
  1149. pitcairn_golden_registers,
  1150. (const u32)ARRAY_SIZE(pitcairn_golden_registers));
  1151. radeon_program_register_sequence(rdev,
  1152. pitcairn_golden_rlc_registers,
  1153. (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
  1154. radeon_program_register_sequence(rdev,
  1155. pitcairn_mgcg_cgcg_init,
  1156. (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
  1157. break;
  1158. case CHIP_VERDE:
  1159. radeon_program_register_sequence(rdev,
  1160. verde_golden_registers,
  1161. (const u32)ARRAY_SIZE(verde_golden_registers));
  1162. radeon_program_register_sequence(rdev,
  1163. verde_golden_rlc_registers,
  1164. (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
  1165. radeon_program_register_sequence(rdev,
  1166. verde_mgcg_cgcg_init,
  1167. (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
  1168. radeon_program_register_sequence(rdev,
  1169. verde_pg_init,
  1170. (const u32)ARRAY_SIZE(verde_pg_init));
  1171. break;
  1172. case CHIP_OLAND:
  1173. radeon_program_register_sequence(rdev,
  1174. oland_golden_registers,
  1175. (const u32)ARRAY_SIZE(oland_golden_registers));
  1176. radeon_program_register_sequence(rdev,
  1177. oland_golden_rlc_registers,
  1178. (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
  1179. radeon_program_register_sequence(rdev,
  1180. oland_mgcg_cgcg_init,
  1181. (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
  1182. break;
  1183. case CHIP_HAINAN:
  1184. radeon_program_register_sequence(rdev,
  1185. hainan_golden_registers,
  1186. (const u32)ARRAY_SIZE(hainan_golden_registers));
  1187. radeon_program_register_sequence(rdev,
  1188. hainan_golden_registers2,
  1189. (const u32)ARRAY_SIZE(hainan_golden_registers2));
  1190. radeon_program_register_sequence(rdev,
  1191. hainan_mgcg_cgcg_init,
  1192. (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
  1193. break;
  1194. default:
  1195. break;
  1196. }
  1197. }
  1198. #define PCIE_BUS_CLK 10000
  1199. #define TCLK (PCIE_BUS_CLK / 10)
  1200. /**
  1201. * si_get_xclk - get the xclk
  1202. *
  1203. * @rdev: radeon_device pointer
  1204. *
  1205. * Returns the reference clock used by the gfx engine
  1206. * (SI).
  1207. */
  1208. u32 si_get_xclk(struct radeon_device *rdev)
  1209. {
  1210. u32 reference_clock = rdev->clock.spll.reference_freq;
  1211. u32 tmp;
  1212. tmp = RREG32(CG_CLKPIN_CNTL_2);
  1213. if (tmp & MUX_TCLK_TO_XCLK)
  1214. return TCLK;
  1215. tmp = RREG32(CG_CLKPIN_CNTL);
  1216. if (tmp & XTALIN_DIVIDE)
  1217. return reference_clock / 4;
  1218. return reference_clock;
  1219. }
  1220. /* get temperature in millidegrees */
  1221. int si_get_temp(struct radeon_device *rdev)
  1222. {
  1223. u32 temp;
  1224. int actual_temp = 0;
  1225. temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  1226. CTF_TEMP_SHIFT;
  1227. if (temp & 0x200)
  1228. actual_temp = 255;
  1229. else
  1230. actual_temp = temp & 0x1ff;
  1231. actual_temp = (actual_temp * 1000);
  1232. return actual_temp;
  1233. }
  1234. #define TAHITI_IO_MC_REGS_SIZE 36
  1235. static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1236. {0x0000006f, 0x03044000},
  1237. {0x00000070, 0x0480c018},
  1238. {0x00000071, 0x00000040},
  1239. {0x00000072, 0x01000000},
  1240. {0x00000074, 0x000000ff},
  1241. {0x00000075, 0x00143400},
  1242. {0x00000076, 0x08ec0800},
  1243. {0x00000077, 0x040000cc},
  1244. {0x00000079, 0x00000000},
  1245. {0x0000007a, 0x21000409},
  1246. {0x0000007c, 0x00000000},
  1247. {0x0000007d, 0xe8000000},
  1248. {0x0000007e, 0x044408a8},
  1249. {0x0000007f, 0x00000003},
  1250. {0x00000080, 0x00000000},
  1251. {0x00000081, 0x01000000},
  1252. {0x00000082, 0x02000000},
  1253. {0x00000083, 0x00000000},
  1254. {0x00000084, 0xe3f3e4f4},
  1255. {0x00000085, 0x00052024},
  1256. {0x00000087, 0x00000000},
  1257. {0x00000088, 0x66036603},
  1258. {0x00000089, 0x01000000},
  1259. {0x0000008b, 0x1c0a0000},
  1260. {0x0000008c, 0xff010000},
  1261. {0x0000008e, 0xffffefff},
  1262. {0x0000008f, 0xfff3efff},
  1263. {0x00000090, 0xfff3efbf},
  1264. {0x00000094, 0x00101101},
  1265. {0x00000095, 0x00000fff},
  1266. {0x00000096, 0x00116fff},
  1267. {0x00000097, 0x60010000},
  1268. {0x00000098, 0x10010000},
  1269. {0x00000099, 0x00006000},
  1270. {0x0000009a, 0x00001000},
  1271. {0x0000009f, 0x00a77400}
  1272. };
  1273. static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1274. {0x0000006f, 0x03044000},
  1275. {0x00000070, 0x0480c018},
  1276. {0x00000071, 0x00000040},
  1277. {0x00000072, 0x01000000},
  1278. {0x00000074, 0x000000ff},
  1279. {0x00000075, 0x00143400},
  1280. {0x00000076, 0x08ec0800},
  1281. {0x00000077, 0x040000cc},
  1282. {0x00000079, 0x00000000},
  1283. {0x0000007a, 0x21000409},
  1284. {0x0000007c, 0x00000000},
  1285. {0x0000007d, 0xe8000000},
  1286. {0x0000007e, 0x044408a8},
  1287. {0x0000007f, 0x00000003},
  1288. {0x00000080, 0x00000000},
  1289. {0x00000081, 0x01000000},
  1290. {0x00000082, 0x02000000},
  1291. {0x00000083, 0x00000000},
  1292. {0x00000084, 0xe3f3e4f4},
  1293. {0x00000085, 0x00052024},
  1294. {0x00000087, 0x00000000},
  1295. {0x00000088, 0x66036603},
  1296. {0x00000089, 0x01000000},
  1297. {0x0000008b, 0x1c0a0000},
  1298. {0x0000008c, 0xff010000},
  1299. {0x0000008e, 0xffffefff},
  1300. {0x0000008f, 0xfff3efff},
  1301. {0x00000090, 0xfff3efbf},
  1302. {0x00000094, 0x00101101},
  1303. {0x00000095, 0x00000fff},
  1304. {0x00000096, 0x00116fff},
  1305. {0x00000097, 0x60010000},
  1306. {0x00000098, 0x10010000},
  1307. {0x00000099, 0x00006000},
  1308. {0x0000009a, 0x00001000},
  1309. {0x0000009f, 0x00a47400}
  1310. };
  1311. static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1312. {0x0000006f, 0x03044000},
  1313. {0x00000070, 0x0480c018},
  1314. {0x00000071, 0x00000040},
  1315. {0x00000072, 0x01000000},
  1316. {0x00000074, 0x000000ff},
  1317. {0x00000075, 0x00143400},
  1318. {0x00000076, 0x08ec0800},
  1319. {0x00000077, 0x040000cc},
  1320. {0x00000079, 0x00000000},
  1321. {0x0000007a, 0x21000409},
  1322. {0x0000007c, 0x00000000},
  1323. {0x0000007d, 0xe8000000},
  1324. {0x0000007e, 0x044408a8},
  1325. {0x0000007f, 0x00000003},
  1326. {0x00000080, 0x00000000},
  1327. {0x00000081, 0x01000000},
  1328. {0x00000082, 0x02000000},
  1329. {0x00000083, 0x00000000},
  1330. {0x00000084, 0xe3f3e4f4},
  1331. {0x00000085, 0x00052024},
  1332. {0x00000087, 0x00000000},
  1333. {0x00000088, 0x66036603},
  1334. {0x00000089, 0x01000000},
  1335. {0x0000008b, 0x1c0a0000},
  1336. {0x0000008c, 0xff010000},
  1337. {0x0000008e, 0xffffefff},
  1338. {0x0000008f, 0xfff3efff},
  1339. {0x00000090, 0xfff3efbf},
  1340. {0x00000094, 0x00101101},
  1341. {0x00000095, 0x00000fff},
  1342. {0x00000096, 0x00116fff},
  1343. {0x00000097, 0x60010000},
  1344. {0x00000098, 0x10010000},
  1345. {0x00000099, 0x00006000},
  1346. {0x0000009a, 0x00001000},
  1347. {0x0000009f, 0x00a37400}
  1348. };
  1349. static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1350. {0x0000006f, 0x03044000},
  1351. {0x00000070, 0x0480c018},
  1352. {0x00000071, 0x00000040},
  1353. {0x00000072, 0x01000000},
  1354. {0x00000074, 0x000000ff},
  1355. {0x00000075, 0x00143400},
  1356. {0x00000076, 0x08ec0800},
  1357. {0x00000077, 0x040000cc},
  1358. {0x00000079, 0x00000000},
  1359. {0x0000007a, 0x21000409},
  1360. {0x0000007c, 0x00000000},
  1361. {0x0000007d, 0xe8000000},
  1362. {0x0000007e, 0x044408a8},
  1363. {0x0000007f, 0x00000003},
  1364. {0x00000080, 0x00000000},
  1365. {0x00000081, 0x01000000},
  1366. {0x00000082, 0x02000000},
  1367. {0x00000083, 0x00000000},
  1368. {0x00000084, 0xe3f3e4f4},
  1369. {0x00000085, 0x00052024},
  1370. {0x00000087, 0x00000000},
  1371. {0x00000088, 0x66036603},
  1372. {0x00000089, 0x01000000},
  1373. {0x0000008b, 0x1c0a0000},
  1374. {0x0000008c, 0xff010000},
  1375. {0x0000008e, 0xffffefff},
  1376. {0x0000008f, 0xfff3efff},
  1377. {0x00000090, 0xfff3efbf},
  1378. {0x00000094, 0x00101101},
  1379. {0x00000095, 0x00000fff},
  1380. {0x00000096, 0x00116fff},
  1381. {0x00000097, 0x60010000},
  1382. {0x00000098, 0x10010000},
  1383. {0x00000099, 0x00006000},
  1384. {0x0000009a, 0x00001000},
  1385. {0x0000009f, 0x00a17730}
  1386. };
  1387. static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1388. {0x0000006f, 0x03044000},
  1389. {0x00000070, 0x0480c018},
  1390. {0x00000071, 0x00000040},
  1391. {0x00000072, 0x01000000},
  1392. {0x00000074, 0x000000ff},
  1393. {0x00000075, 0x00143400},
  1394. {0x00000076, 0x08ec0800},
  1395. {0x00000077, 0x040000cc},
  1396. {0x00000079, 0x00000000},
  1397. {0x0000007a, 0x21000409},
  1398. {0x0000007c, 0x00000000},
  1399. {0x0000007d, 0xe8000000},
  1400. {0x0000007e, 0x044408a8},
  1401. {0x0000007f, 0x00000003},
  1402. {0x00000080, 0x00000000},
  1403. {0x00000081, 0x01000000},
  1404. {0x00000082, 0x02000000},
  1405. {0x00000083, 0x00000000},
  1406. {0x00000084, 0xe3f3e4f4},
  1407. {0x00000085, 0x00052024},
  1408. {0x00000087, 0x00000000},
  1409. {0x00000088, 0x66036603},
  1410. {0x00000089, 0x01000000},
  1411. {0x0000008b, 0x1c0a0000},
  1412. {0x0000008c, 0xff010000},
  1413. {0x0000008e, 0xffffefff},
  1414. {0x0000008f, 0xfff3efff},
  1415. {0x00000090, 0xfff3efbf},
  1416. {0x00000094, 0x00101101},
  1417. {0x00000095, 0x00000fff},
  1418. {0x00000096, 0x00116fff},
  1419. {0x00000097, 0x60010000},
  1420. {0x00000098, 0x10010000},
  1421. {0x00000099, 0x00006000},
  1422. {0x0000009a, 0x00001000},
  1423. {0x0000009f, 0x00a07730}
  1424. };
  1425. /* ucode loading */
  1426. static int si_mc_load_microcode(struct radeon_device *rdev)
  1427. {
  1428. const __be32 *fw_data;
  1429. u32 running, blackout = 0;
  1430. u32 *io_mc_regs;
  1431. int i, ucode_size, regs_size;
  1432. if (!rdev->mc_fw)
  1433. return -EINVAL;
  1434. switch (rdev->family) {
  1435. case CHIP_TAHITI:
  1436. io_mc_regs = (u32 *)&tahiti_io_mc_regs;
  1437. ucode_size = SI_MC_UCODE_SIZE;
  1438. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1439. break;
  1440. case CHIP_PITCAIRN:
  1441. io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
  1442. ucode_size = SI_MC_UCODE_SIZE;
  1443. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1444. break;
  1445. case CHIP_VERDE:
  1446. default:
  1447. io_mc_regs = (u32 *)&verde_io_mc_regs;
  1448. ucode_size = SI_MC_UCODE_SIZE;
  1449. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1450. break;
  1451. case CHIP_OLAND:
  1452. io_mc_regs = (u32 *)&oland_io_mc_regs;
  1453. ucode_size = OLAND_MC_UCODE_SIZE;
  1454. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1455. break;
  1456. case CHIP_HAINAN:
  1457. io_mc_regs = (u32 *)&hainan_io_mc_regs;
  1458. ucode_size = OLAND_MC_UCODE_SIZE;
  1459. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1460. break;
  1461. }
  1462. running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
  1463. if (running == 0) {
  1464. if (running) {
  1465. blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
  1466. WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
  1467. }
  1468. /* reset the engine and set to writable */
  1469. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  1470. WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
  1471. /* load mc io regs */
  1472. for (i = 0; i < regs_size; i++) {
  1473. WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
  1474. WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
  1475. }
  1476. /* load the MC ucode */
  1477. fw_data = (const __be32 *)rdev->mc_fw->data;
  1478. for (i = 0; i < ucode_size; i++)
  1479. WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
  1480. /* put the engine back into the active state */
  1481. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  1482. WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
  1483. WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
  1484. /* wait for training to complete */
  1485. for (i = 0; i < rdev->usec_timeout; i++) {
  1486. if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
  1487. break;
  1488. udelay(1);
  1489. }
  1490. for (i = 0; i < rdev->usec_timeout; i++) {
  1491. if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
  1492. break;
  1493. udelay(1);
  1494. }
  1495. if (running)
  1496. WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
  1497. }
  1498. return 0;
  1499. }
  1500. static int si_init_microcode(struct radeon_device *rdev)
  1501. {
  1502. const char *chip_name;
  1503. const char *rlc_chip_name;
  1504. size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
  1505. size_t smc_req_size;
  1506. char fw_name[30];
  1507. int err;
  1508. DRM_DEBUG("\n");
  1509. switch (rdev->family) {
  1510. case CHIP_TAHITI:
  1511. chip_name = "TAHITI";
  1512. rlc_chip_name = "TAHITI";
  1513. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1514. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1515. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1516. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1517. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1518. smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
  1519. break;
  1520. case CHIP_PITCAIRN:
  1521. chip_name = "PITCAIRN";
  1522. rlc_chip_name = "PITCAIRN";
  1523. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1524. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1525. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1526. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1527. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1528. smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
  1529. break;
  1530. case CHIP_VERDE:
  1531. chip_name = "VERDE";
  1532. rlc_chip_name = "VERDE";
  1533. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1534. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1535. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1536. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1537. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1538. smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
  1539. break;
  1540. case CHIP_OLAND:
  1541. chip_name = "OLAND";
  1542. rlc_chip_name = "OLAND";
  1543. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1544. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1545. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1546. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1547. mc_req_size = OLAND_MC_UCODE_SIZE * 4;
  1548. smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
  1549. break;
  1550. case CHIP_HAINAN:
  1551. chip_name = "HAINAN";
  1552. rlc_chip_name = "HAINAN";
  1553. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1554. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1555. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1556. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1557. mc_req_size = OLAND_MC_UCODE_SIZE * 4;
  1558. smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
  1559. break;
  1560. default: BUG();
  1561. }
  1562. DRM_INFO("Loading %s Microcode\n", chip_name);
  1563. snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
  1564. err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
  1565. if (err)
  1566. goto out;
  1567. if (rdev->pfp_fw->size != pfp_req_size) {
  1568. printk(KERN_ERR
  1569. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1570. rdev->pfp_fw->size, fw_name);
  1571. err = -EINVAL;
  1572. goto out;
  1573. }
  1574. snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
  1575. err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
  1576. if (err)
  1577. goto out;
  1578. if (rdev->me_fw->size != me_req_size) {
  1579. printk(KERN_ERR
  1580. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1581. rdev->me_fw->size, fw_name);
  1582. err = -EINVAL;
  1583. }
  1584. snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
  1585. err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
  1586. if (err)
  1587. goto out;
  1588. if (rdev->ce_fw->size != ce_req_size) {
  1589. printk(KERN_ERR
  1590. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1591. rdev->ce_fw->size, fw_name);
  1592. err = -EINVAL;
  1593. }
  1594. snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
  1595. err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
  1596. if (err)
  1597. goto out;
  1598. if (rdev->rlc_fw->size != rlc_req_size) {
  1599. printk(KERN_ERR
  1600. "si_rlc: Bogus length %zu in firmware \"%s\"\n",
  1601. rdev->rlc_fw->size, fw_name);
  1602. err = -EINVAL;
  1603. }
  1604. snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
  1605. err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
  1606. if (err)
  1607. goto out;
  1608. if (rdev->mc_fw->size != mc_req_size) {
  1609. printk(KERN_ERR
  1610. "si_mc: Bogus length %zu in firmware \"%s\"\n",
  1611. rdev->mc_fw->size, fw_name);
  1612. err = -EINVAL;
  1613. }
  1614. snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
  1615. err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
  1616. if (err) {
  1617. printk(KERN_ERR
  1618. "smc: error loading firmware \"%s\"\n",
  1619. fw_name);
  1620. release_firmware(rdev->smc_fw);
  1621. rdev->smc_fw = NULL;
  1622. } else if (rdev->smc_fw->size != smc_req_size) {
  1623. printk(KERN_ERR
  1624. "si_smc: Bogus length %zu in firmware \"%s\"\n",
  1625. rdev->smc_fw->size, fw_name);
  1626. err = -EINVAL;
  1627. }
  1628. out:
  1629. if (err) {
  1630. if (err != -EINVAL)
  1631. printk(KERN_ERR
  1632. "si_cp: Failed to load firmware \"%s\"\n",
  1633. fw_name);
  1634. release_firmware(rdev->pfp_fw);
  1635. rdev->pfp_fw = NULL;
  1636. release_firmware(rdev->me_fw);
  1637. rdev->me_fw = NULL;
  1638. release_firmware(rdev->ce_fw);
  1639. rdev->ce_fw = NULL;
  1640. release_firmware(rdev->rlc_fw);
  1641. rdev->rlc_fw = NULL;
  1642. release_firmware(rdev->mc_fw);
  1643. rdev->mc_fw = NULL;
  1644. release_firmware(rdev->smc_fw);
  1645. rdev->smc_fw = NULL;
  1646. }
  1647. return err;
  1648. }
  1649. /* watermark setup */
  1650. static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
  1651. struct radeon_crtc *radeon_crtc,
  1652. struct drm_display_mode *mode,
  1653. struct drm_display_mode *other_mode)
  1654. {
  1655. u32 tmp, buffer_alloc, i;
  1656. u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
  1657. /*
  1658. * Line Buffer Setup
  1659. * There are 3 line buffers, each one shared by 2 display controllers.
  1660. * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
  1661. * the display controllers. The paritioning is done via one of four
  1662. * preset allocations specified in bits 21:20:
  1663. * 0 - half lb
  1664. * 2 - whole lb, other crtc must be disabled
  1665. */
  1666. /* this can get tricky if we have two large displays on a paired group
  1667. * of crtcs. Ideally for multiple large displays we'd assign them to
  1668. * non-linked crtcs for maximum line buffer allocation.
  1669. */
  1670. if (radeon_crtc->base.enabled && mode) {
  1671. if (other_mode) {
  1672. tmp = 0; /* 1/2 */
  1673. buffer_alloc = 1;
  1674. } else {
  1675. tmp = 2; /* whole */
  1676. buffer_alloc = 2;
  1677. }
  1678. } else {
  1679. tmp = 0;
  1680. buffer_alloc = 0;
  1681. }
  1682. WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
  1683. DC_LB_MEMORY_CONFIG(tmp));
  1684. WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
  1685. DMIF_BUFFERS_ALLOCATED(buffer_alloc));
  1686. for (i = 0; i < rdev->usec_timeout; i++) {
  1687. if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
  1688. DMIF_BUFFERS_ALLOCATED_COMPLETED)
  1689. break;
  1690. udelay(1);
  1691. }
  1692. if (radeon_crtc->base.enabled && mode) {
  1693. switch (tmp) {
  1694. case 0:
  1695. default:
  1696. return 4096 * 2;
  1697. case 2:
  1698. return 8192 * 2;
  1699. }
  1700. }
  1701. /* controller not enabled, so no lb used */
  1702. return 0;
  1703. }
  1704. static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
  1705. {
  1706. u32 tmp = RREG32(MC_SHARED_CHMAP);
  1707. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  1708. case 0:
  1709. default:
  1710. return 1;
  1711. case 1:
  1712. return 2;
  1713. case 2:
  1714. return 4;
  1715. case 3:
  1716. return 8;
  1717. case 4:
  1718. return 3;
  1719. case 5:
  1720. return 6;
  1721. case 6:
  1722. return 10;
  1723. case 7:
  1724. return 12;
  1725. case 8:
  1726. return 16;
  1727. }
  1728. }
  1729. struct dce6_wm_params {
  1730. u32 dram_channels; /* number of dram channels */
  1731. u32 yclk; /* bandwidth per dram data pin in kHz */
  1732. u32 sclk; /* engine clock in kHz */
  1733. u32 disp_clk; /* display clock in kHz */
  1734. u32 src_width; /* viewport width */
  1735. u32 active_time; /* active display time in ns */
  1736. u32 blank_time; /* blank time in ns */
  1737. bool interlaced; /* mode is interlaced */
  1738. fixed20_12 vsc; /* vertical scale ratio */
  1739. u32 num_heads; /* number of active crtcs */
  1740. u32 bytes_per_pixel; /* bytes per pixel display + overlay */
  1741. u32 lb_size; /* line buffer allocated to pipe */
  1742. u32 vtaps; /* vertical scaler taps */
  1743. };
  1744. static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
  1745. {
  1746. /* Calculate raw DRAM Bandwidth */
  1747. fixed20_12 dram_efficiency; /* 0.7 */
  1748. fixed20_12 yclk, dram_channels, bandwidth;
  1749. fixed20_12 a;
  1750. a.full = dfixed_const(1000);
  1751. yclk.full = dfixed_const(wm->yclk);
  1752. yclk.full = dfixed_div(yclk, a);
  1753. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  1754. a.full = dfixed_const(10);
  1755. dram_efficiency.full = dfixed_const(7);
  1756. dram_efficiency.full = dfixed_div(dram_efficiency, a);
  1757. bandwidth.full = dfixed_mul(dram_channels, yclk);
  1758. bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
  1759. return dfixed_trunc(bandwidth);
  1760. }
  1761. static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
  1762. {
  1763. /* Calculate DRAM Bandwidth and the part allocated to display. */
  1764. fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
  1765. fixed20_12 yclk, dram_channels, bandwidth;
  1766. fixed20_12 a;
  1767. a.full = dfixed_const(1000);
  1768. yclk.full = dfixed_const(wm->yclk);
  1769. yclk.full = dfixed_div(yclk, a);
  1770. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  1771. a.full = dfixed_const(10);
  1772. disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
  1773. disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
  1774. bandwidth.full = dfixed_mul(dram_channels, yclk);
  1775. bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
  1776. return dfixed_trunc(bandwidth);
  1777. }
  1778. static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
  1779. {
  1780. /* Calculate the display Data return Bandwidth */
  1781. fixed20_12 return_efficiency; /* 0.8 */
  1782. fixed20_12 sclk, bandwidth;
  1783. fixed20_12 a;
  1784. a.full = dfixed_const(1000);
  1785. sclk.full = dfixed_const(wm->sclk);
  1786. sclk.full = dfixed_div(sclk, a);
  1787. a.full = dfixed_const(10);
  1788. return_efficiency.full = dfixed_const(8);
  1789. return_efficiency.full = dfixed_div(return_efficiency, a);
  1790. a.full = dfixed_const(32);
  1791. bandwidth.full = dfixed_mul(a, sclk);
  1792. bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
  1793. return dfixed_trunc(bandwidth);
  1794. }
  1795. static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
  1796. {
  1797. return 32;
  1798. }
  1799. static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
  1800. {
  1801. /* Calculate the DMIF Request Bandwidth */
  1802. fixed20_12 disp_clk_request_efficiency; /* 0.8 */
  1803. fixed20_12 disp_clk, sclk, bandwidth;
  1804. fixed20_12 a, b1, b2;
  1805. u32 min_bandwidth;
  1806. a.full = dfixed_const(1000);
  1807. disp_clk.full = dfixed_const(wm->disp_clk);
  1808. disp_clk.full = dfixed_div(disp_clk, a);
  1809. a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
  1810. b1.full = dfixed_mul(a, disp_clk);
  1811. a.full = dfixed_const(1000);
  1812. sclk.full = dfixed_const(wm->sclk);
  1813. sclk.full = dfixed_div(sclk, a);
  1814. a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
  1815. b2.full = dfixed_mul(a, sclk);
  1816. a.full = dfixed_const(10);
  1817. disp_clk_request_efficiency.full = dfixed_const(8);
  1818. disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
  1819. min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
  1820. a.full = dfixed_const(min_bandwidth);
  1821. bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
  1822. return dfixed_trunc(bandwidth);
  1823. }
  1824. static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
  1825. {
  1826. /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
  1827. u32 dram_bandwidth = dce6_dram_bandwidth(wm);
  1828. u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
  1829. u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
  1830. return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
  1831. }
  1832. static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
  1833. {
  1834. /* Calculate the display mode Average Bandwidth
  1835. * DisplayMode should contain the source and destination dimensions,
  1836. * timing, etc.
  1837. */
  1838. fixed20_12 bpp;
  1839. fixed20_12 line_time;
  1840. fixed20_12 src_width;
  1841. fixed20_12 bandwidth;
  1842. fixed20_12 a;
  1843. a.full = dfixed_const(1000);
  1844. line_time.full = dfixed_const(wm->active_time + wm->blank_time);
  1845. line_time.full = dfixed_div(line_time, a);
  1846. bpp.full = dfixed_const(wm->bytes_per_pixel);
  1847. src_width.full = dfixed_const(wm->src_width);
  1848. bandwidth.full = dfixed_mul(src_width, bpp);
  1849. bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
  1850. bandwidth.full = dfixed_div(bandwidth, line_time);
  1851. return dfixed_trunc(bandwidth);
  1852. }
  1853. static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
  1854. {
  1855. /* First calcualte the latency in ns */
  1856. u32 mc_latency = 2000; /* 2000 ns. */
  1857. u32 available_bandwidth = dce6_available_bandwidth(wm);
  1858. u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
  1859. u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
  1860. u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
  1861. u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
  1862. (wm->num_heads * cursor_line_pair_return_time);
  1863. u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
  1864. u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
  1865. u32 tmp, dmif_size = 12288;
  1866. fixed20_12 a, b, c;
  1867. if (wm->num_heads == 0)
  1868. return 0;
  1869. a.full = dfixed_const(2);
  1870. b.full = dfixed_const(1);
  1871. if ((wm->vsc.full > a.full) ||
  1872. ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
  1873. (wm->vtaps >= 5) ||
  1874. ((wm->vsc.full >= a.full) && wm->interlaced))
  1875. max_src_lines_per_dst_line = 4;
  1876. else
  1877. max_src_lines_per_dst_line = 2;
  1878. a.full = dfixed_const(available_bandwidth);
  1879. b.full = dfixed_const(wm->num_heads);
  1880. a.full = dfixed_div(a, b);
  1881. b.full = dfixed_const(mc_latency + 512);
  1882. c.full = dfixed_const(wm->disp_clk);
  1883. b.full = dfixed_div(b, c);
  1884. c.full = dfixed_const(dmif_size);
  1885. b.full = dfixed_div(c, b);
  1886. tmp = min(dfixed_trunc(a), dfixed_trunc(b));
  1887. b.full = dfixed_const(1000);
  1888. c.full = dfixed_const(wm->disp_clk);
  1889. b.full = dfixed_div(c, b);
  1890. c.full = dfixed_const(wm->bytes_per_pixel);
  1891. b.full = dfixed_mul(b, c);
  1892. lb_fill_bw = min(tmp, dfixed_trunc(b));
  1893. a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
  1894. b.full = dfixed_const(1000);
  1895. c.full = dfixed_const(lb_fill_bw);
  1896. b.full = dfixed_div(c, b);
  1897. a.full = dfixed_div(a, b);
  1898. line_fill_time = dfixed_trunc(a);
  1899. if (line_fill_time < wm->active_time)
  1900. return latency;
  1901. else
  1902. return latency + (line_fill_time - wm->active_time);
  1903. }
  1904. static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
  1905. {
  1906. if (dce6_average_bandwidth(wm) <=
  1907. (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
  1908. return true;
  1909. else
  1910. return false;
  1911. };
  1912. static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
  1913. {
  1914. if (dce6_average_bandwidth(wm) <=
  1915. (dce6_available_bandwidth(wm) / wm->num_heads))
  1916. return true;
  1917. else
  1918. return false;
  1919. };
  1920. static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
  1921. {
  1922. u32 lb_partitions = wm->lb_size / wm->src_width;
  1923. u32 line_time = wm->active_time + wm->blank_time;
  1924. u32 latency_tolerant_lines;
  1925. u32 latency_hiding;
  1926. fixed20_12 a;
  1927. a.full = dfixed_const(1);
  1928. if (wm->vsc.full > a.full)
  1929. latency_tolerant_lines = 1;
  1930. else {
  1931. if (lb_partitions <= (wm->vtaps + 1))
  1932. latency_tolerant_lines = 1;
  1933. else
  1934. latency_tolerant_lines = 2;
  1935. }
  1936. latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
  1937. if (dce6_latency_watermark(wm) <= latency_hiding)
  1938. return true;
  1939. else
  1940. return false;
  1941. }
  1942. static void dce6_program_watermarks(struct radeon_device *rdev,
  1943. struct radeon_crtc *radeon_crtc,
  1944. u32 lb_size, u32 num_heads)
  1945. {
  1946. struct drm_display_mode *mode = &radeon_crtc->base.mode;
  1947. struct dce6_wm_params wm_low, wm_high;
  1948. u32 dram_channels;
  1949. u32 pixel_period;
  1950. u32 line_time = 0;
  1951. u32 latency_watermark_a = 0, latency_watermark_b = 0;
  1952. u32 priority_a_mark = 0, priority_b_mark = 0;
  1953. u32 priority_a_cnt = PRIORITY_OFF;
  1954. u32 priority_b_cnt = PRIORITY_OFF;
  1955. u32 tmp, arb_control3;
  1956. fixed20_12 a, b, c;
  1957. if (radeon_crtc->base.enabled && num_heads && mode) {
  1958. pixel_period = 1000000 / (u32)mode->clock;
  1959. line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
  1960. priority_a_cnt = 0;
  1961. priority_b_cnt = 0;
  1962. if (rdev->family == CHIP_ARUBA)
  1963. dram_channels = evergreen_get_number_of_dram_channels(rdev);
  1964. else
  1965. dram_channels = si_get_number_of_dram_channels(rdev);
  1966. /* watermark for high clocks */
  1967. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  1968. wm_high.yclk =
  1969. radeon_dpm_get_mclk(rdev, false) * 10;
  1970. wm_high.sclk =
  1971. radeon_dpm_get_sclk(rdev, false) * 10;
  1972. } else {
  1973. wm_high.yclk = rdev->pm.current_mclk * 10;
  1974. wm_high.sclk = rdev->pm.current_sclk * 10;
  1975. }
  1976. wm_high.disp_clk = mode->clock;
  1977. wm_high.src_width = mode->crtc_hdisplay;
  1978. wm_high.active_time = mode->crtc_hdisplay * pixel_period;
  1979. wm_high.blank_time = line_time - wm_high.active_time;
  1980. wm_high.interlaced = false;
  1981. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1982. wm_high.interlaced = true;
  1983. wm_high.vsc = radeon_crtc->vsc;
  1984. wm_high.vtaps = 1;
  1985. if (radeon_crtc->rmx_type != RMX_OFF)
  1986. wm_high.vtaps = 2;
  1987. wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
  1988. wm_high.lb_size = lb_size;
  1989. wm_high.dram_channels = dram_channels;
  1990. wm_high.num_heads = num_heads;
  1991. /* watermark for low clocks */
  1992. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  1993. wm_low.yclk =
  1994. radeon_dpm_get_mclk(rdev, true) * 10;
  1995. wm_low.sclk =
  1996. radeon_dpm_get_sclk(rdev, true) * 10;
  1997. } else {
  1998. wm_low.yclk = rdev->pm.current_mclk * 10;
  1999. wm_low.sclk = rdev->pm.current_sclk * 10;
  2000. }
  2001. wm_low.disp_clk = mode->clock;
  2002. wm_low.src_width = mode->crtc_hdisplay;
  2003. wm_low.active_time = mode->crtc_hdisplay * pixel_period;
  2004. wm_low.blank_time = line_time - wm_low.active_time;
  2005. wm_low.interlaced = false;
  2006. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  2007. wm_low.interlaced = true;
  2008. wm_low.vsc = radeon_crtc->vsc;
  2009. wm_low.vtaps = 1;
  2010. if (radeon_crtc->rmx_type != RMX_OFF)
  2011. wm_low.vtaps = 2;
  2012. wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
  2013. wm_low.lb_size = lb_size;
  2014. wm_low.dram_channels = dram_channels;
  2015. wm_low.num_heads = num_heads;
  2016. /* set for high clocks */
  2017. latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
  2018. /* set for low clocks */
  2019. latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
  2020. /* possibly force display priority to high */
  2021. /* should really do this at mode validation time... */
  2022. if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
  2023. !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
  2024. !dce6_check_latency_hiding(&wm_high) ||
  2025. (rdev->disp_priority == 2)) {
  2026. DRM_DEBUG_KMS("force priority to high\n");
  2027. priority_a_cnt |= PRIORITY_ALWAYS_ON;
  2028. priority_b_cnt |= PRIORITY_ALWAYS_ON;
  2029. }
  2030. if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
  2031. !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
  2032. !dce6_check_latency_hiding(&wm_low) ||
  2033. (rdev->disp_priority == 2)) {
  2034. DRM_DEBUG_KMS("force priority to high\n");
  2035. priority_a_cnt |= PRIORITY_ALWAYS_ON;
  2036. priority_b_cnt |= PRIORITY_ALWAYS_ON;
  2037. }
  2038. a.full = dfixed_const(1000);
  2039. b.full = dfixed_const(mode->clock);
  2040. b.full = dfixed_div(b, a);
  2041. c.full = dfixed_const(latency_watermark_a);
  2042. c.full = dfixed_mul(c, b);
  2043. c.full = dfixed_mul(c, radeon_crtc->hsc);
  2044. c.full = dfixed_div(c, a);
  2045. a.full = dfixed_const(16);
  2046. c.full = dfixed_div(c, a);
  2047. priority_a_mark = dfixed_trunc(c);
  2048. priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
  2049. a.full = dfixed_const(1000);
  2050. b.full = dfixed_const(mode->clock);
  2051. b.full = dfixed_div(b, a);
  2052. c.full = dfixed_const(latency_watermark_b);
  2053. c.full = dfixed_mul(c, b);
  2054. c.full = dfixed_mul(c, radeon_crtc->hsc);
  2055. c.full = dfixed_div(c, a);
  2056. a.full = dfixed_const(16);
  2057. c.full = dfixed_div(c, a);
  2058. priority_b_mark = dfixed_trunc(c);
  2059. priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
  2060. }
  2061. /* select wm A */
  2062. arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
  2063. tmp = arb_control3;
  2064. tmp &= ~LATENCY_WATERMARK_MASK(3);
  2065. tmp |= LATENCY_WATERMARK_MASK(1);
  2066. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
  2067. WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
  2068. (LATENCY_LOW_WATERMARK(latency_watermark_a) |
  2069. LATENCY_HIGH_WATERMARK(line_time)));
  2070. /* select wm B */
  2071. tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
  2072. tmp &= ~LATENCY_WATERMARK_MASK(3);
  2073. tmp |= LATENCY_WATERMARK_MASK(2);
  2074. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
  2075. WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
  2076. (LATENCY_LOW_WATERMARK(latency_watermark_b) |
  2077. LATENCY_HIGH_WATERMARK(line_time)));
  2078. /* restore original selection */
  2079. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
  2080. /* write the priority marks */
  2081. WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
  2082. WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
  2083. /* save values for DPM */
  2084. radeon_crtc->line_time = line_time;
  2085. radeon_crtc->wm_high = latency_watermark_a;
  2086. radeon_crtc->wm_low = latency_watermark_b;
  2087. }
  2088. void dce6_bandwidth_update(struct radeon_device *rdev)
  2089. {
  2090. struct drm_display_mode *mode0 = NULL;
  2091. struct drm_display_mode *mode1 = NULL;
  2092. u32 num_heads = 0, lb_size;
  2093. int i;
  2094. radeon_update_display_priority(rdev);
  2095. for (i = 0; i < rdev->num_crtc; i++) {
  2096. if (rdev->mode_info.crtcs[i]->base.enabled)
  2097. num_heads++;
  2098. }
  2099. for (i = 0; i < rdev->num_crtc; i += 2) {
  2100. mode0 = &rdev->mode_info.crtcs[i]->base.mode;
  2101. mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
  2102. lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
  2103. dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
  2104. lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
  2105. dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
  2106. }
  2107. }
  2108. /*
  2109. * Core functions
  2110. */
  2111. static void si_tiling_mode_table_init(struct radeon_device *rdev)
  2112. {
  2113. const u32 num_tile_mode_states = 32;
  2114. u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
  2115. switch (rdev->config.si.mem_row_size_in_kb) {
  2116. case 1:
  2117. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
  2118. break;
  2119. case 2:
  2120. default:
  2121. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
  2122. break;
  2123. case 4:
  2124. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
  2125. break;
  2126. }
  2127. if ((rdev->family == CHIP_TAHITI) ||
  2128. (rdev->family == CHIP_PITCAIRN)) {
  2129. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  2130. switch (reg_offset) {
  2131. case 0: /* non-AA compressed depth or any compressed stencil */
  2132. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2133. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2134. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2135. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2136. NUM_BANKS(ADDR_SURF_16_BANK) |
  2137. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2138. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2139. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2140. break;
  2141. case 1: /* 2xAA/4xAA compressed depth only */
  2142. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2143. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2144. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2145. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2146. NUM_BANKS(ADDR_SURF_16_BANK) |
  2147. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2148. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2149. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2150. break;
  2151. case 2: /* 8xAA compressed depth only */
  2152. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2153. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2154. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2155. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2156. NUM_BANKS(ADDR_SURF_16_BANK) |
  2157. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2158. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2159. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2160. break;
  2161. case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
  2162. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2163. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2164. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2165. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2166. NUM_BANKS(ADDR_SURF_16_BANK) |
  2167. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2168. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2169. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2170. break;
  2171. case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
  2172. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2173. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2174. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2175. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2176. NUM_BANKS(ADDR_SURF_16_BANK) |
  2177. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2178. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2179. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2180. break;
  2181. case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
  2182. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2183. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2184. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2185. TILE_SPLIT(split_equal_to_row_size) |
  2186. NUM_BANKS(ADDR_SURF_16_BANK) |
  2187. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2188. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2189. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2190. break;
  2191. case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
  2192. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2193. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2194. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2195. TILE_SPLIT(split_equal_to_row_size) |
  2196. NUM_BANKS(ADDR_SURF_16_BANK) |
  2197. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2198. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2199. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2200. break;
  2201. case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
  2202. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2203. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2204. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2205. TILE_SPLIT(split_equal_to_row_size) |
  2206. NUM_BANKS(ADDR_SURF_16_BANK) |
  2207. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2208. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2209. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2210. break;
  2211. case 8: /* 1D and 1D Array Surfaces */
  2212. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  2213. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2214. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2215. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2216. NUM_BANKS(ADDR_SURF_16_BANK) |
  2217. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2218. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2219. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2220. break;
  2221. case 9: /* Displayable maps. */
  2222. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2223. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2224. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2225. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2226. NUM_BANKS(ADDR_SURF_16_BANK) |
  2227. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2228. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2229. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2230. break;
  2231. case 10: /* Display 8bpp. */
  2232. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2233. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2234. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2235. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2236. NUM_BANKS(ADDR_SURF_16_BANK) |
  2237. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2238. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2239. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2240. break;
  2241. case 11: /* Display 16bpp. */
  2242. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2243. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2244. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2245. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2246. NUM_BANKS(ADDR_SURF_16_BANK) |
  2247. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2248. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2249. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2250. break;
  2251. case 12: /* Display 32bpp. */
  2252. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2253. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2254. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2255. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2256. NUM_BANKS(ADDR_SURF_16_BANK) |
  2257. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2258. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2259. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2260. break;
  2261. case 13: /* Thin. */
  2262. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2263. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2264. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2265. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2266. NUM_BANKS(ADDR_SURF_16_BANK) |
  2267. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2268. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2269. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2270. break;
  2271. case 14: /* Thin 8 bpp. */
  2272. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2273. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2274. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2275. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2276. NUM_BANKS(ADDR_SURF_16_BANK) |
  2277. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2278. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2279. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2280. break;
  2281. case 15: /* Thin 16 bpp. */
  2282. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2283. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2284. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2285. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2286. NUM_BANKS(ADDR_SURF_16_BANK) |
  2287. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2288. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2289. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2290. break;
  2291. case 16: /* Thin 32 bpp. */
  2292. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2293. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2294. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2295. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2296. NUM_BANKS(ADDR_SURF_16_BANK) |
  2297. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2298. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2299. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2300. break;
  2301. case 17: /* Thin 64 bpp. */
  2302. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2303. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2304. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2305. TILE_SPLIT(split_equal_to_row_size) |
  2306. NUM_BANKS(ADDR_SURF_16_BANK) |
  2307. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2308. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2309. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2310. break;
  2311. case 21: /* 8 bpp PRT. */
  2312. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2313. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2314. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2315. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2316. NUM_BANKS(ADDR_SURF_16_BANK) |
  2317. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  2318. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2319. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2320. break;
  2321. case 22: /* 16 bpp PRT */
  2322. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2323. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2324. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2325. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2326. NUM_BANKS(ADDR_SURF_16_BANK) |
  2327. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2328. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2329. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2330. break;
  2331. case 23: /* 32 bpp PRT */
  2332. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2333. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2334. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2335. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2336. NUM_BANKS(ADDR_SURF_16_BANK) |
  2337. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2338. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2339. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2340. break;
  2341. case 24: /* 64 bpp PRT */
  2342. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2343. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2344. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2345. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2346. NUM_BANKS(ADDR_SURF_16_BANK) |
  2347. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2348. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2349. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2350. break;
  2351. case 25: /* 128 bpp PRT */
  2352. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2353. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2354. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2355. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
  2356. NUM_BANKS(ADDR_SURF_8_BANK) |
  2357. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2358. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2359. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2360. break;
  2361. default:
  2362. gb_tile_moden = 0;
  2363. break;
  2364. }
  2365. rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
  2366. WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
  2367. }
  2368. } else if ((rdev->family == CHIP_VERDE) ||
  2369. (rdev->family == CHIP_OLAND) ||
  2370. (rdev->family == CHIP_HAINAN)) {
  2371. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  2372. switch (reg_offset) {
  2373. case 0: /* non-AA compressed depth or any compressed stencil */
  2374. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2375. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2376. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2377. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2378. NUM_BANKS(ADDR_SURF_16_BANK) |
  2379. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2380. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2381. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2382. break;
  2383. case 1: /* 2xAA/4xAA compressed depth only */
  2384. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2385. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2386. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2387. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2388. NUM_BANKS(ADDR_SURF_16_BANK) |
  2389. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2390. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2391. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2392. break;
  2393. case 2: /* 8xAA compressed depth only */
  2394. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2395. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2396. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2397. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2398. NUM_BANKS(ADDR_SURF_16_BANK) |
  2399. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2400. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2401. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2402. break;
  2403. case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
  2404. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2405. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2406. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2407. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2408. NUM_BANKS(ADDR_SURF_16_BANK) |
  2409. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2410. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2411. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2412. break;
  2413. case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
  2414. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2415. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2416. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2417. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2418. NUM_BANKS(ADDR_SURF_16_BANK) |
  2419. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2420. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2421. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2422. break;
  2423. case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
  2424. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2425. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2426. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2427. TILE_SPLIT(split_equal_to_row_size) |
  2428. NUM_BANKS(ADDR_SURF_16_BANK) |
  2429. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2430. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2431. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2432. break;
  2433. case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
  2434. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2435. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2436. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2437. TILE_SPLIT(split_equal_to_row_size) |
  2438. NUM_BANKS(ADDR_SURF_16_BANK) |
  2439. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2440. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2441. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2442. break;
  2443. case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
  2444. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2445. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2446. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2447. TILE_SPLIT(split_equal_to_row_size) |
  2448. NUM_BANKS(ADDR_SURF_16_BANK) |
  2449. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2450. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2451. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2452. break;
  2453. case 8: /* 1D and 1D Array Surfaces */
  2454. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  2455. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2456. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2457. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2458. NUM_BANKS(ADDR_SURF_16_BANK) |
  2459. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2460. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2461. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2462. break;
  2463. case 9: /* Displayable maps. */
  2464. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2465. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2466. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2467. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2468. NUM_BANKS(ADDR_SURF_16_BANK) |
  2469. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2470. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2471. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2472. break;
  2473. case 10: /* Display 8bpp. */
  2474. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2475. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2476. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2477. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2478. NUM_BANKS(ADDR_SURF_16_BANK) |
  2479. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2480. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2481. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2482. break;
  2483. case 11: /* Display 16bpp. */
  2484. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2485. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2486. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2487. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2488. NUM_BANKS(ADDR_SURF_16_BANK) |
  2489. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2490. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2491. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2492. break;
  2493. case 12: /* Display 32bpp. */
  2494. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2495. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2496. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2497. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2498. NUM_BANKS(ADDR_SURF_16_BANK) |
  2499. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2500. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2501. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2502. break;
  2503. case 13: /* Thin. */
  2504. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2505. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2506. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2507. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2508. NUM_BANKS(ADDR_SURF_16_BANK) |
  2509. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2510. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2511. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2512. break;
  2513. case 14: /* Thin 8 bpp. */
  2514. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2515. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2516. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2517. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2518. NUM_BANKS(ADDR_SURF_16_BANK) |
  2519. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2520. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2521. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2522. break;
  2523. case 15: /* Thin 16 bpp. */
  2524. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2525. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2526. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2527. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2528. NUM_BANKS(ADDR_SURF_16_BANK) |
  2529. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2530. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2531. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2532. break;
  2533. case 16: /* Thin 32 bpp. */
  2534. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2535. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2536. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2537. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2538. NUM_BANKS(ADDR_SURF_16_BANK) |
  2539. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2540. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2541. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2542. break;
  2543. case 17: /* Thin 64 bpp. */
  2544. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2545. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2546. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2547. TILE_SPLIT(split_equal_to_row_size) |
  2548. NUM_BANKS(ADDR_SURF_16_BANK) |
  2549. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2550. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2551. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2552. break;
  2553. case 21: /* 8 bpp PRT. */
  2554. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2555. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2556. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2557. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2558. NUM_BANKS(ADDR_SURF_16_BANK) |
  2559. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  2560. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2561. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2562. break;
  2563. case 22: /* 16 bpp PRT */
  2564. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2565. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2566. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2567. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2568. NUM_BANKS(ADDR_SURF_16_BANK) |
  2569. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2570. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2571. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2572. break;
  2573. case 23: /* 32 bpp PRT */
  2574. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2575. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2576. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2577. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2578. NUM_BANKS(ADDR_SURF_16_BANK) |
  2579. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2580. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2581. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2582. break;
  2583. case 24: /* 64 bpp PRT */
  2584. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2585. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2586. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2587. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2588. NUM_BANKS(ADDR_SURF_16_BANK) |
  2589. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2590. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2591. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2592. break;
  2593. case 25: /* 128 bpp PRT */
  2594. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2595. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2596. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2597. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
  2598. NUM_BANKS(ADDR_SURF_8_BANK) |
  2599. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2600. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2601. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2602. break;
  2603. default:
  2604. gb_tile_moden = 0;
  2605. break;
  2606. }
  2607. rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
  2608. WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
  2609. }
  2610. } else
  2611. DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
  2612. }
  2613. static void si_select_se_sh(struct radeon_device *rdev,
  2614. u32 se_num, u32 sh_num)
  2615. {
  2616. u32 data = INSTANCE_BROADCAST_WRITES;
  2617. if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
  2618. data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
  2619. else if (se_num == 0xffffffff)
  2620. data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
  2621. else if (sh_num == 0xffffffff)
  2622. data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
  2623. else
  2624. data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
  2625. WREG32(GRBM_GFX_INDEX, data);
  2626. }
  2627. static u32 si_create_bitmask(u32 bit_width)
  2628. {
  2629. u32 i, mask = 0;
  2630. for (i = 0; i < bit_width; i++) {
  2631. mask <<= 1;
  2632. mask |= 1;
  2633. }
  2634. return mask;
  2635. }
  2636. static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
  2637. {
  2638. u32 data, mask;
  2639. data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
  2640. if (data & 1)
  2641. data &= INACTIVE_CUS_MASK;
  2642. else
  2643. data = 0;
  2644. data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
  2645. data >>= INACTIVE_CUS_SHIFT;
  2646. mask = si_create_bitmask(cu_per_sh);
  2647. return ~data & mask;
  2648. }
  2649. static void si_setup_spi(struct radeon_device *rdev,
  2650. u32 se_num, u32 sh_per_se,
  2651. u32 cu_per_sh)
  2652. {
  2653. int i, j, k;
  2654. u32 data, mask, active_cu;
  2655. for (i = 0; i < se_num; i++) {
  2656. for (j = 0; j < sh_per_se; j++) {
  2657. si_select_se_sh(rdev, i, j);
  2658. data = RREG32(SPI_STATIC_THREAD_MGMT_3);
  2659. active_cu = si_get_cu_enabled(rdev, cu_per_sh);
  2660. mask = 1;
  2661. for (k = 0; k < 16; k++) {
  2662. mask <<= k;
  2663. if (active_cu & mask) {
  2664. data &= ~mask;
  2665. WREG32(SPI_STATIC_THREAD_MGMT_3, data);
  2666. break;
  2667. }
  2668. }
  2669. }
  2670. }
  2671. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2672. }
  2673. static u32 si_get_rb_disabled(struct radeon_device *rdev,
  2674. u32 max_rb_num, u32 se_num,
  2675. u32 sh_per_se)
  2676. {
  2677. u32 data, mask;
  2678. data = RREG32(CC_RB_BACKEND_DISABLE);
  2679. if (data & 1)
  2680. data &= BACKEND_DISABLE_MASK;
  2681. else
  2682. data = 0;
  2683. data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
  2684. data >>= BACKEND_DISABLE_SHIFT;
  2685. mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
  2686. return data & mask;
  2687. }
  2688. static void si_setup_rb(struct radeon_device *rdev,
  2689. u32 se_num, u32 sh_per_se,
  2690. u32 max_rb_num)
  2691. {
  2692. int i, j;
  2693. u32 data, mask;
  2694. u32 disabled_rbs = 0;
  2695. u32 enabled_rbs = 0;
  2696. for (i = 0; i < se_num; i++) {
  2697. for (j = 0; j < sh_per_se; j++) {
  2698. si_select_se_sh(rdev, i, j);
  2699. data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
  2700. disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
  2701. }
  2702. }
  2703. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2704. mask = 1;
  2705. for (i = 0; i < max_rb_num; i++) {
  2706. if (!(disabled_rbs & mask))
  2707. enabled_rbs |= mask;
  2708. mask <<= 1;
  2709. }
  2710. for (i = 0; i < se_num; i++) {
  2711. si_select_se_sh(rdev, i, 0xffffffff);
  2712. data = 0;
  2713. for (j = 0; j < sh_per_se; j++) {
  2714. switch (enabled_rbs & 3) {
  2715. case 1:
  2716. data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
  2717. break;
  2718. case 2:
  2719. data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
  2720. break;
  2721. case 3:
  2722. default:
  2723. data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
  2724. break;
  2725. }
  2726. enabled_rbs >>= 2;
  2727. }
  2728. WREG32(PA_SC_RASTER_CONFIG, data);
  2729. }
  2730. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2731. }
  2732. static void si_gpu_init(struct radeon_device *rdev)
  2733. {
  2734. u32 gb_addr_config = 0;
  2735. u32 mc_shared_chmap, mc_arb_ramcfg;
  2736. u32 sx_debug_1;
  2737. u32 hdp_host_path_cntl;
  2738. u32 tmp;
  2739. int i, j;
  2740. switch (rdev->family) {
  2741. case CHIP_TAHITI:
  2742. rdev->config.si.max_shader_engines = 2;
  2743. rdev->config.si.max_tile_pipes = 12;
  2744. rdev->config.si.max_cu_per_sh = 8;
  2745. rdev->config.si.max_sh_per_se = 2;
  2746. rdev->config.si.max_backends_per_se = 4;
  2747. rdev->config.si.max_texture_channel_caches = 12;
  2748. rdev->config.si.max_gprs = 256;
  2749. rdev->config.si.max_gs_threads = 32;
  2750. rdev->config.si.max_hw_contexts = 8;
  2751. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2752. rdev->config.si.sc_prim_fifo_size_backend = 0x100;
  2753. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2754. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2755. gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
  2756. break;
  2757. case CHIP_PITCAIRN:
  2758. rdev->config.si.max_shader_engines = 2;
  2759. rdev->config.si.max_tile_pipes = 8;
  2760. rdev->config.si.max_cu_per_sh = 5;
  2761. rdev->config.si.max_sh_per_se = 2;
  2762. rdev->config.si.max_backends_per_se = 4;
  2763. rdev->config.si.max_texture_channel_caches = 8;
  2764. rdev->config.si.max_gprs = 256;
  2765. rdev->config.si.max_gs_threads = 32;
  2766. rdev->config.si.max_hw_contexts = 8;
  2767. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2768. rdev->config.si.sc_prim_fifo_size_backend = 0x100;
  2769. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2770. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2771. gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
  2772. break;
  2773. case CHIP_VERDE:
  2774. default:
  2775. rdev->config.si.max_shader_engines = 1;
  2776. rdev->config.si.max_tile_pipes = 4;
  2777. rdev->config.si.max_cu_per_sh = 5;
  2778. rdev->config.si.max_sh_per_se = 2;
  2779. rdev->config.si.max_backends_per_se = 4;
  2780. rdev->config.si.max_texture_channel_caches = 4;
  2781. rdev->config.si.max_gprs = 256;
  2782. rdev->config.si.max_gs_threads = 32;
  2783. rdev->config.si.max_hw_contexts = 8;
  2784. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2785. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2786. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2787. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2788. gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
  2789. break;
  2790. case CHIP_OLAND:
  2791. rdev->config.si.max_shader_engines = 1;
  2792. rdev->config.si.max_tile_pipes = 4;
  2793. rdev->config.si.max_cu_per_sh = 6;
  2794. rdev->config.si.max_sh_per_se = 1;
  2795. rdev->config.si.max_backends_per_se = 2;
  2796. rdev->config.si.max_texture_channel_caches = 4;
  2797. rdev->config.si.max_gprs = 256;
  2798. rdev->config.si.max_gs_threads = 16;
  2799. rdev->config.si.max_hw_contexts = 8;
  2800. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2801. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2802. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2803. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2804. gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
  2805. break;
  2806. case CHIP_HAINAN:
  2807. rdev->config.si.max_shader_engines = 1;
  2808. rdev->config.si.max_tile_pipes = 4;
  2809. rdev->config.si.max_cu_per_sh = 5;
  2810. rdev->config.si.max_sh_per_se = 1;
  2811. rdev->config.si.max_backends_per_se = 1;
  2812. rdev->config.si.max_texture_channel_caches = 2;
  2813. rdev->config.si.max_gprs = 256;
  2814. rdev->config.si.max_gs_threads = 16;
  2815. rdev->config.si.max_hw_contexts = 8;
  2816. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2817. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2818. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2819. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2820. gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
  2821. break;
  2822. }
  2823. /* Initialize HDP */
  2824. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  2825. WREG32((0x2c14 + j), 0x00000000);
  2826. WREG32((0x2c18 + j), 0x00000000);
  2827. WREG32((0x2c1c + j), 0x00000000);
  2828. WREG32((0x2c20 + j), 0x00000000);
  2829. WREG32((0x2c24 + j), 0x00000000);
  2830. }
  2831. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  2832. evergreen_fix_pci_max_read_req_size(rdev);
  2833. WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
  2834. mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
  2835. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  2836. rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
  2837. rdev->config.si.mem_max_burst_length_bytes = 256;
  2838. tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
  2839. rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
  2840. if (rdev->config.si.mem_row_size_in_kb > 4)
  2841. rdev->config.si.mem_row_size_in_kb = 4;
  2842. /* XXX use MC settings? */
  2843. rdev->config.si.shader_engine_tile_size = 32;
  2844. rdev->config.si.num_gpus = 1;
  2845. rdev->config.si.multi_gpu_tile_size = 64;
  2846. /* fix up row size */
  2847. gb_addr_config &= ~ROW_SIZE_MASK;
  2848. switch (rdev->config.si.mem_row_size_in_kb) {
  2849. case 1:
  2850. default:
  2851. gb_addr_config |= ROW_SIZE(0);
  2852. break;
  2853. case 2:
  2854. gb_addr_config |= ROW_SIZE(1);
  2855. break;
  2856. case 4:
  2857. gb_addr_config |= ROW_SIZE(2);
  2858. break;
  2859. }
  2860. /* setup tiling info dword. gb_addr_config is not adequate since it does
  2861. * not have bank info, so create a custom tiling dword.
  2862. * bits 3:0 num_pipes
  2863. * bits 7:4 num_banks
  2864. * bits 11:8 group_size
  2865. * bits 15:12 row_size
  2866. */
  2867. rdev->config.si.tile_config = 0;
  2868. switch (rdev->config.si.num_tile_pipes) {
  2869. case 1:
  2870. rdev->config.si.tile_config |= (0 << 0);
  2871. break;
  2872. case 2:
  2873. rdev->config.si.tile_config |= (1 << 0);
  2874. break;
  2875. case 4:
  2876. rdev->config.si.tile_config |= (2 << 0);
  2877. break;
  2878. case 8:
  2879. default:
  2880. /* XXX what about 12? */
  2881. rdev->config.si.tile_config |= (3 << 0);
  2882. break;
  2883. }
  2884. switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
  2885. case 0: /* four banks */
  2886. rdev->config.si.tile_config |= 0 << 4;
  2887. break;
  2888. case 1: /* eight banks */
  2889. rdev->config.si.tile_config |= 1 << 4;
  2890. break;
  2891. case 2: /* sixteen banks */
  2892. default:
  2893. rdev->config.si.tile_config |= 2 << 4;
  2894. break;
  2895. }
  2896. rdev->config.si.tile_config |=
  2897. ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
  2898. rdev->config.si.tile_config |=
  2899. ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
  2900. WREG32(GB_ADDR_CONFIG, gb_addr_config);
  2901. WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
  2902. WREG32(DMIF_ADDR_CALC, gb_addr_config);
  2903. WREG32(HDP_ADDR_CONFIG, gb_addr_config);
  2904. WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
  2905. WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
  2906. if (rdev->has_uvd) {
  2907. WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
  2908. WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
  2909. WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
  2910. }
  2911. si_tiling_mode_table_init(rdev);
  2912. si_setup_rb(rdev, rdev->config.si.max_shader_engines,
  2913. rdev->config.si.max_sh_per_se,
  2914. rdev->config.si.max_backends_per_se);
  2915. si_setup_spi(rdev, rdev->config.si.max_shader_engines,
  2916. rdev->config.si.max_sh_per_se,
  2917. rdev->config.si.max_cu_per_sh);
  2918. /* set HW defaults for 3D engine */
  2919. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  2920. ROQ_IB2_START(0x2b)));
  2921. WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
  2922. sx_debug_1 = RREG32(SX_DEBUG_1);
  2923. WREG32(SX_DEBUG_1, sx_debug_1);
  2924. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  2925. WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
  2926. SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
  2927. SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
  2928. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
  2929. WREG32(VGT_NUM_INSTANCES, 1);
  2930. WREG32(CP_PERFMON_CNTL, 0);
  2931. WREG32(SQ_CONFIG, 0);
  2932. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  2933. FORCE_EOV_MAX_REZ_CNT(255)));
  2934. WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
  2935. AUTO_INVLD_EN(ES_AND_GS_AUTO));
  2936. WREG32(VGT_GS_VERTEX_REUSE, 16);
  2937. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  2938. WREG32(CB_PERFCOUNTER0_SELECT0, 0);
  2939. WREG32(CB_PERFCOUNTER0_SELECT1, 0);
  2940. WREG32(CB_PERFCOUNTER1_SELECT0, 0);
  2941. WREG32(CB_PERFCOUNTER1_SELECT1, 0);
  2942. WREG32(CB_PERFCOUNTER2_SELECT0, 0);
  2943. WREG32(CB_PERFCOUNTER2_SELECT1, 0);
  2944. WREG32(CB_PERFCOUNTER3_SELECT0, 0);
  2945. WREG32(CB_PERFCOUNTER3_SELECT1, 0);
  2946. tmp = RREG32(HDP_MISC_CNTL);
  2947. tmp |= HDP_FLUSH_INVALIDATE_CACHE;
  2948. WREG32(HDP_MISC_CNTL, tmp);
  2949. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  2950. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  2951. WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
  2952. udelay(50);
  2953. }
  2954. /*
  2955. * GPU scratch registers helpers function.
  2956. */
  2957. static void si_scratch_init(struct radeon_device *rdev)
  2958. {
  2959. int i;
  2960. rdev->scratch.num_reg = 7;
  2961. rdev->scratch.reg_base = SCRATCH_REG0;
  2962. for (i = 0; i < rdev->scratch.num_reg; i++) {
  2963. rdev->scratch.free[i] = true;
  2964. rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  2965. }
  2966. }
  2967. void si_fence_ring_emit(struct radeon_device *rdev,
  2968. struct radeon_fence *fence)
  2969. {
  2970. struct radeon_ring *ring = &rdev->ring[fence->ring];
  2971. u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
  2972. /* flush read cache over gart */
  2973. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2974. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  2975. radeon_ring_write(ring, 0);
  2976. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  2977. radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
  2978. PACKET3_TC_ACTION_ENA |
  2979. PACKET3_SH_KCACHE_ACTION_ENA |
  2980. PACKET3_SH_ICACHE_ACTION_ENA);
  2981. radeon_ring_write(ring, 0xFFFFFFFF);
  2982. radeon_ring_write(ring, 0);
  2983. radeon_ring_write(ring, 10); /* poll interval */
  2984. /* EVENT_WRITE_EOP - flush caches, send int */
  2985. radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
  2986. radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
  2987. radeon_ring_write(ring, addr & 0xffffffff);
  2988. radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
  2989. radeon_ring_write(ring, fence->seq);
  2990. radeon_ring_write(ring, 0);
  2991. }
  2992. /*
  2993. * IB stuff
  2994. */
  2995. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  2996. {
  2997. struct radeon_ring *ring = &rdev->ring[ib->ring];
  2998. u32 header;
  2999. if (ib->is_const_ib) {
  3000. /* set switch buffer packet before const IB */
  3001. radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
  3002. radeon_ring_write(ring, 0);
  3003. header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
  3004. } else {
  3005. u32 next_rptr;
  3006. if (ring->rptr_save_reg) {
  3007. next_rptr = ring->wptr + 3 + 4 + 8;
  3008. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  3009. radeon_ring_write(ring, ((ring->rptr_save_reg -
  3010. PACKET3_SET_CONFIG_REG_START) >> 2));
  3011. radeon_ring_write(ring, next_rptr);
  3012. } else if (rdev->wb.enabled) {
  3013. next_rptr = ring->wptr + 5 + 4 + 8;
  3014. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3015. radeon_ring_write(ring, (1 << 8));
  3016. radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
  3017. radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
  3018. radeon_ring_write(ring, next_rptr);
  3019. }
  3020. header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
  3021. }
  3022. radeon_ring_write(ring, header);
  3023. radeon_ring_write(ring,
  3024. #ifdef __BIG_ENDIAN
  3025. (2 << 0) |
  3026. #endif
  3027. (ib->gpu_addr & 0xFFFFFFFC));
  3028. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
  3029. radeon_ring_write(ring, ib->length_dw |
  3030. (ib->vm ? (ib->vm->id << 24) : 0));
  3031. if (!ib->is_const_ib) {
  3032. /* flush read cache over gart for this vmid */
  3033. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  3034. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  3035. radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
  3036. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  3037. radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
  3038. PACKET3_TC_ACTION_ENA |
  3039. PACKET3_SH_KCACHE_ACTION_ENA |
  3040. PACKET3_SH_ICACHE_ACTION_ENA);
  3041. radeon_ring_write(ring, 0xFFFFFFFF);
  3042. radeon_ring_write(ring, 0);
  3043. radeon_ring_write(ring, 10); /* poll interval */
  3044. }
  3045. }
  3046. /*
  3047. * CP.
  3048. */
  3049. static void si_cp_enable(struct radeon_device *rdev, bool enable)
  3050. {
  3051. if (enable)
  3052. WREG32(CP_ME_CNTL, 0);
  3053. else {
  3054. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  3055. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
  3056. WREG32(SCRATCH_UMSK, 0);
  3057. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  3058. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  3059. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  3060. }
  3061. udelay(50);
  3062. }
  3063. static int si_cp_load_microcode(struct radeon_device *rdev)
  3064. {
  3065. const __be32 *fw_data;
  3066. int i;
  3067. if (!rdev->me_fw || !rdev->pfp_fw)
  3068. return -EINVAL;
  3069. si_cp_enable(rdev, false);
  3070. /* PFP */
  3071. fw_data = (const __be32 *)rdev->pfp_fw->data;
  3072. WREG32(CP_PFP_UCODE_ADDR, 0);
  3073. for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
  3074. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  3075. WREG32(CP_PFP_UCODE_ADDR, 0);
  3076. /* CE */
  3077. fw_data = (const __be32 *)rdev->ce_fw->data;
  3078. WREG32(CP_CE_UCODE_ADDR, 0);
  3079. for (i = 0; i < SI_CE_UCODE_SIZE; i++)
  3080. WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
  3081. WREG32(CP_CE_UCODE_ADDR, 0);
  3082. /* ME */
  3083. fw_data = (const __be32 *)rdev->me_fw->data;
  3084. WREG32(CP_ME_RAM_WADDR, 0);
  3085. for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
  3086. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  3087. WREG32(CP_ME_RAM_WADDR, 0);
  3088. WREG32(CP_PFP_UCODE_ADDR, 0);
  3089. WREG32(CP_CE_UCODE_ADDR, 0);
  3090. WREG32(CP_ME_RAM_WADDR, 0);
  3091. WREG32(CP_ME_RAM_RADDR, 0);
  3092. return 0;
  3093. }
  3094. static int si_cp_start(struct radeon_device *rdev)
  3095. {
  3096. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  3097. int r, i;
  3098. r = radeon_ring_lock(rdev, ring, 7 + 4);
  3099. if (r) {
  3100. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  3101. return r;
  3102. }
  3103. /* init the CP */
  3104. radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
  3105. radeon_ring_write(ring, 0x1);
  3106. radeon_ring_write(ring, 0x0);
  3107. radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
  3108. radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
  3109. radeon_ring_write(ring, 0);
  3110. radeon_ring_write(ring, 0);
  3111. /* init the CE partitions */
  3112. radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
  3113. radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
  3114. radeon_ring_write(ring, 0xc000);
  3115. radeon_ring_write(ring, 0xe000);
  3116. radeon_ring_unlock_commit(rdev, ring);
  3117. si_cp_enable(rdev, true);
  3118. r = radeon_ring_lock(rdev, ring, si_default_size + 10);
  3119. if (r) {
  3120. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  3121. return r;
  3122. }
  3123. /* setup clear context state */
  3124. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  3125. radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  3126. for (i = 0; i < si_default_size; i++)
  3127. radeon_ring_write(ring, si_default_state[i]);
  3128. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  3129. radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  3130. /* set clear context state */
  3131. radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  3132. radeon_ring_write(ring, 0);
  3133. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  3134. radeon_ring_write(ring, 0x00000316);
  3135. radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  3136. radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
  3137. radeon_ring_unlock_commit(rdev, ring);
  3138. for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
  3139. ring = &rdev->ring[i];
  3140. r = radeon_ring_lock(rdev, ring, 2);
  3141. /* clear the compute context state */
  3142. radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
  3143. radeon_ring_write(ring, 0);
  3144. radeon_ring_unlock_commit(rdev, ring);
  3145. }
  3146. return 0;
  3147. }
  3148. static void si_cp_fini(struct radeon_device *rdev)
  3149. {
  3150. struct radeon_ring *ring;
  3151. si_cp_enable(rdev, false);
  3152. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  3153. radeon_ring_fini(rdev, ring);
  3154. radeon_scratch_free(rdev, ring->rptr_save_reg);
  3155. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  3156. radeon_ring_fini(rdev, ring);
  3157. radeon_scratch_free(rdev, ring->rptr_save_reg);
  3158. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  3159. radeon_ring_fini(rdev, ring);
  3160. radeon_scratch_free(rdev, ring->rptr_save_reg);
  3161. }
  3162. static int si_cp_resume(struct radeon_device *rdev)
  3163. {
  3164. struct radeon_ring *ring;
  3165. u32 tmp;
  3166. u32 rb_bufsz;
  3167. int r;
  3168. si_enable_gui_idle_interrupt(rdev, false);
  3169. WREG32(CP_SEM_WAIT_TIMER, 0x0);
  3170. WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
  3171. /* Set the write pointer delay */
  3172. WREG32(CP_RB_WPTR_DELAY, 0);
  3173. WREG32(CP_DEBUG, 0);
  3174. WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
  3175. /* ring 0 - compute and gfx */
  3176. /* Set ring buffer size */
  3177. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  3178. rb_bufsz = order_base_2(ring->ring_size / 8);
  3179. tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  3180. #ifdef __BIG_ENDIAN
  3181. tmp |= BUF_SWAP_32BIT;
  3182. #endif
  3183. WREG32(CP_RB0_CNTL, tmp);
  3184. /* Initialize the ring buffer's read and write pointers */
  3185. WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
  3186. ring->wptr = 0;
  3187. WREG32(CP_RB0_WPTR, ring->wptr);
  3188. /* set the wb address whether it's enabled or not */
  3189. WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
  3190. WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
  3191. if (rdev->wb.enabled)
  3192. WREG32(SCRATCH_UMSK, 0xff);
  3193. else {
  3194. tmp |= RB_NO_UPDATE;
  3195. WREG32(SCRATCH_UMSK, 0);
  3196. }
  3197. mdelay(1);
  3198. WREG32(CP_RB0_CNTL, tmp);
  3199. WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
  3200. ring->rptr = RREG32(CP_RB0_RPTR);
  3201. /* ring1 - compute only */
  3202. /* Set ring buffer size */
  3203. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  3204. rb_bufsz = order_base_2(ring->ring_size / 8);
  3205. tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  3206. #ifdef __BIG_ENDIAN
  3207. tmp |= BUF_SWAP_32BIT;
  3208. #endif
  3209. WREG32(CP_RB1_CNTL, tmp);
  3210. /* Initialize the ring buffer's read and write pointers */
  3211. WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
  3212. ring->wptr = 0;
  3213. WREG32(CP_RB1_WPTR, ring->wptr);
  3214. /* set the wb address whether it's enabled or not */
  3215. WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
  3216. WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
  3217. mdelay(1);
  3218. WREG32(CP_RB1_CNTL, tmp);
  3219. WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
  3220. ring->rptr = RREG32(CP_RB1_RPTR);
  3221. /* ring2 - compute only */
  3222. /* Set ring buffer size */
  3223. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  3224. rb_bufsz = order_base_2(ring->ring_size / 8);
  3225. tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  3226. #ifdef __BIG_ENDIAN
  3227. tmp |= BUF_SWAP_32BIT;
  3228. #endif
  3229. WREG32(CP_RB2_CNTL, tmp);
  3230. /* Initialize the ring buffer's read and write pointers */
  3231. WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
  3232. ring->wptr = 0;
  3233. WREG32(CP_RB2_WPTR, ring->wptr);
  3234. /* set the wb address whether it's enabled or not */
  3235. WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
  3236. WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
  3237. mdelay(1);
  3238. WREG32(CP_RB2_CNTL, tmp);
  3239. WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
  3240. ring->rptr = RREG32(CP_RB2_RPTR);
  3241. /* start the rings */
  3242. si_cp_start(rdev);
  3243. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
  3244. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
  3245. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
  3246. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  3247. if (r) {
  3248. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  3249. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  3250. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  3251. return r;
  3252. }
  3253. r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
  3254. if (r) {
  3255. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  3256. }
  3257. r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
  3258. if (r) {
  3259. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  3260. }
  3261. si_enable_gui_idle_interrupt(rdev, true);
  3262. return 0;
  3263. }
  3264. u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
  3265. {
  3266. u32 reset_mask = 0;
  3267. u32 tmp;
  3268. /* GRBM_STATUS */
  3269. tmp = RREG32(GRBM_STATUS);
  3270. if (tmp & (PA_BUSY | SC_BUSY |
  3271. BCI_BUSY | SX_BUSY |
  3272. TA_BUSY | VGT_BUSY |
  3273. DB_BUSY | CB_BUSY |
  3274. GDS_BUSY | SPI_BUSY |
  3275. IA_BUSY | IA_BUSY_NO_DMA))
  3276. reset_mask |= RADEON_RESET_GFX;
  3277. if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
  3278. CP_BUSY | CP_COHERENCY_BUSY))
  3279. reset_mask |= RADEON_RESET_CP;
  3280. if (tmp & GRBM_EE_BUSY)
  3281. reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
  3282. /* GRBM_STATUS2 */
  3283. tmp = RREG32(GRBM_STATUS2);
  3284. if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
  3285. reset_mask |= RADEON_RESET_RLC;
  3286. /* DMA_STATUS_REG 0 */
  3287. tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
  3288. if (!(tmp & DMA_IDLE))
  3289. reset_mask |= RADEON_RESET_DMA;
  3290. /* DMA_STATUS_REG 1 */
  3291. tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
  3292. if (!(tmp & DMA_IDLE))
  3293. reset_mask |= RADEON_RESET_DMA1;
  3294. /* SRBM_STATUS2 */
  3295. tmp = RREG32(SRBM_STATUS2);
  3296. if (tmp & DMA_BUSY)
  3297. reset_mask |= RADEON_RESET_DMA;
  3298. if (tmp & DMA1_BUSY)
  3299. reset_mask |= RADEON_RESET_DMA1;
  3300. /* SRBM_STATUS */
  3301. tmp = RREG32(SRBM_STATUS);
  3302. if (tmp & IH_BUSY)
  3303. reset_mask |= RADEON_RESET_IH;
  3304. if (tmp & SEM_BUSY)
  3305. reset_mask |= RADEON_RESET_SEM;
  3306. if (tmp & GRBM_RQ_PENDING)
  3307. reset_mask |= RADEON_RESET_GRBM;
  3308. if (tmp & VMC_BUSY)
  3309. reset_mask |= RADEON_RESET_VMC;
  3310. if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
  3311. MCC_BUSY | MCD_BUSY))
  3312. reset_mask |= RADEON_RESET_MC;
  3313. if (evergreen_is_display_hung(rdev))
  3314. reset_mask |= RADEON_RESET_DISPLAY;
  3315. /* VM_L2_STATUS */
  3316. tmp = RREG32(VM_L2_STATUS);
  3317. if (tmp & L2_BUSY)
  3318. reset_mask |= RADEON_RESET_VMC;
  3319. /* Skip MC reset as it's mostly likely not hung, just busy */
  3320. if (reset_mask & RADEON_RESET_MC) {
  3321. DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
  3322. reset_mask &= ~RADEON_RESET_MC;
  3323. }
  3324. return reset_mask;
  3325. }
  3326. static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
  3327. {
  3328. struct evergreen_mc_save save;
  3329. u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
  3330. u32 tmp;
  3331. if (reset_mask == 0)
  3332. return;
  3333. dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
  3334. evergreen_print_gpu_status_regs(rdev);
  3335. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
  3336. RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
  3337. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
  3338. RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
  3339. /* Disable CP parsing/prefetching */
  3340. WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
  3341. if (reset_mask & RADEON_RESET_DMA) {
  3342. /* dma0 */
  3343. tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
  3344. tmp &= ~DMA_RB_ENABLE;
  3345. WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
  3346. }
  3347. if (reset_mask & RADEON_RESET_DMA1) {
  3348. /* dma1 */
  3349. tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
  3350. tmp &= ~DMA_RB_ENABLE;
  3351. WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
  3352. }
  3353. udelay(50);
  3354. evergreen_mc_stop(rdev, &save);
  3355. if (evergreen_mc_wait_for_idle(rdev)) {
  3356. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3357. }
  3358. if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
  3359. grbm_soft_reset = SOFT_RESET_CB |
  3360. SOFT_RESET_DB |
  3361. SOFT_RESET_GDS |
  3362. SOFT_RESET_PA |
  3363. SOFT_RESET_SC |
  3364. SOFT_RESET_BCI |
  3365. SOFT_RESET_SPI |
  3366. SOFT_RESET_SX |
  3367. SOFT_RESET_TC |
  3368. SOFT_RESET_TA |
  3369. SOFT_RESET_VGT |
  3370. SOFT_RESET_IA;
  3371. }
  3372. if (reset_mask & RADEON_RESET_CP) {
  3373. grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
  3374. srbm_soft_reset |= SOFT_RESET_GRBM;
  3375. }
  3376. if (reset_mask & RADEON_RESET_DMA)
  3377. srbm_soft_reset |= SOFT_RESET_DMA;
  3378. if (reset_mask & RADEON_RESET_DMA1)
  3379. srbm_soft_reset |= SOFT_RESET_DMA1;
  3380. if (reset_mask & RADEON_RESET_DISPLAY)
  3381. srbm_soft_reset |= SOFT_RESET_DC;
  3382. if (reset_mask & RADEON_RESET_RLC)
  3383. grbm_soft_reset |= SOFT_RESET_RLC;
  3384. if (reset_mask & RADEON_RESET_SEM)
  3385. srbm_soft_reset |= SOFT_RESET_SEM;
  3386. if (reset_mask & RADEON_RESET_IH)
  3387. srbm_soft_reset |= SOFT_RESET_IH;
  3388. if (reset_mask & RADEON_RESET_GRBM)
  3389. srbm_soft_reset |= SOFT_RESET_GRBM;
  3390. if (reset_mask & RADEON_RESET_VMC)
  3391. srbm_soft_reset |= SOFT_RESET_VMC;
  3392. if (reset_mask & RADEON_RESET_MC)
  3393. srbm_soft_reset |= SOFT_RESET_MC;
  3394. if (grbm_soft_reset) {
  3395. tmp = RREG32(GRBM_SOFT_RESET);
  3396. tmp |= grbm_soft_reset;
  3397. dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
  3398. WREG32(GRBM_SOFT_RESET, tmp);
  3399. tmp = RREG32(GRBM_SOFT_RESET);
  3400. udelay(50);
  3401. tmp &= ~grbm_soft_reset;
  3402. WREG32(GRBM_SOFT_RESET, tmp);
  3403. tmp = RREG32(GRBM_SOFT_RESET);
  3404. }
  3405. if (srbm_soft_reset) {
  3406. tmp = RREG32(SRBM_SOFT_RESET);
  3407. tmp |= srbm_soft_reset;
  3408. dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  3409. WREG32(SRBM_SOFT_RESET, tmp);
  3410. tmp = RREG32(SRBM_SOFT_RESET);
  3411. udelay(50);
  3412. tmp &= ~srbm_soft_reset;
  3413. WREG32(SRBM_SOFT_RESET, tmp);
  3414. tmp = RREG32(SRBM_SOFT_RESET);
  3415. }
  3416. /* Wait a little for things to settle down */
  3417. udelay(50);
  3418. evergreen_mc_resume(rdev, &save);
  3419. udelay(50);
  3420. evergreen_print_gpu_status_regs(rdev);
  3421. }
  3422. int si_asic_reset(struct radeon_device *rdev)
  3423. {
  3424. u32 reset_mask;
  3425. reset_mask = si_gpu_check_soft_reset(rdev);
  3426. if (reset_mask)
  3427. r600_set_bios_scratch_engine_hung(rdev, true);
  3428. si_gpu_soft_reset(rdev, reset_mask);
  3429. reset_mask = si_gpu_check_soft_reset(rdev);
  3430. if (!reset_mask)
  3431. r600_set_bios_scratch_engine_hung(rdev, false);
  3432. return 0;
  3433. }
  3434. /**
  3435. * si_gfx_is_lockup - Check if the GFX engine is locked up
  3436. *
  3437. * @rdev: radeon_device pointer
  3438. * @ring: radeon_ring structure holding ring information
  3439. *
  3440. * Check if the GFX engine is locked up.
  3441. * Returns true if the engine appears to be locked up, false if not.
  3442. */
  3443. bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  3444. {
  3445. u32 reset_mask = si_gpu_check_soft_reset(rdev);
  3446. if (!(reset_mask & (RADEON_RESET_GFX |
  3447. RADEON_RESET_COMPUTE |
  3448. RADEON_RESET_CP))) {
  3449. radeon_ring_lockup_update(ring);
  3450. return false;
  3451. }
  3452. /* force CP activities */
  3453. radeon_ring_force_activity(rdev, ring);
  3454. return radeon_ring_test_lockup(rdev, ring);
  3455. }
  3456. /* MC */
  3457. static void si_mc_program(struct radeon_device *rdev)
  3458. {
  3459. struct evergreen_mc_save save;
  3460. u32 tmp;
  3461. int i, j;
  3462. /* Initialize HDP */
  3463. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  3464. WREG32((0x2c14 + j), 0x00000000);
  3465. WREG32((0x2c18 + j), 0x00000000);
  3466. WREG32((0x2c1c + j), 0x00000000);
  3467. WREG32((0x2c20 + j), 0x00000000);
  3468. WREG32((0x2c24 + j), 0x00000000);
  3469. }
  3470. WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
  3471. evergreen_mc_stop(rdev, &save);
  3472. if (radeon_mc_wait_for_idle(rdev)) {
  3473. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3474. }
  3475. if (!ASIC_IS_NODCE(rdev))
  3476. /* Lockout access through VGA aperture*/
  3477. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  3478. /* Update configuration */
  3479. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  3480. rdev->mc.vram_start >> 12);
  3481. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  3482. rdev->mc.vram_end >> 12);
  3483. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
  3484. rdev->vram_scratch.gpu_addr >> 12);
  3485. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  3486. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  3487. WREG32(MC_VM_FB_LOCATION, tmp);
  3488. /* XXX double check these! */
  3489. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  3490. WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
  3491. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  3492. WREG32(MC_VM_AGP_BASE, 0);
  3493. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  3494. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  3495. if (radeon_mc_wait_for_idle(rdev)) {
  3496. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3497. }
  3498. evergreen_mc_resume(rdev, &save);
  3499. if (!ASIC_IS_NODCE(rdev)) {
  3500. /* we need to own VRAM, so turn off the VGA renderer here
  3501. * to stop it overwriting our objects */
  3502. rv515_vga_render_disable(rdev);
  3503. }
  3504. }
  3505. void si_vram_gtt_location(struct radeon_device *rdev,
  3506. struct radeon_mc *mc)
  3507. {
  3508. if (mc->mc_vram_size > 0xFFC0000000ULL) {
  3509. /* leave room for at least 1024M GTT */
  3510. dev_warn(rdev->dev, "limiting VRAM\n");
  3511. mc->real_vram_size = 0xFFC0000000ULL;
  3512. mc->mc_vram_size = 0xFFC0000000ULL;
  3513. }
  3514. radeon_vram_location(rdev, &rdev->mc, 0);
  3515. rdev->mc.gtt_base_align = 0;
  3516. radeon_gtt_location(rdev, mc);
  3517. }
  3518. static int si_mc_init(struct radeon_device *rdev)
  3519. {
  3520. u32 tmp;
  3521. int chansize, numchan;
  3522. /* Get VRAM informations */
  3523. rdev->mc.vram_is_ddr = true;
  3524. tmp = RREG32(MC_ARB_RAMCFG);
  3525. if (tmp & CHANSIZE_OVERRIDE) {
  3526. chansize = 16;
  3527. } else if (tmp & CHANSIZE_MASK) {
  3528. chansize = 64;
  3529. } else {
  3530. chansize = 32;
  3531. }
  3532. tmp = RREG32(MC_SHARED_CHMAP);
  3533. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  3534. case 0:
  3535. default:
  3536. numchan = 1;
  3537. break;
  3538. case 1:
  3539. numchan = 2;
  3540. break;
  3541. case 2:
  3542. numchan = 4;
  3543. break;
  3544. case 3:
  3545. numchan = 8;
  3546. break;
  3547. case 4:
  3548. numchan = 3;
  3549. break;
  3550. case 5:
  3551. numchan = 6;
  3552. break;
  3553. case 6:
  3554. numchan = 10;
  3555. break;
  3556. case 7:
  3557. numchan = 12;
  3558. break;
  3559. case 8:
  3560. numchan = 16;
  3561. break;
  3562. }
  3563. rdev->mc.vram_width = numchan * chansize;
  3564. /* Could aper size report 0 ? */
  3565. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  3566. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  3567. /* size in MB on si */
  3568. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
  3569. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
  3570. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  3571. si_vram_gtt_location(rdev, &rdev->mc);
  3572. radeon_update_bandwidth_info(rdev);
  3573. return 0;
  3574. }
  3575. /*
  3576. * GART
  3577. */
  3578. void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
  3579. {
  3580. /* flush hdp cache */
  3581. WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  3582. /* bits 0-15 are the VM contexts0-15 */
  3583. WREG32(VM_INVALIDATE_REQUEST, 1);
  3584. }
  3585. static int si_pcie_gart_enable(struct radeon_device *rdev)
  3586. {
  3587. int r, i;
  3588. if (rdev->gart.robj == NULL) {
  3589. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  3590. return -EINVAL;
  3591. }
  3592. r = radeon_gart_table_vram_pin(rdev);
  3593. if (r)
  3594. return r;
  3595. radeon_gart_restore(rdev);
  3596. /* Setup TLB control */
  3597. WREG32(MC_VM_MX_L1_TLB_CNTL,
  3598. (0xA << 7) |
  3599. ENABLE_L1_TLB |
  3600. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  3601. ENABLE_ADVANCED_DRIVER_MODEL |
  3602. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  3603. /* Setup L2 cache */
  3604. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
  3605. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  3606. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  3607. EFFECTIVE_L2_QUEUE_SIZE(7) |
  3608. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  3609. WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
  3610. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  3611. L2_CACHE_BIGK_FRAGMENT_SIZE(0));
  3612. /* setup context0 */
  3613. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  3614. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  3615. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  3616. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  3617. (u32)(rdev->dummy_page.addr >> 12));
  3618. WREG32(VM_CONTEXT0_CNTL2, 0);
  3619. WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  3620. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
  3621. WREG32(0x15D4, 0);
  3622. WREG32(0x15D8, 0);
  3623. WREG32(0x15DC, 0);
  3624. /* empty context1-15 */
  3625. /* set vm size, must be a multiple of 4 */
  3626. WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
  3627. WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
  3628. /* Assign the pt base to something valid for now; the pts used for
  3629. * the VMs are determined by the application and setup and assigned
  3630. * on the fly in the vm part of radeon_gart.c
  3631. */
  3632. for (i = 1; i < 16; i++) {
  3633. if (i < 8)
  3634. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
  3635. rdev->gart.table_addr >> 12);
  3636. else
  3637. WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
  3638. rdev->gart.table_addr >> 12);
  3639. }
  3640. /* enable context1-15 */
  3641. WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
  3642. (u32)(rdev->dummy_page.addr >> 12));
  3643. WREG32(VM_CONTEXT1_CNTL2, 4);
  3644. WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
  3645. RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3646. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  3647. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3648. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  3649. PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3650. PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
  3651. VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3652. VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
  3653. READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3654. READ_PROTECTION_FAULT_ENABLE_DEFAULT |
  3655. WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3656. WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
  3657. si_pcie_gart_tlb_flush(rdev);
  3658. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  3659. (unsigned)(rdev->mc.gtt_size >> 20),
  3660. (unsigned long long)rdev->gart.table_addr);
  3661. rdev->gart.ready = true;
  3662. return 0;
  3663. }
  3664. static void si_pcie_gart_disable(struct radeon_device *rdev)
  3665. {
  3666. /* Disable all tables */
  3667. WREG32(VM_CONTEXT0_CNTL, 0);
  3668. WREG32(VM_CONTEXT1_CNTL, 0);
  3669. /* Setup TLB control */
  3670. WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  3671. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  3672. /* Setup L2 cache */
  3673. WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  3674. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  3675. EFFECTIVE_L2_QUEUE_SIZE(7) |
  3676. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  3677. WREG32(VM_L2_CNTL2, 0);
  3678. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  3679. L2_CACHE_BIGK_FRAGMENT_SIZE(0));
  3680. radeon_gart_table_vram_unpin(rdev);
  3681. }
  3682. static void si_pcie_gart_fini(struct radeon_device *rdev)
  3683. {
  3684. si_pcie_gart_disable(rdev);
  3685. radeon_gart_table_vram_free(rdev);
  3686. radeon_gart_fini(rdev);
  3687. }
  3688. /* vm parser */
  3689. static bool si_vm_reg_valid(u32 reg)
  3690. {
  3691. /* context regs are fine */
  3692. if (reg >= 0x28000)
  3693. return true;
  3694. /* check config regs */
  3695. switch (reg) {
  3696. case GRBM_GFX_INDEX:
  3697. case CP_STRMOUT_CNTL:
  3698. case VGT_VTX_VECT_EJECT_REG:
  3699. case VGT_CACHE_INVALIDATION:
  3700. case VGT_ESGS_RING_SIZE:
  3701. case VGT_GSVS_RING_SIZE:
  3702. case VGT_GS_VERTEX_REUSE:
  3703. case VGT_PRIMITIVE_TYPE:
  3704. case VGT_INDEX_TYPE:
  3705. case VGT_NUM_INDICES:
  3706. case VGT_NUM_INSTANCES:
  3707. case VGT_TF_RING_SIZE:
  3708. case VGT_HS_OFFCHIP_PARAM:
  3709. case VGT_TF_MEMORY_BASE:
  3710. case PA_CL_ENHANCE:
  3711. case PA_SU_LINE_STIPPLE_VALUE:
  3712. case PA_SC_LINE_STIPPLE_STATE:
  3713. case PA_SC_ENHANCE:
  3714. case SQC_CACHES:
  3715. case SPI_STATIC_THREAD_MGMT_1:
  3716. case SPI_STATIC_THREAD_MGMT_2:
  3717. case SPI_STATIC_THREAD_MGMT_3:
  3718. case SPI_PS_MAX_WAVE_ID:
  3719. case SPI_CONFIG_CNTL:
  3720. case SPI_CONFIG_CNTL_1:
  3721. case TA_CNTL_AUX:
  3722. return true;
  3723. default:
  3724. DRM_ERROR("Invalid register 0x%x in CS\n", reg);
  3725. return false;
  3726. }
  3727. }
  3728. static int si_vm_packet3_ce_check(struct radeon_device *rdev,
  3729. u32 *ib, struct radeon_cs_packet *pkt)
  3730. {
  3731. switch (pkt->opcode) {
  3732. case PACKET3_NOP:
  3733. case PACKET3_SET_BASE:
  3734. case PACKET3_SET_CE_DE_COUNTERS:
  3735. case PACKET3_LOAD_CONST_RAM:
  3736. case PACKET3_WRITE_CONST_RAM:
  3737. case PACKET3_WRITE_CONST_RAM_OFFSET:
  3738. case PACKET3_DUMP_CONST_RAM:
  3739. case PACKET3_INCREMENT_CE_COUNTER:
  3740. case PACKET3_WAIT_ON_DE_COUNTER:
  3741. case PACKET3_CE_WRITE:
  3742. break;
  3743. default:
  3744. DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
  3745. return -EINVAL;
  3746. }
  3747. return 0;
  3748. }
  3749. static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
  3750. {
  3751. u32 start_reg, reg, i;
  3752. u32 command = ib[idx + 4];
  3753. u32 info = ib[idx + 1];
  3754. u32 idx_value = ib[idx];
  3755. if (command & PACKET3_CP_DMA_CMD_SAS) {
  3756. /* src address space is register */
  3757. if (((info & 0x60000000) >> 29) == 0) {
  3758. start_reg = idx_value << 2;
  3759. if (command & PACKET3_CP_DMA_CMD_SAIC) {
  3760. reg = start_reg;
  3761. if (!si_vm_reg_valid(reg)) {
  3762. DRM_ERROR("CP DMA Bad SRC register\n");
  3763. return -EINVAL;
  3764. }
  3765. } else {
  3766. for (i = 0; i < (command & 0x1fffff); i++) {
  3767. reg = start_reg + (4 * i);
  3768. if (!si_vm_reg_valid(reg)) {
  3769. DRM_ERROR("CP DMA Bad SRC register\n");
  3770. return -EINVAL;
  3771. }
  3772. }
  3773. }
  3774. }
  3775. }
  3776. if (command & PACKET3_CP_DMA_CMD_DAS) {
  3777. /* dst address space is register */
  3778. if (((info & 0x00300000) >> 20) == 0) {
  3779. start_reg = ib[idx + 2];
  3780. if (command & PACKET3_CP_DMA_CMD_DAIC) {
  3781. reg = start_reg;
  3782. if (!si_vm_reg_valid(reg)) {
  3783. DRM_ERROR("CP DMA Bad DST register\n");
  3784. return -EINVAL;
  3785. }
  3786. } else {
  3787. for (i = 0; i < (command & 0x1fffff); i++) {
  3788. reg = start_reg + (4 * i);
  3789. if (!si_vm_reg_valid(reg)) {
  3790. DRM_ERROR("CP DMA Bad DST register\n");
  3791. return -EINVAL;
  3792. }
  3793. }
  3794. }
  3795. }
  3796. }
  3797. return 0;
  3798. }
  3799. static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
  3800. u32 *ib, struct radeon_cs_packet *pkt)
  3801. {
  3802. int r;
  3803. u32 idx = pkt->idx + 1;
  3804. u32 idx_value = ib[idx];
  3805. u32 start_reg, end_reg, reg, i;
  3806. switch (pkt->opcode) {
  3807. case PACKET3_NOP:
  3808. case PACKET3_SET_BASE:
  3809. case PACKET3_CLEAR_STATE:
  3810. case PACKET3_INDEX_BUFFER_SIZE:
  3811. case PACKET3_DISPATCH_DIRECT:
  3812. case PACKET3_DISPATCH_INDIRECT:
  3813. case PACKET3_ALLOC_GDS:
  3814. case PACKET3_WRITE_GDS_RAM:
  3815. case PACKET3_ATOMIC_GDS:
  3816. case PACKET3_ATOMIC:
  3817. case PACKET3_OCCLUSION_QUERY:
  3818. case PACKET3_SET_PREDICATION:
  3819. case PACKET3_COND_EXEC:
  3820. case PACKET3_PRED_EXEC:
  3821. case PACKET3_DRAW_INDIRECT:
  3822. case PACKET3_DRAW_INDEX_INDIRECT:
  3823. case PACKET3_INDEX_BASE:
  3824. case PACKET3_DRAW_INDEX_2:
  3825. case PACKET3_CONTEXT_CONTROL:
  3826. case PACKET3_INDEX_TYPE:
  3827. case PACKET3_DRAW_INDIRECT_MULTI:
  3828. case PACKET3_DRAW_INDEX_AUTO:
  3829. case PACKET3_DRAW_INDEX_IMMD:
  3830. case PACKET3_NUM_INSTANCES:
  3831. case PACKET3_DRAW_INDEX_MULTI_AUTO:
  3832. case PACKET3_STRMOUT_BUFFER_UPDATE:
  3833. case PACKET3_DRAW_INDEX_OFFSET_2:
  3834. case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
  3835. case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
  3836. case PACKET3_MPEG_INDEX:
  3837. case PACKET3_WAIT_REG_MEM:
  3838. case PACKET3_MEM_WRITE:
  3839. case PACKET3_PFP_SYNC_ME:
  3840. case PACKET3_SURFACE_SYNC:
  3841. case PACKET3_EVENT_WRITE:
  3842. case PACKET3_EVENT_WRITE_EOP:
  3843. case PACKET3_EVENT_WRITE_EOS:
  3844. case PACKET3_SET_CONTEXT_REG:
  3845. case PACKET3_SET_CONTEXT_REG_INDIRECT:
  3846. case PACKET3_SET_SH_REG:
  3847. case PACKET3_SET_SH_REG_OFFSET:
  3848. case PACKET3_INCREMENT_DE_COUNTER:
  3849. case PACKET3_WAIT_ON_CE_COUNTER:
  3850. case PACKET3_WAIT_ON_AVAIL_BUFFER:
  3851. case PACKET3_ME_WRITE:
  3852. break;
  3853. case PACKET3_COPY_DATA:
  3854. if ((idx_value & 0xf00) == 0) {
  3855. reg = ib[idx + 3] * 4;
  3856. if (!si_vm_reg_valid(reg))
  3857. return -EINVAL;
  3858. }
  3859. break;
  3860. case PACKET3_WRITE_DATA:
  3861. if ((idx_value & 0xf00) == 0) {
  3862. start_reg = ib[idx + 1] * 4;
  3863. if (idx_value & 0x10000) {
  3864. if (!si_vm_reg_valid(start_reg))
  3865. return -EINVAL;
  3866. } else {
  3867. for (i = 0; i < (pkt->count - 2); i++) {
  3868. reg = start_reg + (4 * i);
  3869. if (!si_vm_reg_valid(reg))
  3870. return -EINVAL;
  3871. }
  3872. }
  3873. }
  3874. break;
  3875. case PACKET3_COND_WRITE:
  3876. if (idx_value & 0x100) {
  3877. reg = ib[idx + 5] * 4;
  3878. if (!si_vm_reg_valid(reg))
  3879. return -EINVAL;
  3880. }
  3881. break;
  3882. case PACKET3_COPY_DW:
  3883. if (idx_value & 0x2) {
  3884. reg = ib[idx + 3] * 4;
  3885. if (!si_vm_reg_valid(reg))
  3886. return -EINVAL;
  3887. }
  3888. break;
  3889. case PACKET3_SET_CONFIG_REG:
  3890. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
  3891. end_reg = 4 * pkt->count + start_reg - 4;
  3892. if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
  3893. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  3894. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  3895. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  3896. return -EINVAL;
  3897. }
  3898. for (i = 0; i < pkt->count; i++) {
  3899. reg = start_reg + (4 * i);
  3900. if (!si_vm_reg_valid(reg))
  3901. return -EINVAL;
  3902. }
  3903. break;
  3904. case PACKET3_CP_DMA:
  3905. r = si_vm_packet3_cp_dma_check(ib, idx);
  3906. if (r)
  3907. return r;
  3908. break;
  3909. default:
  3910. DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
  3911. return -EINVAL;
  3912. }
  3913. return 0;
  3914. }
  3915. static int si_vm_packet3_compute_check(struct radeon_device *rdev,
  3916. u32 *ib, struct radeon_cs_packet *pkt)
  3917. {
  3918. int r;
  3919. u32 idx = pkt->idx + 1;
  3920. u32 idx_value = ib[idx];
  3921. u32 start_reg, reg, i;
  3922. switch (pkt->opcode) {
  3923. case PACKET3_NOP:
  3924. case PACKET3_SET_BASE:
  3925. case PACKET3_CLEAR_STATE:
  3926. case PACKET3_DISPATCH_DIRECT:
  3927. case PACKET3_DISPATCH_INDIRECT:
  3928. case PACKET3_ALLOC_GDS:
  3929. case PACKET3_WRITE_GDS_RAM:
  3930. case PACKET3_ATOMIC_GDS:
  3931. case PACKET3_ATOMIC:
  3932. case PACKET3_OCCLUSION_QUERY:
  3933. case PACKET3_SET_PREDICATION:
  3934. case PACKET3_COND_EXEC:
  3935. case PACKET3_PRED_EXEC:
  3936. case PACKET3_CONTEXT_CONTROL:
  3937. case PACKET3_STRMOUT_BUFFER_UPDATE:
  3938. case PACKET3_WAIT_REG_MEM:
  3939. case PACKET3_MEM_WRITE:
  3940. case PACKET3_PFP_SYNC_ME:
  3941. case PACKET3_SURFACE_SYNC:
  3942. case PACKET3_EVENT_WRITE:
  3943. case PACKET3_EVENT_WRITE_EOP:
  3944. case PACKET3_EVENT_WRITE_EOS:
  3945. case PACKET3_SET_CONTEXT_REG:
  3946. case PACKET3_SET_CONTEXT_REG_INDIRECT:
  3947. case PACKET3_SET_SH_REG:
  3948. case PACKET3_SET_SH_REG_OFFSET:
  3949. case PACKET3_INCREMENT_DE_COUNTER:
  3950. case PACKET3_WAIT_ON_CE_COUNTER:
  3951. case PACKET3_WAIT_ON_AVAIL_BUFFER:
  3952. case PACKET3_ME_WRITE:
  3953. break;
  3954. case PACKET3_COPY_DATA:
  3955. if ((idx_value & 0xf00) == 0) {
  3956. reg = ib[idx + 3] * 4;
  3957. if (!si_vm_reg_valid(reg))
  3958. return -EINVAL;
  3959. }
  3960. break;
  3961. case PACKET3_WRITE_DATA:
  3962. if ((idx_value & 0xf00) == 0) {
  3963. start_reg = ib[idx + 1] * 4;
  3964. if (idx_value & 0x10000) {
  3965. if (!si_vm_reg_valid(start_reg))
  3966. return -EINVAL;
  3967. } else {
  3968. for (i = 0; i < (pkt->count - 2); i++) {
  3969. reg = start_reg + (4 * i);
  3970. if (!si_vm_reg_valid(reg))
  3971. return -EINVAL;
  3972. }
  3973. }
  3974. }
  3975. break;
  3976. case PACKET3_COND_WRITE:
  3977. if (idx_value & 0x100) {
  3978. reg = ib[idx + 5] * 4;
  3979. if (!si_vm_reg_valid(reg))
  3980. return -EINVAL;
  3981. }
  3982. break;
  3983. case PACKET3_COPY_DW:
  3984. if (idx_value & 0x2) {
  3985. reg = ib[idx + 3] * 4;
  3986. if (!si_vm_reg_valid(reg))
  3987. return -EINVAL;
  3988. }
  3989. break;
  3990. case PACKET3_CP_DMA:
  3991. r = si_vm_packet3_cp_dma_check(ib, idx);
  3992. if (r)
  3993. return r;
  3994. break;
  3995. default:
  3996. DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
  3997. return -EINVAL;
  3998. }
  3999. return 0;
  4000. }
  4001. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
  4002. {
  4003. int ret = 0;
  4004. u32 idx = 0;
  4005. struct radeon_cs_packet pkt;
  4006. do {
  4007. pkt.idx = idx;
  4008. pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
  4009. pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
  4010. pkt.one_reg_wr = 0;
  4011. switch (pkt.type) {
  4012. case RADEON_PACKET_TYPE0:
  4013. dev_err(rdev->dev, "Packet0 not allowed!\n");
  4014. ret = -EINVAL;
  4015. break;
  4016. case RADEON_PACKET_TYPE2:
  4017. idx += 1;
  4018. break;
  4019. case RADEON_PACKET_TYPE3:
  4020. pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
  4021. if (ib->is_const_ib)
  4022. ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
  4023. else {
  4024. switch (ib->ring) {
  4025. case RADEON_RING_TYPE_GFX_INDEX:
  4026. ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
  4027. break;
  4028. case CAYMAN_RING_TYPE_CP1_INDEX:
  4029. case CAYMAN_RING_TYPE_CP2_INDEX:
  4030. ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
  4031. break;
  4032. default:
  4033. dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
  4034. ret = -EINVAL;
  4035. break;
  4036. }
  4037. }
  4038. idx += pkt.count + 2;
  4039. break;
  4040. default:
  4041. dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
  4042. ret = -EINVAL;
  4043. break;
  4044. }
  4045. if (ret)
  4046. break;
  4047. } while (idx < ib->length_dw);
  4048. return ret;
  4049. }
  4050. /*
  4051. * vm
  4052. */
  4053. int si_vm_init(struct radeon_device *rdev)
  4054. {
  4055. /* number of VMs */
  4056. rdev->vm_manager.nvm = 16;
  4057. /* base offset of vram pages */
  4058. rdev->vm_manager.vram_base_offset = 0;
  4059. return 0;
  4060. }
  4061. void si_vm_fini(struct radeon_device *rdev)
  4062. {
  4063. }
  4064. /**
  4065. * si_vm_decode_fault - print human readable fault info
  4066. *
  4067. * @rdev: radeon_device pointer
  4068. * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
  4069. * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
  4070. *
  4071. * Print human readable fault information (SI).
  4072. */
  4073. static void si_vm_decode_fault(struct radeon_device *rdev,
  4074. u32 status, u32 addr)
  4075. {
  4076. u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
  4077. u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
  4078. u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
  4079. char *block;
  4080. if (rdev->family == CHIP_TAHITI) {
  4081. switch (mc_id) {
  4082. case 160:
  4083. case 144:
  4084. case 96:
  4085. case 80:
  4086. case 224:
  4087. case 208:
  4088. case 32:
  4089. case 16:
  4090. block = "CB";
  4091. break;
  4092. case 161:
  4093. case 145:
  4094. case 97:
  4095. case 81:
  4096. case 225:
  4097. case 209:
  4098. case 33:
  4099. case 17:
  4100. block = "CB_FMASK";
  4101. break;
  4102. case 162:
  4103. case 146:
  4104. case 98:
  4105. case 82:
  4106. case 226:
  4107. case 210:
  4108. case 34:
  4109. case 18:
  4110. block = "CB_CMASK";
  4111. break;
  4112. case 163:
  4113. case 147:
  4114. case 99:
  4115. case 83:
  4116. case 227:
  4117. case 211:
  4118. case 35:
  4119. case 19:
  4120. block = "CB_IMMED";
  4121. break;
  4122. case 164:
  4123. case 148:
  4124. case 100:
  4125. case 84:
  4126. case 228:
  4127. case 212:
  4128. case 36:
  4129. case 20:
  4130. block = "DB";
  4131. break;
  4132. case 165:
  4133. case 149:
  4134. case 101:
  4135. case 85:
  4136. case 229:
  4137. case 213:
  4138. case 37:
  4139. case 21:
  4140. block = "DB_HTILE";
  4141. break;
  4142. case 167:
  4143. case 151:
  4144. case 103:
  4145. case 87:
  4146. case 231:
  4147. case 215:
  4148. case 39:
  4149. case 23:
  4150. block = "DB_STEN";
  4151. break;
  4152. case 72:
  4153. case 68:
  4154. case 64:
  4155. case 8:
  4156. case 4:
  4157. case 0:
  4158. case 136:
  4159. case 132:
  4160. case 128:
  4161. case 200:
  4162. case 196:
  4163. case 192:
  4164. block = "TC";
  4165. break;
  4166. case 112:
  4167. case 48:
  4168. block = "CP";
  4169. break;
  4170. case 49:
  4171. case 177:
  4172. case 50:
  4173. case 178:
  4174. block = "SH";
  4175. break;
  4176. case 53:
  4177. case 190:
  4178. block = "VGT";
  4179. break;
  4180. case 117:
  4181. block = "IH";
  4182. break;
  4183. case 51:
  4184. case 115:
  4185. block = "RLC";
  4186. break;
  4187. case 119:
  4188. case 183:
  4189. block = "DMA0";
  4190. break;
  4191. case 61:
  4192. block = "DMA1";
  4193. break;
  4194. case 248:
  4195. case 120:
  4196. block = "HDP";
  4197. break;
  4198. default:
  4199. block = "unknown";
  4200. break;
  4201. }
  4202. } else {
  4203. switch (mc_id) {
  4204. case 32:
  4205. case 16:
  4206. case 96:
  4207. case 80:
  4208. case 160:
  4209. case 144:
  4210. case 224:
  4211. case 208:
  4212. block = "CB";
  4213. break;
  4214. case 33:
  4215. case 17:
  4216. case 97:
  4217. case 81:
  4218. case 161:
  4219. case 145:
  4220. case 225:
  4221. case 209:
  4222. block = "CB_FMASK";
  4223. break;
  4224. case 34:
  4225. case 18:
  4226. case 98:
  4227. case 82:
  4228. case 162:
  4229. case 146:
  4230. case 226:
  4231. case 210:
  4232. block = "CB_CMASK";
  4233. break;
  4234. case 35:
  4235. case 19:
  4236. case 99:
  4237. case 83:
  4238. case 163:
  4239. case 147:
  4240. case 227:
  4241. case 211:
  4242. block = "CB_IMMED";
  4243. break;
  4244. case 36:
  4245. case 20:
  4246. case 100:
  4247. case 84:
  4248. case 164:
  4249. case 148:
  4250. case 228:
  4251. case 212:
  4252. block = "DB";
  4253. break;
  4254. case 37:
  4255. case 21:
  4256. case 101:
  4257. case 85:
  4258. case 165:
  4259. case 149:
  4260. case 229:
  4261. case 213:
  4262. block = "DB_HTILE";
  4263. break;
  4264. case 39:
  4265. case 23:
  4266. case 103:
  4267. case 87:
  4268. case 167:
  4269. case 151:
  4270. case 231:
  4271. case 215:
  4272. block = "DB_STEN";
  4273. break;
  4274. case 72:
  4275. case 68:
  4276. case 8:
  4277. case 4:
  4278. case 136:
  4279. case 132:
  4280. case 200:
  4281. case 196:
  4282. block = "TC";
  4283. break;
  4284. case 112:
  4285. case 48:
  4286. block = "CP";
  4287. break;
  4288. case 49:
  4289. case 177:
  4290. case 50:
  4291. case 178:
  4292. block = "SH";
  4293. break;
  4294. case 53:
  4295. block = "VGT";
  4296. break;
  4297. case 117:
  4298. block = "IH";
  4299. break;
  4300. case 51:
  4301. case 115:
  4302. block = "RLC";
  4303. break;
  4304. case 119:
  4305. case 183:
  4306. block = "DMA0";
  4307. break;
  4308. case 61:
  4309. block = "DMA1";
  4310. break;
  4311. case 248:
  4312. case 120:
  4313. block = "HDP";
  4314. break;
  4315. default:
  4316. block = "unknown";
  4317. break;
  4318. }
  4319. }
  4320. printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
  4321. protections, vmid, addr,
  4322. (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
  4323. block, mc_id);
  4324. }
  4325. /**
  4326. * si_vm_set_page - update the page tables using the CP
  4327. *
  4328. * @rdev: radeon_device pointer
  4329. * @ib: indirect buffer to fill with commands
  4330. * @pe: addr of the page entry
  4331. * @addr: dst addr to write into pe
  4332. * @count: number of page entries to update
  4333. * @incr: increase next addr by incr bytes
  4334. * @flags: access flags
  4335. *
  4336. * Update the page tables using the CP (SI).
  4337. */
  4338. void si_vm_set_page(struct radeon_device *rdev,
  4339. struct radeon_ib *ib,
  4340. uint64_t pe,
  4341. uint64_t addr, unsigned count,
  4342. uint32_t incr, uint32_t flags)
  4343. {
  4344. uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
  4345. uint64_t value;
  4346. unsigned ndw;
  4347. if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
  4348. while (count) {
  4349. ndw = 2 + count * 2;
  4350. if (ndw > 0x3FFE)
  4351. ndw = 0x3FFE;
  4352. ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
  4353. ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
  4354. WRITE_DATA_DST_SEL(1));
  4355. ib->ptr[ib->length_dw++] = pe;
  4356. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  4357. for (; ndw > 2; ndw -= 2, --count, pe += 8) {
  4358. if (flags & RADEON_VM_PAGE_SYSTEM) {
  4359. value = radeon_vm_map_gart(rdev, addr);
  4360. value &= 0xFFFFFFFFFFFFF000ULL;
  4361. } else if (flags & RADEON_VM_PAGE_VALID) {
  4362. value = addr;
  4363. } else {
  4364. value = 0;
  4365. }
  4366. addr += incr;
  4367. value |= r600_flags;
  4368. ib->ptr[ib->length_dw++] = value;
  4369. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  4370. }
  4371. }
  4372. } else {
  4373. /* DMA */
  4374. si_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
  4375. }
  4376. }
  4377. void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
  4378. {
  4379. struct radeon_ring *ring = &rdev->ring[ridx];
  4380. if (vm == NULL)
  4381. return;
  4382. /* write new base address */
  4383. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  4384. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  4385. WRITE_DATA_DST_SEL(0)));
  4386. if (vm->id < 8) {
  4387. radeon_ring_write(ring,
  4388. (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
  4389. } else {
  4390. radeon_ring_write(ring,
  4391. (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
  4392. }
  4393. radeon_ring_write(ring, 0);
  4394. radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
  4395. /* flush hdp cache */
  4396. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  4397. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  4398. WRITE_DATA_DST_SEL(0)));
  4399. radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
  4400. radeon_ring_write(ring, 0);
  4401. radeon_ring_write(ring, 0x1);
  4402. /* bits 0-15 are the VM contexts0-15 */
  4403. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  4404. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  4405. WRITE_DATA_DST_SEL(0)));
  4406. radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
  4407. radeon_ring_write(ring, 0);
  4408. radeon_ring_write(ring, 1 << vm->id);
  4409. /* sync PFP to ME, otherwise we might get invalid PFP reads */
  4410. radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  4411. radeon_ring_write(ring, 0x0);
  4412. }
  4413. /*
  4414. * Power and clock gating
  4415. */
  4416. static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
  4417. {
  4418. int i;
  4419. for (i = 0; i < rdev->usec_timeout; i++) {
  4420. if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
  4421. break;
  4422. udelay(1);
  4423. }
  4424. for (i = 0; i < rdev->usec_timeout; i++) {
  4425. if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
  4426. break;
  4427. udelay(1);
  4428. }
  4429. }
  4430. static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
  4431. bool enable)
  4432. {
  4433. u32 tmp = RREG32(CP_INT_CNTL_RING0);
  4434. u32 mask;
  4435. int i;
  4436. if (enable)
  4437. tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  4438. else
  4439. tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  4440. WREG32(CP_INT_CNTL_RING0, tmp);
  4441. if (!enable) {
  4442. /* read a gfx register */
  4443. tmp = RREG32(DB_DEPTH_INFO);
  4444. mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
  4445. for (i = 0; i < rdev->usec_timeout; i++) {
  4446. if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
  4447. break;
  4448. udelay(1);
  4449. }
  4450. }
  4451. }
  4452. static void si_set_uvd_dcm(struct radeon_device *rdev,
  4453. bool sw_mode)
  4454. {
  4455. u32 tmp, tmp2;
  4456. tmp = RREG32(UVD_CGC_CTRL);
  4457. tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
  4458. tmp |= DCM | CG_DT(1) | CLK_OD(4);
  4459. if (sw_mode) {
  4460. tmp &= ~0x7ffff800;
  4461. tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
  4462. } else {
  4463. tmp |= 0x7ffff800;
  4464. tmp2 = 0;
  4465. }
  4466. WREG32(UVD_CGC_CTRL, tmp);
  4467. WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
  4468. }
  4469. void si_init_uvd_internal_cg(struct radeon_device *rdev)
  4470. {
  4471. bool hw_mode = true;
  4472. if (hw_mode) {
  4473. si_set_uvd_dcm(rdev, false);
  4474. } else {
  4475. u32 tmp = RREG32(UVD_CGC_CTRL);
  4476. tmp &= ~DCM;
  4477. WREG32(UVD_CGC_CTRL, tmp);
  4478. }
  4479. }
  4480. static u32 si_halt_rlc(struct radeon_device *rdev)
  4481. {
  4482. u32 data, orig;
  4483. orig = data = RREG32(RLC_CNTL);
  4484. if (data & RLC_ENABLE) {
  4485. data &= ~RLC_ENABLE;
  4486. WREG32(RLC_CNTL, data);
  4487. si_wait_for_rlc_serdes(rdev);
  4488. }
  4489. return orig;
  4490. }
  4491. static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
  4492. {
  4493. u32 tmp;
  4494. tmp = RREG32(RLC_CNTL);
  4495. if (tmp != rlc)
  4496. WREG32(RLC_CNTL, rlc);
  4497. }
  4498. static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
  4499. {
  4500. u32 data, orig;
  4501. orig = data = RREG32(DMA_PG);
  4502. if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
  4503. data |= PG_CNTL_ENABLE;
  4504. else
  4505. data &= ~PG_CNTL_ENABLE;
  4506. if (orig != data)
  4507. WREG32(DMA_PG, data);
  4508. }
  4509. static void si_init_dma_pg(struct radeon_device *rdev)
  4510. {
  4511. u32 tmp;
  4512. WREG32(DMA_PGFSM_WRITE, 0x00002000);
  4513. WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
  4514. for (tmp = 0; tmp < 5; tmp++)
  4515. WREG32(DMA_PGFSM_WRITE, 0);
  4516. }
  4517. static void si_enable_gfx_cgpg(struct radeon_device *rdev,
  4518. bool enable)
  4519. {
  4520. u32 tmp;
  4521. if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
  4522. tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
  4523. WREG32(RLC_TTOP_D, tmp);
  4524. tmp = RREG32(RLC_PG_CNTL);
  4525. tmp |= GFX_PG_ENABLE;
  4526. WREG32(RLC_PG_CNTL, tmp);
  4527. tmp = RREG32(RLC_AUTO_PG_CTRL);
  4528. tmp |= AUTO_PG_EN;
  4529. WREG32(RLC_AUTO_PG_CTRL, tmp);
  4530. } else {
  4531. tmp = RREG32(RLC_AUTO_PG_CTRL);
  4532. tmp &= ~AUTO_PG_EN;
  4533. WREG32(RLC_AUTO_PG_CTRL, tmp);
  4534. tmp = RREG32(DB_RENDER_CONTROL);
  4535. }
  4536. }
  4537. static void si_init_gfx_cgpg(struct radeon_device *rdev)
  4538. {
  4539. u32 tmp;
  4540. WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
  4541. tmp = RREG32(RLC_PG_CNTL);
  4542. tmp |= GFX_PG_SRC;
  4543. WREG32(RLC_PG_CNTL, tmp);
  4544. WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
  4545. tmp = RREG32(RLC_AUTO_PG_CTRL);
  4546. tmp &= ~GRBM_REG_SGIT_MASK;
  4547. tmp |= GRBM_REG_SGIT(0x700);
  4548. tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
  4549. WREG32(RLC_AUTO_PG_CTRL, tmp);
  4550. }
  4551. static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
  4552. {
  4553. u32 mask = 0, tmp, tmp1;
  4554. int i;
  4555. si_select_se_sh(rdev, se, sh);
  4556. tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
  4557. tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
  4558. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  4559. tmp &= 0xffff0000;
  4560. tmp |= tmp1;
  4561. tmp >>= 16;
  4562. for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
  4563. mask <<= 1;
  4564. mask |= 1;
  4565. }
  4566. return (~tmp) & mask;
  4567. }
  4568. static void si_init_ao_cu_mask(struct radeon_device *rdev)
  4569. {
  4570. u32 i, j, k, active_cu_number = 0;
  4571. u32 mask, counter, cu_bitmap;
  4572. u32 tmp = 0;
  4573. for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
  4574. for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
  4575. mask = 1;
  4576. cu_bitmap = 0;
  4577. counter = 0;
  4578. for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
  4579. if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
  4580. if (counter < 2)
  4581. cu_bitmap |= mask;
  4582. counter++;
  4583. }
  4584. mask <<= 1;
  4585. }
  4586. active_cu_number += counter;
  4587. tmp |= (cu_bitmap << (i * 16 + j * 8));
  4588. }
  4589. }
  4590. WREG32(RLC_PG_AO_CU_MASK, tmp);
  4591. tmp = RREG32(RLC_MAX_PG_CU);
  4592. tmp &= ~MAX_PU_CU_MASK;
  4593. tmp |= MAX_PU_CU(active_cu_number);
  4594. WREG32(RLC_MAX_PG_CU, tmp);
  4595. }
  4596. static void si_enable_cgcg(struct radeon_device *rdev,
  4597. bool enable)
  4598. {
  4599. u32 data, orig, tmp;
  4600. orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
  4601. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
  4602. si_enable_gui_idle_interrupt(rdev, true);
  4603. WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
  4604. tmp = si_halt_rlc(rdev);
  4605. WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
  4606. WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
  4607. WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
  4608. si_wait_for_rlc_serdes(rdev);
  4609. si_update_rlc(rdev, tmp);
  4610. WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
  4611. data |= CGCG_EN | CGLS_EN;
  4612. } else {
  4613. si_enable_gui_idle_interrupt(rdev, false);
  4614. RREG32(CB_CGTT_SCLK_CTRL);
  4615. RREG32(CB_CGTT_SCLK_CTRL);
  4616. RREG32(CB_CGTT_SCLK_CTRL);
  4617. RREG32(CB_CGTT_SCLK_CTRL);
  4618. data &= ~(CGCG_EN | CGLS_EN);
  4619. }
  4620. if (orig != data)
  4621. WREG32(RLC_CGCG_CGLS_CTRL, data);
  4622. }
  4623. static void si_enable_mgcg(struct radeon_device *rdev,
  4624. bool enable)
  4625. {
  4626. u32 data, orig, tmp = 0;
  4627. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
  4628. orig = data = RREG32(CGTS_SM_CTRL_REG);
  4629. data = 0x96940200;
  4630. if (orig != data)
  4631. WREG32(CGTS_SM_CTRL_REG, data);
  4632. if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
  4633. orig = data = RREG32(CP_MEM_SLP_CNTL);
  4634. data |= CP_MEM_LS_EN;
  4635. if (orig != data)
  4636. WREG32(CP_MEM_SLP_CNTL, data);
  4637. }
  4638. orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
  4639. data &= 0xffffffc0;
  4640. if (orig != data)
  4641. WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
  4642. tmp = si_halt_rlc(rdev);
  4643. WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
  4644. WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
  4645. WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
  4646. si_update_rlc(rdev, tmp);
  4647. } else {
  4648. orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
  4649. data |= 0x00000003;
  4650. if (orig != data)
  4651. WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
  4652. data = RREG32(CP_MEM_SLP_CNTL);
  4653. if (data & CP_MEM_LS_EN) {
  4654. data &= ~CP_MEM_LS_EN;
  4655. WREG32(CP_MEM_SLP_CNTL, data);
  4656. }
  4657. orig = data = RREG32(CGTS_SM_CTRL_REG);
  4658. data |= LS_OVERRIDE | OVERRIDE;
  4659. if (orig != data)
  4660. WREG32(CGTS_SM_CTRL_REG, data);
  4661. tmp = si_halt_rlc(rdev);
  4662. WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
  4663. WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
  4664. WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
  4665. si_update_rlc(rdev, tmp);
  4666. }
  4667. }
  4668. static void si_enable_uvd_mgcg(struct radeon_device *rdev,
  4669. bool enable)
  4670. {
  4671. u32 orig, data, tmp;
  4672. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
  4673. tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
  4674. tmp |= 0x3fff;
  4675. WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
  4676. orig = data = RREG32(UVD_CGC_CTRL);
  4677. data |= DCM;
  4678. if (orig != data)
  4679. WREG32(UVD_CGC_CTRL, data);
  4680. WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
  4681. WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
  4682. } else {
  4683. tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
  4684. tmp &= ~0x3fff;
  4685. WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
  4686. orig = data = RREG32(UVD_CGC_CTRL);
  4687. data &= ~DCM;
  4688. if (orig != data)
  4689. WREG32(UVD_CGC_CTRL, data);
  4690. WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
  4691. WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
  4692. }
  4693. }
  4694. static const u32 mc_cg_registers[] =
  4695. {
  4696. MC_HUB_MISC_HUB_CG,
  4697. MC_HUB_MISC_SIP_CG,
  4698. MC_HUB_MISC_VM_CG,
  4699. MC_XPB_CLK_GAT,
  4700. ATC_MISC_CG,
  4701. MC_CITF_MISC_WR_CG,
  4702. MC_CITF_MISC_RD_CG,
  4703. MC_CITF_MISC_VM_CG,
  4704. VM_L2_CG,
  4705. };
  4706. static void si_enable_mc_ls(struct radeon_device *rdev,
  4707. bool enable)
  4708. {
  4709. int i;
  4710. u32 orig, data;
  4711. for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
  4712. orig = data = RREG32(mc_cg_registers[i]);
  4713. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
  4714. data |= MC_LS_ENABLE;
  4715. else
  4716. data &= ~MC_LS_ENABLE;
  4717. if (data != orig)
  4718. WREG32(mc_cg_registers[i], data);
  4719. }
  4720. }
  4721. static void si_enable_mc_mgcg(struct radeon_device *rdev,
  4722. bool enable)
  4723. {
  4724. int i;
  4725. u32 orig, data;
  4726. for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
  4727. orig = data = RREG32(mc_cg_registers[i]);
  4728. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
  4729. data |= MC_CG_ENABLE;
  4730. else
  4731. data &= ~MC_CG_ENABLE;
  4732. if (data != orig)
  4733. WREG32(mc_cg_registers[i], data);
  4734. }
  4735. }
  4736. static void si_enable_dma_mgcg(struct radeon_device *rdev,
  4737. bool enable)
  4738. {
  4739. u32 orig, data, offset;
  4740. int i;
  4741. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
  4742. for (i = 0; i < 2; i++) {
  4743. if (i == 0)
  4744. offset = DMA0_REGISTER_OFFSET;
  4745. else
  4746. offset = DMA1_REGISTER_OFFSET;
  4747. orig = data = RREG32(DMA_POWER_CNTL + offset);
  4748. data &= ~MEM_POWER_OVERRIDE;
  4749. if (data != orig)
  4750. WREG32(DMA_POWER_CNTL + offset, data);
  4751. WREG32(DMA_CLK_CTRL + offset, 0x00000100);
  4752. }
  4753. } else {
  4754. for (i = 0; i < 2; i++) {
  4755. if (i == 0)
  4756. offset = DMA0_REGISTER_OFFSET;
  4757. else
  4758. offset = DMA1_REGISTER_OFFSET;
  4759. orig = data = RREG32(DMA_POWER_CNTL + offset);
  4760. data |= MEM_POWER_OVERRIDE;
  4761. if (data != orig)
  4762. WREG32(DMA_POWER_CNTL + offset, data);
  4763. orig = data = RREG32(DMA_CLK_CTRL + offset);
  4764. data = 0xff000000;
  4765. if (data != orig)
  4766. WREG32(DMA_CLK_CTRL + offset, data);
  4767. }
  4768. }
  4769. }
  4770. static void si_enable_bif_mgls(struct radeon_device *rdev,
  4771. bool enable)
  4772. {
  4773. u32 orig, data;
  4774. orig = data = RREG32_PCIE(PCIE_CNTL2);
  4775. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
  4776. data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
  4777. REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
  4778. else
  4779. data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
  4780. REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
  4781. if (orig != data)
  4782. WREG32_PCIE(PCIE_CNTL2, data);
  4783. }
  4784. static void si_enable_hdp_mgcg(struct radeon_device *rdev,
  4785. bool enable)
  4786. {
  4787. u32 orig, data;
  4788. orig = data = RREG32(HDP_HOST_PATH_CNTL);
  4789. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
  4790. data &= ~CLOCK_GATING_DIS;
  4791. else
  4792. data |= CLOCK_GATING_DIS;
  4793. if (orig != data)
  4794. WREG32(HDP_HOST_PATH_CNTL, data);
  4795. }
  4796. static void si_enable_hdp_ls(struct radeon_device *rdev,
  4797. bool enable)
  4798. {
  4799. u32 orig, data;
  4800. orig = data = RREG32(HDP_MEM_POWER_LS);
  4801. if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
  4802. data |= HDP_LS_ENABLE;
  4803. else
  4804. data &= ~HDP_LS_ENABLE;
  4805. if (orig != data)
  4806. WREG32(HDP_MEM_POWER_LS, data);
  4807. }
  4808. void si_update_cg(struct radeon_device *rdev,
  4809. u32 block, bool enable)
  4810. {
  4811. if (block & RADEON_CG_BLOCK_GFX) {
  4812. si_enable_gui_idle_interrupt(rdev, false);
  4813. /* order matters! */
  4814. if (enable) {
  4815. si_enable_mgcg(rdev, true);
  4816. si_enable_cgcg(rdev, true);
  4817. } else {
  4818. si_enable_cgcg(rdev, false);
  4819. si_enable_mgcg(rdev, false);
  4820. }
  4821. si_enable_gui_idle_interrupt(rdev, true);
  4822. }
  4823. if (block & RADEON_CG_BLOCK_MC) {
  4824. si_enable_mc_mgcg(rdev, enable);
  4825. si_enable_mc_ls(rdev, enable);
  4826. }
  4827. if (block & RADEON_CG_BLOCK_SDMA) {
  4828. si_enable_dma_mgcg(rdev, enable);
  4829. }
  4830. if (block & RADEON_CG_BLOCK_BIF) {
  4831. si_enable_bif_mgls(rdev, enable);
  4832. }
  4833. if (block & RADEON_CG_BLOCK_UVD) {
  4834. if (rdev->has_uvd) {
  4835. si_enable_uvd_mgcg(rdev, enable);
  4836. }
  4837. }
  4838. if (block & RADEON_CG_BLOCK_HDP) {
  4839. si_enable_hdp_mgcg(rdev, enable);
  4840. si_enable_hdp_ls(rdev, enable);
  4841. }
  4842. }
  4843. static void si_init_cg(struct radeon_device *rdev)
  4844. {
  4845. si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
  4846. RADEON_CG_BLOCK_MC |
  4847. RADEON_CG_BLOCK_SDMA |
  4848. RADEON_CG_BLOCK_BIF |
  4849. RADEON_CG_BLOCK_HDP), true);
  4850. if (rdev->has_uvd) {
  4851. si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
  4852. si_init_uvd_internal_cg(rdev);
  4853. }
  4854. }
  4855. static void si_fini_cg(struct radeon_device *rdev)
  4856. {
  4857. if (rdev->has_uvd) {
  4858. si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
  4859. }
  4860. si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
  4861. RADEON_CG_BLOCK_MC |
  4862. RADEON_CG_BLOCK_SDMA |
  4863. RADEON_CG_BLOCK_BIF |
  4864. RADEON_CG_BLOCK_HDP), false);
  4865. }
  4866. u32 si_get_csb_size(struct radeon_device *rdev)
  4867. {
  4868. u32 count = 0;
  4869. const struct cs_section_def *sect = NULL;
  4870. const struct cs_extent_def *ext = NULL;
  4871. if (rdev->rlc.cs_data == NULL)
  4872. return 0;
  4873. /* begin clear state */
  4874. count += 2;
  4875. /* context control state */
  4876. count += 3;
  4877. for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
  4878. for (ext = sect->section; ext->extent != NULL; ++ext) {
  4879. if (sect->id == SECT_CONTEXT)
  4880. count += 2 + ext->reg_count;
  4881. else
  4882. return 0;
  4883. }
  4884. }
  4885. /* pa_sc_raster_config */
  4886. count += 3;
  4887. /* end clear state */
  4888. count += 2;
  4889. /* clear state */
  4890. count += 2;
  4891. return count;
  4892. }
  4893. void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
  4894. {
  4895. u32 count = 0, i;
  4896. const struct cs_section_def *sect = NULL;
  4897. const struct cs_extent_def *ext = NULL;
  4898. if (rdev->rlc.cs_data == NULL)
  4899. return;
  4900. if (buffer == NULL)
  4901. return;
  4902. buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
  4903. buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE;
  4904. buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);
  4905. buffer[count++] = 0x80000000;
  4906. buffer[count++] = 0x80000000;
  4907. for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
  4908. for (ext = sect->section; ext->extent != NULL; ++ext) {
  4909. if (sect->id == SECT_CONTEXT) {
  4910. buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count);
  4911. buffer[count++] = ext->reg_index - 0xa000;
  4912. for (i = 0; i < ext->reg_count; i++)
  4913. buffer[count++] = ext->extent[i];
  4914. } else {
  4915. return;
  4916. }
  4917. }
  4918. }
  4919. buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
  4920. buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START;
  4921. switch (rdev->family) {
  4922. case CHIP_TAHITI:
  4923. case CHIP_PITCAIRN:
  4924. buffer[count++] = 0x2a00126a;
  4925. break;
  4926. case CHIP_VERDE:
  4927. buffer[count++] = 0x0000124a;
  4928. break;
  4929. case CHIP_OLAND:
  4930. buffer[count++] = 0x00000082;
  4931. break;
  4932. case CHIP_HAINAN:
  4933. buffer[count++] = 0x00000000;
  4934. break;
  4935. default:
  4936. buffer[count++] = 0x00000000;
  4937. break;
  4938. }
  4939. buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
  4940. buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE;
  4941. buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0);
  4942. buffer[count++] = 0;
  4943. }
  4944. static void si_init_pg(struct radeon_device *rdev)
  4945. {
  4946. if (rdev->pg_flags) {
  4947. if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
  4948. si_init_dma_pg(rdev);
  4949. }
  4950. si_init_ao_cu_mask(rdev);
  4951. if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
  4952. si_init_gfx_cgpg(rdev);
  4953. }
  4954. si_enable_dma_pg(rdev, true);
  4955. si_enable_gfx_cgpg(rdev, true);
  4956. } else {
  4957. WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
  4958. WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
  4959. }
  4960. }
  4961. static void si_fini_pg(struct radeon_device *rdev)
  4962. {
  4963. if (rdev->pg_flags) {
  4964. si_enable_dma_pg(rdev, false);
  4965. si_enable_gfx_cgpg(rdev, false);
  4966. }
  4967. }
  4968. /*
  4969. * RLC
  4970. */
  4971. void si_rlc_reset(struct radeon_device *rdev)
  4972. {
  4973. u32 tmp = RREG32(GRBM_SOFT_RESET);
  4974. tmp |= SOFT_RESET_RLC;
  4975. WREG32(GRBM_SOFT_RESET, tmp);
  4976. udelay(50);
  4977. tmp &= ~SOFT_RESET_RLC;
  4978. WREG32(GRBM_SOFT_RESET, tmp);
  4979. udelay(50);
  4980. }
  4981. static void si_rlc_stop(struct radeon_device *rdev)
  4982. {
  4983. WREG32(RLC_CNTL, 0);
  4984. si_enable_gui_idle_interrupt(rdev, false);
  4985. si_wait_for_rlc_serdes(rdev);
  4986. }
  4987. static void si_rlc_start(struct radeon_device *rdev)
  4988. {
  4989. WREG32(RLC_CNTL, RLC_ENABLE);
  4990. si_enable_gui_idle_interrupt(rdev, true);
  4991. udelay(50);
  4992. }
  4993. static bool si_lbpw_supported(struct radeon_device *rdev)
  4994. {
  4995. u32 tmp;
  4996. /* Enable LBPW only for DDR3 */
  4997. tmp = RREG32(MC_SEQ_MISC0);
  4998. if ((tmp & 0xF0000000) == 0xB0000000)
  4999. return true;
  5000. return false;
  5001. }
  5002. static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
  5003. {
  5004. u32 tmp;
  5005. tmp = RREG32(RLC_LB_CNTL);
  5006. if (enable)
  5007. tmp |= LOAD_BALANCE_ENABLE;
  5008. else
  5009. tmp &= ~LOAD_BALANCE_ENABLE;
  5010. WREG32(RLC_LB_CNTL, tmp);
  5011. if (!enable) {
  5012. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  5013. WREG32(SPI_LB_CU_MASK, 0x00ff);
  5014. }
  5015. }
  5016. static int si_rlc_resume(struct radeon_device *rdev)
  5017. {
  5018. u32 i;
  5019. const __be32 *fw_data;
  5020. if (!rdev->rlc_fw)
  5021. return -EINVAL;
  5022. si_rlc_stop(rdev);
  5023. si_rlc_reset(rdev);
  5024. si_init_pg(rdev);
  5025. si_init_cg(rdev);
  5026. WREG32(RLC_RL_BASE, 0);
  5027. WREG32(RLC_RL_SIZE, 0);
  5028. WREG32(RLC_LB_CNTL, 0);
  5029. WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
  5030. WREG32(RLC_LB_CNTR_INIT, 0);
  5031. WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
  5032. WREG32(RLC_MC_CNTL, 0);
  5033. WREG32(RLC_UCODE_CNTL, 0);
  5034. fw_data = (const __be32 *)rdev->rlc_fw->data;
  5035. for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
  5036. WREG32(RLC_UCODE_ADDR, i);
  5037. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  5038. }
  5039. WREG32(RLC_UCODE_ADDR, 0);
  5040. si_enable_lbpw(rdev, si_lbpw_supported(rdev));
  5041. si_rlc_start(rdev);
  5042. return 0;
  5043. }
  5044. static void si_enable_interrupts(struct radeon_device *rdev)
  5045. {
  5046. u32 ih_cntl = RREG32(IH_CNTL);
  5047. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  5048. ih_cntl |= ENABLE_INTR;
  5049. ih_rb_cntl |= IH_RB_ENABLE;
  5050. WREG32(IH_CNTL, ih_cntl);
  5051. WREG32(IH_RB_CNTL, ih_rb_cntl);
  5052. rdev->ih.enabled = true;
  5053. }
  5054. static void si_disable_interrupts(struct radeon_device *rdev)
  5055. {
  5056. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  5057. u32 ih_cntl = RREG32(IH_CNTL);
  5058. ih_rb_cntl &= ~IH_RB_ENABLE;
  5059. ih_cntl &= ~ENABLE_INTR;
  5060. WREG32(IH_RB_CNTL, ih_rb_cntl);
  5061. WREG32(IH_CNTL, ih_cntl);
  5062. /* set rptr, wptr to 0 */
  5063. WREG32(IH_RB_RPTR, 0);
  5064. WREG32(IH_RB_WPTR, 0);
  5065. rdev->ih.enabled = false;
  5066. rdev->ih.rptr = 0;
  5067. }
  5068. static void si_disable_interrupt_state(struct radeon_device *rdev)
  5069. {
  5070. u32 tmp;
  5071. tmp = RREG32(CP_INT_CNTL_RING0) &
  5072. (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  5073. WREG32(CP_INT_CNTL_RING0, tmp);
  5074. WREG32(CP_INT_CNTL_RING1, 0);
  5075. WREG32(CP_INT_CNTL_RING2, 0);
  5076. tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
  5077. WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
  5078. tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
  5079. WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
  5080. WREG32(GRBM_INT_CNTL, 0);
  5081. if (rdev->num_crtc >= 2) {
  5082. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  5083. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  5084. }
  5085. if (rdev->num_crtc >= 4) {
  5086. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  5087. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  5088. }
  5089. if (rdev->num_crtc >= 6) {
  5090. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  5091. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  5092. }
  5093. if (rdev->num_crtc >= 2) {
  5094. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  5095. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  5096. }
  5097. if (rdev->num_crtc >= 4) {
  5098. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  5099. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  5100. }
  5101. if (rdev->num_crtc >= 6) {
  5102. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  5103. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  5104. }
  5105. if (!ASIC_IS_NODCE(rdev)) {
  5106. WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
  5107. tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5108. WREG32(DC_HPD1_INT_CONTROL, tmp);
  5109. tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5110. WREG32(DC_HPD2_INT_CONTROL, tmp);
  5111. tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5112. WREG32(DC_HPD3_INT_CONTROL, tmp);
  5113. tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5114. WREG32(DC_HPD4_INT_CONTROL, tmp);
  5115. tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5116. WREG32(DC_HPD5_INT_CONTROL, tmp);
  5117. tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  5118. WREG32(DC_HPD6_INT_CONTROL, tmp);
  5119. }
  5120. }
  5121. static int si_irq_init(struct radeon_device *rdev)
  5122. {
  5123. int ret = 0;
  5124. int rb_bufsz;
  5125. u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
  5126. /* allocate ring */
  5127. ret = r600_ih_ring_alloc(rdev);
  5128. if (ret)
  5129. return ret;
  5130. /* disable irqs */
  5131. si_disable_interrupts(rdev);
  5132. /* init rlc */
  5133. ret = si_rlc_resume(rdev);
  5134. if (ret) {
  5135. r600_ih_ring_fini(rdev);
  5136. return ret;
  5137. }
  5138. /* setup interrupt control */
  5139. /* set dummy read address to ring address */
  5140. WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
  5141. interrupt_cntl = RREG32(INTERRUPT_CNTL);
  5142. /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
  5143. * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
  5144. */
  5145. interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
  5146. /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
  5147. interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
  5148. WREG32(INTERRUPT_CNTL, interrupt_cntl);
  5149. WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
  5150. rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
  5151. ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
  5152. IH_WPTR_OVERFLOW_CLEAR |
  5153. (rb_bufsz << 1));
  5154. if (rdev->wb.enabled)
  5155. ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
  5156. /* set the writeback address whether it's enabled or not */
  5157. WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
  5158. WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
  5159. WREG32(IH_RB_CNTL, ih_rb_cntl);
  5160. /* set rptr, wptr to 0 */
  5161. WREG32(IH_RB_RPTR, 0);
  5162. WREG32(IH_RB_WPTR, 0);
  5163. /* Default settings for IH_CNTL (disabled at first) */
  5164. ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
  5165. /* RPTR_REARM only works if msi's are enabled */
  5166. if (rdev->msi_enabled)
  5167. ih_cntl |= RPTR_REARM;
  5168. WREG32(IH_CNTL, ih_cntl);
  5169. /* force the active interrupt state to all disabled */
  5170. si_disable_interrupt_state(rdev);
  5171. pci_set_master(rdev->pdev);
  5172. /* enable irqs */
  5173. si_enable_interrupts(rdev);
  5174. return ret;
  5175. }
  5176. int si_irq_set(struct radeon_device *rdev)
  5177. {
  5178. u32 cp_int_cntl;
  5179. u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
  5180. u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
  5181. u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
  5182. u32 grbm_int_cntl = 0;
  5183. u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
  5184. u32 dma_cntl, dma_cntl1;
  5185. u32 thermal_int = 0;
  5186. if (!rdev->irq.installed) {
  5187. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  5188. return -EINVAL;
  5189. }
  5190. /* don't enable anything if the ih is disabled */
  5191. if (!rdev->ih.enabled) {
  5192. si_disable_interrupts(rdev);
  5193. /* force the active interrupt state to all disabled */
  5194. si_disable_interrupt_state(rdev);
  5195. return 0;
  5196. }
  5197. cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
  5198. (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  5199. if (!ASIC_IS_NODCE(rdev)) {
  5200. hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5201. hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5202. hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5203. hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5204. hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5205. hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
  5206. }
  5207. dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
  5208. dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
  5209. thermal_int = RREG32(CG_THERMAL_INT) &
  5210. ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
  5211. /* enable CP interrupts on all rings */
  5212. if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
  5213. DRM_DEBUG("si_irq_set: sw int gfx\n");
  5214. cp_int_cntl |= TIME_STAMP_INT_ENABLE;
  5215. }
  5216. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
  5217. DRM_DEBUG("si_irq_set: sw int cp1\n");
  5218. cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
  5219. }
  5220. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
  5221. DRM_DEBUG("si_irq_set: sw int cp2\n");
  5222. cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
  5223. }
  5224. if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
  5225. DRM_DEBUG("si_irq_set: sw int dma\n");
  5226. dma_cntl |= TRAP_ENABLE;
  5227. }
  5228. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
  5229. DRM_DEBUG("si_irq_set: sw int dma1\n");
  5230. dma_cntl1 |= TRAP_ENABLE;
  5231. }
  5232. if (rdev->irq.crtc_vblank_int[0] ||
  5233. atomic_read(&rdev->irq.pflip[0])) {
  5234. DRM_DEBUG("si_irq_set: vblank 0\n");
  5235. crtc1 |= VBLANK_INT_MASK;
  5236. }
  5237. if (rdev->irq.crtc_vblank_int[1] ||
  5238. atomic_read(&rdev->irq.pflip[1])) {
  5239. DRM_DEBUG("si_irq_set: vblank 1\n");
  5240. crtc2 |= VBLANK_INT_MASK;
  5241. }
  5242. if (rdev->irq.crtc_vblank_int[2] ||
  5243. atomic_read(&rdev->irq.pflip[2])) {
  5244. DRM_DEBUG("si_irq_set: vblank 2\n");
  5245. crtc3 |= VBLANK_INT_MASK;
  5246. }
  5247. if (rdev->irq.crtc_vblank_int[3] ||
  5248. atomic_read(&rdev->irq.pflip[3])) {
  5249. DRM_DEBUG("si_irq_set: vblank 3\n");
  5250. crtc4 |= VBLANK_INT_MASK;
  5251. }
  5252. if (rdev->irq.crtc_vblank_int[4] ||
  5253. atomic_read(&rdev->irq.pflip[4])) {
  5254. DRM_DEBUG("si_irq_set: vblank 4\n");
  5255. crtc5 |= VBLANK_INT_MASK;
  5256. }
  5257. if (rdev->irq.crtc_vblank_int[5] ||
  5258. atomic_read(&rdev->irq.pflip[5])) {
  5259. DRM_DEBUG("si_irq_set: vblank 5\n");
  5260. crtc6 |= VBLANK_INT_MASK;
  5261. }
  5262. if (rdev->irq.hpd[0]) {
  5263. DRM_DEBUG("si_irq_set: hpd 1\n");
  5264. hpd1 |= DC_HPDx_INT_EN;
  5265. }
  5266. if (rdev->irq.hpd[1]) {
  5267. DRM_DEBUG("si_irq_set: hpd 2\n");
  5268. hpd2 |= DC_HPDx_INT_EN;
  5269. }
  5270. if (rdev->irq.hpd[2]) {
  5271. DRM_DEBUG("si_irq_set: hpd 3\n");
  5272. hpd3 |= DC_HPDx_INT_EN;
  5273. }
  5274. if (rdev->irq.hpd[3]) {
  5275. DRM_DEBUG("si_irq_set: hpd 4\n");
  5276. hpd4 |= DC_HPDx_INT_EN;
  5277. }
  5278. if (rdev->irq.hpd[4]) {
  5279. DRM_DEBUG("si_irq_set: hpd 5\n");
  5280. hpd5 |= DC_HPDx_INT_EN;
  5281. }
  5282. if (rdev->irq.hpd[5]) {
  5283. DRM_DEBUG("si_irq_set: hpd 6\n");
  5284. hpd6 |= DC_HPDx_INT_EN;
  5285. }
  5286. WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
  5287. WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
  5288. WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
  5289. WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
  5290. WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
  5291. WREG32(GRBM_INT_CNTL, grbm_int_cntl);
  5292. if (rdev->irq.dpm_thermal) {
  5293. DRM_DEBUG("dpm thermal\n");
  5294. thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
  5295. }
  5296. if (rdev->num_crtc >= 2) {
  5297. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
  5298. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
  5299. }
  5300. if (rdev->num_crtc >= 4) {
  5301. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
  5302. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
  5303. }
  5304. if (rdev->num_crtc >= 6) {
  5305. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
  5306. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
  5307. }
  5308. if (rdev->num_crtc >= 2) {
  5309. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
  5310. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
  5311. }
  5312. if (rdev->num_crtc >= 4) {
  5313. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
  5314. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
  5315. }
  5316. if (rdev->num_crtc >= 6) {
  5317. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
  5318. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
  5319. }
  5320. if (!ASIC_IS_NODCE(rdev)) {
  5321. WREG32(DC_HPD1_INT_CONTROL, hpd1);
  5322. WREG32(DC_HPD2_INT_CONTROL, hpd2);
  5323. WREG32(DC_HPD3_INT_CONTROL, hpd3);
  5324. WREG32(DC_HPD4_INT_CONTROL, hpd4);
  5325. WREG32(DC_HPD5_INT_CONTROL, hpd5);
  5326. WREG32(DC_HPD6_INT_CONTROL, hpd6);
  5327. }
  5328. WREG32(CG_THERMAL_INT, thermal_int);
  5329. return 0;
  5330. }
  5331. static inline void si_irq_ack(struct radeon_device *rdev)
  5332. {
  5333. u32 tmp;
  5334. if (ASIC_IS_NODCE(rdev))
  5335. return;
  5336. rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
  5337. rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
  5338. rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
  5339. rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
  5340. rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
  5341. rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
  5342. rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
  5343. rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
  5344. if (rdev->num_crtc >= 4) {
  5345. rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
  5346. rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
  5347. }
  5348. if (rdev->num_crtc >= 6) {
  5349. rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
  5350. rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
  5351. }
  5352. if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
  5353. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5354. if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
  5355. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5356. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
  5357. WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
  5358. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
  5359. WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
  5360. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
  5361. WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
  5362. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
  5363. WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
  5364. if (rdev->num_crtc >= 4) {
  5365. if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
  5366. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5367. if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
  5368. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5369. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
  5370. WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
  5371. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
  5372. WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
  5373. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
  5374. WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
  5375. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
  5376. WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
  5377. }
  5378. if (rdev->num_crtc >= 6) {
  5379. if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
  5380. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5381. if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
  5382. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  5383. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
  5384. WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
  5385. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
  5386. WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
  5387. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
  5388. WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
  5389. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
  5390. WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
  5391. }
  5392. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  5393. tmp = RREG32(DC_HPD1_INT_CONTROL);
  5394. tmp |= DC_HPDx_INT_ACK;
  5395. WREG32(DC_HPD1_INT_CONTROL, tmp);
  5396. }
  5397. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  5398. tmp = RREG32(DC_HPD2_INT_CONTROL);
  5399. tmp |= DC_HPDx_INT_ACK;
  5400. WREG32(DC_HPD2_INT_CONTROL, tmp);
  5401. }
  5402. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  5403. tmp = RREG32(DC_HPD3_INT_CONTROL);
  5404. tmp |= DC_HPDx_INT_ACK;
  5405. WREG32(DC_HPD3_INT_CONTROL, tmp);
  5406. }
  5407. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  5408. tmp = RREG32(DC_HPD4_INT_CONTROL);
  5409. tmp |= DC_HPDx_INT_ACK;
  5410. WREG32(DC_HPD4_INT_CONTROL, tmp);
  5411. }
  5412. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  5413. tmp = RREG32(DC_HPD5_INT_CONTROL);
  5414. tmp |= DC_HPDx_INT_ACK;
  5415. WREG32(DC_HPD5_INT_CONTROL, tmp);
  5416. }
  5417. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  5418. tmp = RREG32(DC_HPD5_INT_CONTROL);
  5419. tmp |= DC_HPDx_INT_ACK;
  5420. WREG32(DC_HPD6_INT_CONTROL, tmp);
  5421. }
  5422. }
  5423. static void si_irq_disable(struct radeon_device *rdev)
  5424. {
  5425. si_disable_interrupts(rdev);
  5426. /* Wait and acknowledge irq */
  5427. mdelay(1);
  5428. si_irq_ack(rdev);
  5429. si_disable_interrupt_state(rdev);
  5430. }
  5431. static void si_irq_suspend(struct radeon_device *rdev)
  5432. {
  5433. si_irq_disable(rdev);
  5434. si_rlc_stop(rdev);
  5435. }
  5436. static void si_irq_fini(struct radeon_device *rdev)
  5437. {
  5438. si_irq_suspend(rdev);
  5439. r600_ih_ring_fini(rdev);
  5440. }
  5441. static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
  5442. {
  5443. u32 wptr, tmp;
  5444. if (rdev->wb.enabled)
  5445. wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  5446. else
  5447. wptr = RREG32(IH_RB_WPTR);
  5448. if (wptr & RB_OVERFLOW) {
  5449. /* When a ring buffer overflow happen start parsing interrupt
  5450. * from the last not overwritten vector (wptr + 16). Hopefully
  5451. * this should allow us to catchup.
  5452. */
  5453. dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
  5454. wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
  5455. rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
  5456. tmp = RREG32(IH_RB_CNTL);
  5457. tmp |= IH_WPTR_OVERFLOW_CLEAR;
  5458. WREG32(IH_RB_CNTL, tmp);
  5459. }
  5460. return (wptr & rdev->ih.ptr_mask);
  5461. }
  5462. /* SI IV Ring
  5463. * Each IV ring entry is 128 bits:
  5464. * [7:0] - interrupt source id
  5465. * [31:8] - reserved
  5466. * [59:32] - interrupt source data
  5467. * [63:60] - reserved
  5468. * [71:64] - RINGID
  5469. * [79:72] - VMID
  5470. * [127:80] - reserved
  5471. */
  5472. int si_irq_process(struct radeon_device *rdev)
  5473. {
  5474. u32 wptr;
  5475. u32 rptr;
  5476. u32 src_id, src_data, ring_id;
  5477. u32 ring_index;
  5478. bool queue_hotplug = false;
  5479. bool queue_thermal = false;
  5480. u32 status, addr;
  5481. if (!rdev->ih.enabled || rdev->shutdown)
  5482. return IRQ_NONE;
  5483. wptr = si_get_ih_wptr(rdev);
  5484. restart_ih:
  5485. /* is somebody else already processing irqs? */
  5486. if (atomic_xchg(&rdev->ih.lock, 1))
  5487. return IRQ_NONE;
  5488. rptr = rdev->ih.rptr;
  5489. DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
  5490. /* Order reading of wptr vs. reading of IH ring data */
  5491. rmb();
  5492. /* display interrupts */
  5493. si_irq_ack(rdev);
  5494. while (rptr != wptr) {
  5495. /* wptr/rptr are in bytes! */
  5496. ring_index = rptr / 4;
  5497. src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
  5498. src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
  5499. ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
  5500. switch (src_id) {
  5501. case 1: /* D1 vblank/vline */
  5502. switch (src_data) {
  5503. case 0: /* D1 vblank */
  5504. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
  5505. if (rdev->irq.crtc_vblank_int[0]) {
  5506. drm_handle_vblank(rdev->ddev, 0);
  5507. rdev->pm.vblank_sync = true;
  5508. wake_up(&rdev->irq.vblank_queue);
  5509. }
  5510. if (atomic_read(&rdev->irq.pflip[0]))
  5511. radeon_crtc_handle_flip(rdev, 0);
  5512. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
  5513. DRM_DEBUG("IH: D1 vblank\n");
  5514. }
  5515. break;
  5516. case 1: /* D1 vline */
  5517. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
  5518. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
  5519. DRM_DEBUG("IH: D1 vline\n");
  5520. }
  5521. break;
  5522. default:
  5523. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5524. break;
  5525. }
  5526. break;
  5527. case 2: /* D2 vblank/vline */
  5528. switch (src_data) {
  5529. case 0: /* D2 vblank */
  5530. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
  5531. if (rdev->irq.crtc_vblank_int[1]) {
  5532. drm_handle_vblank(rdev->ddev, 1);
  5533. rdev->pm.vblank_sync = true;
  5534. wake_up(&rdev->irq.vblank_queue);
  5535. }
  5536. if (atomic_read(&rdev->irq.pflip[1]))
  5537. radeon_crtc_handle_flip(rdev, 1);
  5538. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
  5539. DRM_DEBUG("IH: D2 vblank\n");
  5540. }
  5541. break;
  5542. case 1: /* D2 vline */
  5543. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
  5544. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
  5545. DRM_DEBUG("IH: D2 vline\n");
  5546. }
  5547. break;
  5548. default:
  5549. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5550. break;
  5551. }
  5552. break;
  5553. case 3: /* D3 vblank/vline */
  5554. switch (src_data) {
  5555. case 0: /* D3 vblank */
  5556. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
  5557. if (rdev->irq.crtc_vblank_int[2]) {
  5558. drm_handle_vblank(rdev->ddev, 2);
  5559. rdev->pm.vblank_sync = true;
  5560. wake_up(&rdev->irq.vblank_queue);
  5561. }
  5562. if (atomic_read(&rdev->irq.pflip[2]))
  5563. radeon_crtc_handle_flip(rdev, 2);
  5564. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
  5565. DRM_DEBUG("IH: D3 vblank\n");
  5566. }
  5567. break;
  5568. case 1: /* D3 vline */
  5569. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
  5570. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
  5571. DRM_DEBUG("IH: D3 vline\n");
  5572. }
  5573. break;
  5574. default:
  5575. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5576. break;
  5577. }
  5578. break;
  5579. case 4: /* D4 vblank/vline */
  5580. switch (src_data) {
  5581. case 0: /* D4 vblank */
  5582. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
  5583. if (rdev->irq.crtc_vblank_int[3]) {
  5584. drm_handle_vblank(rdev->ddev, 3);
  5585. rdev->pm.vblank_sync = true;
  5586. wake_up(&rdev->irq.vblank_queue);
  5587. }
  5588. if (atomic_read(&rdev->irq.pflip[3]))
  5589. radeon_crtc_handle_flip(rdev, 3);
  5590. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
  5591. DRM_DEBUG("IH: D4 vblank\n");
  5592. }
  5593. break;
  5594. case 1: /* D4 vline */
  5595. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
  5596. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
  5597. DRM_DEBUG("IH: D4 vline\n");
  5598. }
  5599. break;
  5600. default:
  5601. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5602. break;
  5603. }
  5604. break;
  5605. case 5: /* D5 vblank/vline */
  5606. switch (src_data) {
  5607. case 0: /* D5 vblank */
  5608. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
  5609. if (rdev->irq.crtc_vblank_int[4]) {
  5610. drm_handle_vblank(rdev->ddev, 4);
  5611. rdev->pm.vblank_sync = true;
  5612. wake_up(&rdev->irq.vblank_queue);
  5613. }
  5614. if (atomic_read(&rdev->irq.pflip[4]))
  5615. radeon_crtc_handle_flip(rdev, 4);
  5616. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
  5617. DRM_DEBUG("IH: D5 vblank\n");
  5618. }
  5619. break;
  5620. case 1: /* D5 vline */
  5621. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
  5622. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
  5623. DRM_DEBUG("IH: D5 vline\n");
  5624. }
  5625. break;
  5626. default:
  5627. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5628. break;
  5629. }
  5630. break;
  5631. case 6: /* D6 vblank/vline */
  5632. switch (src_data) {
  5633. case 0: /* D6 vblank */
  5634. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
  5635. if (rdev->irq.crtc_vblank_int[5]) {
  5636. drm_handle_vblank(rdev->ddev, 5);
  5637. rdev->pm.vblank_sync = true;
  5638. wake_up(&rdev->irq.vblank_queue);
  5639. }
  5640. if (atomic_read(&rdev->irq.pflip[5]))
  5641. radeon_crtc_handle_flip(rdev, 5);
  5642. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
  5643. DRM_DEBUG("IH: D6 vblank\n");
  5644. }
  5645. break;
  5646. case 1: /* D6 vline */
  5647. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
  5648. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
  5649. DRM_DEBUG("IH: D6 vline\n");
  5650. }
  5651. break;
  5652. default:
  5653. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5654. break;
  5655. }
  5656. break;
  5657. case 42: /* HPD hotplug */
  5658. switch (src_data) {
  5659. case 0:
  5660. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  5661. rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
  5662. queue_hotplug = true;
  5663. DRM_DEBUG("IH: HPD1\n");
  5664. }
  5665. break;
  5666. case 1:
  5667. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  5668. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
  5669. queue_hotplug = true;
  5670. DRM_DEBUG("IH: HPD2\n");
  5671. }
  5672. break;
  5673. case 2:
  5674. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  5675. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
  5676. queue_hotplug = true;
  5677. DRM_DEBUG("IH: HPD3\n");
  5678. }
  5679. break;
  5680. case 3:
  5681. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  5682. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
  5683. queue_hotplug = true;
  5684. DRM_DEBUG("IH: HPD4\n");
  5685. }
  5686. break;
  5687. case 4:
  5688. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  5689. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
  5690. queue_hotplug = true;
  5691. DRM_DEBUG("IH: HPD5\n");
  5692. }
  5693. break;
  5694. case 5:
  5695. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  5696. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
  5697. queue_hotplug = true;
  5698. DRM_DEBUG("IH: HPD6\n");
  5699. }
  5700. break;
  5701. default:
  5702. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5703. break;
  5704. }
  5705. break;
  5706. case 146:
  5707. case 147:
  5708. addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
  5709. status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
  5710. dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
  5711. dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
  5712. addr);
  5713. dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
  5714. status);
  5715. si_vm_decode_fault(rdev, status, addr);
  5716. /* reset addr and status */
  5717. WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
  5718. break;
  5719. case 176: /* RINGID0 CP_INT */
  5720. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  5721. break;
  5722. case 177: /* RINGID1 CP_INT */
  5723. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  5724. break;
  5725. case 178: /* RINGID2 CP_INT */
  5726. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  5727. break;
  5728. case 181: /* CP EOP event */
  5729. DRM_DEBUG("IH: CP EOP\n");
  5730. switch (ring_id) {
  5731. case 0:
  5732. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  5733. break;
  5734. case 1:
  5735. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  5736. break;
  5737. case 2:
  5738. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  5739. break;
  5740. }
  5741. break;
  5742. case 224: /* DMA trap event */
  5743. DRM_DEBUG("IH: DMA trap\n");
  5744. radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
  5745. break;
  5746. case 230: /* thermal low to high */
  5747. DRM_DEBUG("IH: thermal low to high\n");
  5748. rdev->pm.dpm.thermal.high_to_low = false;
  5749. queue_thermal = true;
  5750. break;
  5751. case 231: /* thermal high to low */
  5752. DRM_DEBUG("IH: thermal high to low\n");
  5753. rdev->pm.dpm.thermal.high_to_low = true;
  5754. queue_thermal = true;
  5755. break;
  5756. case 233: /* GUI IDLE */
  5757. DRM_DEBUG("IH: GUI idle\n");
  5758. break;
  5759. case 244: /* DMA trap event */
  5760. DRM_DEBUG("IH: DMA1 trap\n");
  5761. radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
  5762. break;
  5763. default:
  5764. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  5765. break;
  5766. }
  5767. /* wptr/rptr are in bytes! */
  5768. rptr += 16;
  5769. rptr &= rdev->ih.ptr_mask;
  5770. }
  5771. if (queue_hotplug)
  5772. schedule_work(&rdev->hotplug_work);
  5773. if (queue_thermal && rdev->pm.dpm_enabled)
  5774. schedule_work(&rdev->pm.dpm.thermal.work);
  5775. rdev->ih.rptr = rptr;
  5776. WREG32(IH_RB_RPTR, rdev->ih.rptr);
  5777. atomic_set(&rdev->ih.lock, 0);
  5778. /* make sure wptr hasn't changed while processing */
  5779. wptr = si_get_ih_wptr(rdev);
  5780. if (wptr != rptr)
  5781. goto restart_ih;
  5782. return IRQ_HANDLED;
  5783. }
  5784. /*
  5785. * startup/shutdown callbacks
  5786. */
  5787. static int si_startup(struct radeon_device *rdev)
  5788. {
  5789. struct radeon_ring *ring;
  5790. int r;
  5791. /* enable pcie gen2/3 link */
  5792. si_pcie_gen3_enable(rdev);
  5793. /* enable aspm */
  5794. si_program_aspm(rdev);
  5795. /* scratch needs to be initialized before MC */
  5796. r = r600_vram_scratch_init(rdev);
  5797. if (r)
  5798. return r;
  5799. si_mc_program(rdev);
  5800. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
  5801. !rdev->rlc_fw || !rdev->mc_fw) {
  5802. r = si_init_microcode(rdev);
  5803. if (r) {
  5804. DRM_ERROR("Failed to load firmware!\n");
  5805. return r;
  5806. }
  5807. }
  5808. r = si_mc_load_microcode(rdev);
  5809. if (r) {
  5810. DRM_ERROR("Failed to load MC firmware!\n");
  5811. return r;
  5812. }
  5813. r = si_pcie_gart_enable(rdev);
  5814. if (r)
  5815. return r;
  5816. si_gpu_init(rdev);
  5817. /* allocate rlc buffers */
  5818. if (rdev->family == CHIP_VERDE) {
  5819. rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
  5820. rdev->rlc.reg_list_size =
  5821. (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
  5822. }
  5823. rdev->rlc.cs_data = si_cs_data;
  5824. r = sumo_rlc_init(rdev);
  5825. if (r) {
  5826. DRM_ERROR("Failed to init rlc BOs!\n");
  5827. return r;
  5828. }
  5829. /* allocate wb buffer */
  5830. r = radeon_wb_init(rdev);
  5831. if (r)
  5832. return r;
  5833. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  5834. if (r) {
  5835. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  5836. return r;
  5837. }
  5838. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  5839. if (r) {
  5840. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  5841. return r;
  5842. }
  5843. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  5844. if (r) {
  5845. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  5846. return r;
  5847. }
  5848. r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
  5849. if (r) {
  5850. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  5851. return r;
  5852. }
  5853. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
  5854. if (r) {
  5855. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  5856. return r;
  5857. }
  5858. if (rdev->has_uvd) {
  5859. r = uvd_v2_2_resume(rdev);
  5860. if (!r) {
  5861. r = radeon_fence_driver_start_ring(rdev,
  5862. R600_RING_TYPE_UVD_INDEX);
  5863. if (r)
  5864. dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
  5865. }
  5866. if (r)
  5867. rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
  5868. }
  5869. /* Enable IRQ */
  5870. if (!rdev->irq.installed) {
  5871. r = radeon_irq_kms_init(rdev);
  5872. if (r)
  5873. return r;
  5874. }
  5875. r = si_irq_init(rdev);
  5876. if (r) {
  5877. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  5878. radeon_irq_kms_fini(rdev);
  5879. return r;
  5880. }
  5881. si_irq_set(rdev);
  5882. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  5883. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  5884. CP_RB0_RPTR, CP_RB0_WPTR,
  5885. RADEON_CP_PACKET2);
  5886. if (r)
  5887. return r;
  5888. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  5889. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
  5890. CP_RB1_RPTR, CP_RB1_WPTR,
  5891. RADEON_CP_PACKET2);
  5892. if (r)
  5893. return r;
  5894. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  5895. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
  5896. CP_RB2_RPTR, CP_RB2_WPTR,
  5897. RADEON_CP_PACKET2);
  5898. if (r)
  5899. return r;
  5900. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  5901. r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
  5902. DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
  5903. DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
  5904. DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
  5905. if (r)
  5906. return r;
  5907. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  5908. r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
  5909. DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
  5910. DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
  5911. DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
  5912. if (r)
  5913. return r;
  5914. r = si_cp_load_microcode(rdev);
  5915. if (r)
  5916. return r;
  5917. r = si_cp_resume(rdev);
  5918. if (r)
  5919. return r;
  5920. r = cayman_dma_resume(rdev);
  5921. if (r)
  5922. return r;
  5923. if (rdev->has_uvd) {
  5924. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  5925. if (ring->ring_size) {
  5926. r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
  5927. UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
  5928. RADEON_CP_PACKET2);
  5929. if (!r)
  5930. r = uvd_v1_0_init(rdev);
  5931. if (r)
  5932. DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
  5933. }
  5934. }
  5935. r = radeon_ib_pool_init(rdev);
  5936. if (r) {
  5937. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  5938. return r;
  5939. }
  5940. r = radeon_vm_manager_init(rdev);
  5941. if (r) {
  5942. dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
  5943. return r;
  5944. }
  5945. r = dce6_audio_init(rdev);
  5946. if (r)
  5947. return r;
  5948. return 0;
  5949. }
  5950. int si_resume(struct radeon_device *rdev)
  5951. {
  5952. int r;
  5953. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  5954. * posting will perform necessary task to bring back GPU into good
  5955. * shape.
  5956. */
  5957. /* post card */
  5958. atom_asic_init(rdev->mode_info.atom_context);
  5959. /* init golden registers */
  5960. si_init_golden_registers(rdev);
  5961. rdev->accel_working = true;
  5962. r = si_startup(rdev);
  5963. if (r) {
  5964. DRM_ERROR("si startup failed on resume\n");
  5965. rdev->accel_working = false;
  5966. return r;
  5967. }
  5968. return r;
  5969. }
  5970. int si_suspend(struct radeon_device *rdev)
  5971. {
  5972. dce6_audio_fini(rdev);
  5973. radeon_vm_manager_fini(rdev);
  5974. si_cp_enable(rdev, false);
  5975. cayman_dma_stop(rdev);
  5976. if (rdev->has_uvd) {
  5977. uvd_v1_0_fini(rdev);
  5978. radeon_uvd_suspend(rdev);
  5979. }
  5980. si_fini_pg(rdev);
  5981. si_fini_cg(rdev);
  5982. si_irq_suspend(rdev);
  5983. radeon_wb_disable(rdev);
  5984. si_pcie_gart_disable(rdev);
  5985. return 0;
  5986. }
  5987. /* Plan is to move initialization in that function and use
  5988. * helper function so that radeon_device_init pretty much
  5989. * do nothing more than calling asic specific function. This
  5990. * should also allow to remove a bunch of callback function
  5991. * like vram_info.
  5992. */
  5993. int si_init(struct radeon_device *rdev)
  5994. {
  5995. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  5996. int r;
  5997. /* Read BIOS */
  5998. if (!radeon_get_bios(rdev)) {
  5999. if (ASIC_IS_AVIVO(rdev))
  6000. return -EINVAL;
  6001. }
  6002. /* Must be an ATOMBIOS */
  6003. if (!rdev->is_atom_bios) {
  6004. dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
  6005. return -EINVAL;
  6006. }
  6007. r = radeon_atombios_init(rdev);
  6008. if (r)
  6009. return r;
  6010. /* Post card if necessary */
  6011. if (!radeon_card_posted(rdev)) {
  6012. if (!rdev->bios) {
  6013. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  6014. return -EINVAL;
  6015. }
  6016. DRM_INFO("GPU not posted. posting now...\n");
  6017. atom_asic_init(rdev->mode_info.atom_context);
  6018. }
  6019. /* init golden registers */
  6020. si_init_golden_registers(rdev);
  6021. /* Initialize scratch registers */
  6022. si_scratch_init(rdev);
  6023. /* Initialize surface registers */
  6024. radeon_surface_init(rdev);
  6025. /* Initialize clocks */
  6026. radeon_get_clock_info(rdev->ddev);
  6027. /* Fence driver */
  6028. r = radeon_fence_driver_init(rdev);
  6029. if (r)
  6030. return r;
  6031. /* initialize memory controller */
  6032. r = si_mc_init(rdev);
  6033. if (r)
  6034. return r;
  6035. /* Memory manager */
  6036. r = radeon_bo_init(rdev);
  6037. if (r)
  6038. return r;
  6039. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  6040. ring->ring_obj = NULL;
  6041. r600_ring_init(rdev, ring, 1024 * 1024);
  6042. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  6043. ring->ring_obj = NULL;
  6044. r600_ring_init(rdev, ring, 1024 * 1024);
  6045. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  6046. ring->ring_obj = NULL;
  6047. r600_ring_init(rdev, ring, 1024 * 1024);
  6048. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  6049. ring->ring_obj = NULL;
  6050. r600_ring_init(rdev, ring, 64 * 1024);
  6051. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  6052. ring->ring_obj = NULL;
  6053. r600_ring_init(rdev, ring, 64 * 1024);
  6054. if (rdev->has_uvd) {
  6055. r = radeon_uvd_init(rdev);
  6056. if (!r) {
  6057. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  6058. ring->ring_obj = NULL;
  6059. r600_ring_init(rdev, ring, 4096);
  6060. }
  6061. }
  6062. rdev->ih.ring_obj = NULL;
  6063. r600_ih_ring_init(rdev, 64 * 1024);
  6064. r = r600_pcie_gart_init(rdev);
  6065. if (r)
  6066. return r;
  6067. rdev->accel_working = true;
  6068. r = si_startup(rdev);
  6069. if (r) {
  6070. dev_err(rdev->dev, "disabling GPU acceleration\n");
  6071. si_cp_fini(rdev);
  6072. cayman_dma_fini(rdev);
  6073. si_irq_fini(rdev);
  6074. sumo_rlc_fini(rdev);
  6075. radeon_wb_fini(rdev);
  6076. radeon_ib_pool_fini(rdev);
  6077. radeon_vm_manager_fini(rdev);
  6078. radeon_irq_kms_fini(rdev);
  6079. si_pcie_gart_fini(rdev);
  6080. rdev->accel_working = false;
  6081. }
  6082. /* Don't start up if the MC ucode is missing.
  6083. * The default clocks and voltages before the MC ucode
  6084. * is loaded are not suffient for advanced operations.
  6085. */
  6086. if (!rdev->mc_fw) {
  6087. DRM_ERROR("radeon: MC ucode required for NI+.\n");
  6088. return -EINVAL;
  6089. }
  6090. return 0;
  6091. }
  6092. void si_fini(struct radeon_device *rdev)
  6093. {
  6094. si_cp_fini(rdev);
  6095. cayman_dma_fini(rdev);
  6096. si_fini_pg(rdev);
  6097. si_fini_cg(rdev);
  6098. si_irq_fini(rdev);
  6099. sumo_rlc_fini(rdev);
  6100. radeon_wb_fini(rdev);
  6101. radeon_vm_manager_fini(rdev);
  6102. radeon_ib_pool_fini(rdev);
  6103. radeon_irq_kms_fini(rdev);
  6104. if (rdev->has_uvd) {
  6105. uvd_v1_0_fini(rdev);
  6106. radeon_uvd_fini(rdev);
  6107. }
  6108. si_pcie_gart_fini(rdev);
  6109. r600_vram_scratch_fini(rdev);
  6110. radeon_gem_fini(rdev);
  6111. radeon_fence_driver_fini(rdev);
  6112. radeon_bo_fini(rdev);
  6113. radeon_atombios_fini(rdev);
  6114. kfree(rdev->bios);
  6115. rdev->bios = NULL;
  6116. }
  6117. /**
  6118. * si_get_gpu_clock_counter - return GPU clock counter snapshot
  6119. *
  6120. * @rdev: radeon_device pointer
  6121. *
  6122. * Fetches a GPU clock counter snapshot (SI).
  6123. * Returns the 64 bit clock counter snapshot.
  6124. */
  6125. uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
  6126. {
  6127. uint64_t clock;
  6128. mutex_lock(&rdev->gpu_clock_mutex);
  6129. WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
  6130. clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
  6131. ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
  6132. mutex_unlock(&rdev->gpu_clock_mutex);
  6133. return clock;
  6134. }
  6135. int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  6136. {
  6137. unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  6138. int r;
  6139. /* bypass vclk and dclk with bclk */
  6140. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  6141. VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  6142. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  6143. /* put PLL in bypass mode */
  6144. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  6145. if (!vclk || !dclk) {
  6146. /* keep the Bypass mode, put PLL to sleep */
  6147. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  6148. return 0;
  6149. }
  6150. r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
  6151. 16384, 0x03FFFFFF, 0, 128, 5,
  6152. &fb_div, &vclk_div, &dclk_div);
  6153. if (r)
  6154. return r;
  6155. /* set RESET_ANTI_MUX to 0 */
  6156. WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
  6157. /* set VCO_MODE to 1 */
  6158. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
  6159. /* toggle UPLL_SLEEP to 1 then back to 0 */
  6160. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  6161. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
  6162. /* deassert UPLL_RESET */
  6163. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
  6164. mdelay(1);
  6165. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  6166. if (r)
  6167. return r;
  6168. /* assert UPLL_RESET again */
  6169. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  6170. /* disable spread spectrum. */
  6171. WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
  6172. /* set feedback divider */
  6173. WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
  6174. /* set ref divider to 0 */
  6175. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
  6176. if (fb_div < 307200)
  6177. WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
  6178. else
  6179. WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
  6180. /* set PDIV_A and PDIV_B */
  6181. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  6182. UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
  6183. ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
  6184. /* give the PLL some time to settle */
  6185. mdelay(15);
  6186. /* deassert PLL_RESET */
  6187. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
  6188. mdelay(15);
  6189. /* switch from bypass mode to normal mode */
  6190. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
  6191. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  6192. if (r)
  6193. return r;
  6194. /* switch VCLK and DCLK selection */
  6195. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  6196. VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
  6197. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  6198. mdelay(100);
  6199. return 0;
  6200. }
  6201. static void si_pcie_gen3_enable(struct radeon_device *rdev)
  6202. {
  6203. struct pci_dev *root = rdev->pdev->bus->self;
  6204. int bridge_pos, gpu_pos;
  6205. u32 speed_cntl, mask, current_data_rate;
  6206. int ret, i;
  6207. u16 tmp16;
  6208. if (radeon_pcie_gen2 == 0)
  6209. return;
  6210. if (rdev->flags & RADEON_IS_IGP)
  6211. return;
  6212. if (!(rdev->flags & RADEON_IS_PCIE))
  6213. return;
  6214. ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
  6215. if (ret != 0)
  6216. return;
  6217. if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
  6218. return;
  6219. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  6220. current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
  6221. LC_CURRENT_DATA_RATE_SHIFT;
  6222. if (mask & DRM_PCIE_SPEED_80) {
  6223. if (current_data_rate == 2) {
  6224. DRM_INFO("PCIE gen 3 link speeds already enabled\n");
  6225. return;
  6226. }
  6227. DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
  6228. } else if (mask & DRM_PCIE_SPEED_50) {
  6229. if (current_data_rate == 1) {
  6230. DRM_INFO("PCIE gen 2 link speeds already enabled\n");
  6231. return;
  6232. }
  6233. DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
  6234. }
  6235. bridge_pos = pci_pcie_cap(root);
  6236. if (!bridge_pos)
  6237. return;
  6238. gpu_pos = pci_pcie_cap(rdev->pdev);
  6239. if (!gpu_pos)
  6240. return;
  6241. if (mask & DRM_PCIE_SPEED_80) {
  6242. /* re-try equalization if gen3 is not already enabled */
  6243. if (current_data_rate != 2) {
  6244. u16 bridge_cfg, gpu_cfg;
  6245. u16 bridge_cfg2, gpu_cfg2;
  6246. u32 max_lw, current_lw, tmp;
  6247. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
  6248. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
  6249. tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
  6250. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
  6251. tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
  6252. pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
  6253. tmp = RREG32_PCIE(PCIE_LC_STATUS1);
  6254. max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
  6255. current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
  6256. if (current_lw < max_lw) {
  6257. tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  6258. if (tmp & LC_RENEGOTIATION_SUPPORT) {
  6259. tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
  6260. tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
  6261. tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
  6262. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
  6263. }
  6264. }
  6265. for (i = 0; i < 10; i++) {
  6266. /* check status */
  6267. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
  6268. if (tmp16 & PCI_EXP_DEVSTA_TRPND)
  6269. break;
  6270. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
  6271. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
  6272. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
  6273. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
  6274. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  6275. tmp |= LC_SET_QUIESCE;
  6276. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  6277. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  6278. tmp |= LC_REDO_EQ;
  6279. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  6280. mdelay(100);
  6281. /* linkctl */
  6282. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
  6283. tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
  6284. tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
  6285. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
  6286. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
  6287. tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
  6288. tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
  6289. pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
  6290. /* linkctl2 */
  6291. pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
  6292. tmp16 &= ~((1 << 4) | (7 << 9));
  6293. tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
  6294. pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
  6295. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
  6296. tmp16 &= ~((1 << 4) | (7 << 9));
  6297. tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
  6298. pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
  6299. tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
  6300. tmp &= ~LC_SET_QUIESCE;
  6301. WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
  6302. }
  6303. }
  6304. }
  6305. /* set the link speed */
  6306. speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
  6307. speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
  6308. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  6309. pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
  6310. tmp16 &= ~0xf;
  6311. if (mask & DRM_PCIE_SPEED_80)
  6312. tmp16 |= 3; /* gen3 */
  6313. else if (mask & DRM_PCIE_SPEED_50)
  6314. tmp16 |= 2; /* gen2 */
  6315. else
  6316. tmp16 |= 1; /* gen1 */
  6317. pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
  6318. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  6319. speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
  6320. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  6321. for (i = 0; i < rdev->usec_timeout; i++) {
  6322. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  6323. if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
  6324. break;
  6325. udelay(1);
  6326. }
  6327. }
  6328. static void si_program_aspm(struct radeon_device *rdev)
  6329. {
  6330. u32 data, orig;
  6331. bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
  6332. bool disable_clkreq = false;
  6333. if (radeon_aspm == 0)
  6334. return;
  6335. if (!(rdev->flags & RADEON_IS_PCIE))
  6336. return;
  6337. orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
  6338. data &= ~LC_XMIT_N_FTS_MASK;
  6339. data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
  6340. if (orig != data)
  6341. WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
  6342. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
  6343. data |= LC_GO_TO_RECOVERY;
  6344. if (orig != data)
  6345. WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
  6346. orig = data = RREG32_PCIE(PCIE_P_CNTL);
  6347. data |= P_IGNORE_EDB_ERR;
  6348. if (orig != data)
  6349. WREG32_PCIE(PCIE_P_CNTL, data);
  6350. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
  6351. data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
  6352. data |= LC_PMI_TO_L1_DIS;
  6353. if (!disable_l0s)
  6354. data |= LC_L0S_INACTIVITY(7);
  6355. if (!disable_l1) {
  6356. data |= LC_L1_INACTIVITY(7);
  6357. data &= ~LC_PMI_TO_L1_DIS;
  6358. if (orig != data)
  6359. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  6360. if (!disable_plloff_in_l1) {
  6361. bool clk_req_support;
  6362. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
  6363. data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
  6364. data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
  6365. if (orig != data)
  6366. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
  6367. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
  6368. data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
  6369. data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
  6370. if (orig != data)
  6371. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
  6372. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
  6373. data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
  6374. data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
  6375. if (orig != data)
  6376. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
  6377. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
  6378. data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
  6379. data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
  6380. if (orig != data)
  6381. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
  6382. if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
  6383. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
  6384. data &= ~PLL_RAMP_UP_TIME_0_MASK;
  6385. if (orig != data)
  6386. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
  6387. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
  6388. data &= ~PLL_RAMP_UP_TIME_1_MASK;
  6389. if (orig != data)
  6390. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
  6391. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
  6392. data &= ~PLL_RAMP_UP_TIME_2_MASK;
  6393. if (orig != data)
  6394. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
  6395. orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
  6396. data &= ~PLL_RAMP_UP_TIME_3_MASK;
  6397. if (orig != data)
  6398. WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
  6399. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
  6400. data &= ~PLL_RAMP_UP_TIME_0_MASK;
  6401. if (orig != data)
  6402. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
  6403. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
  6404. data &= ~PLL_RAMP_UP_TIME_1_MASK;
  6405. if (orig != data)
  6406. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
  6407. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
  6408. data &= ~PLL_RAMP_UP_TIME_2_MASK;
  6409. if (orig != data)
  6410. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
  6411. orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
  6412. data &= ~PLL_RAMP_UP_TIME_3_MASK;
  6413. if (orig != data)
  6414. WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
  6415. }
  6416. orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  6417. data &= ~LC_DYN_LANES_PWR_STATE_MASK;
  6418. data |= LC_DYN_LANES_PWR_STATE(3);
  6419. if (orig != data)
  6420. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
  6421. orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
  6422. data &= ~LS2_EXIT_TIME_MASK;
  6423. if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
  6424. data |= LS2_EXIT_TIME(5);
  6425. if (orig != data)
  6426. WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
  6427. orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
  6428. data &= ~LS2_EXIT_TIME_MASK;
  6429. if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
  6430. data |= LS2_EXIT_TIME(5);
  6431. if (orig != data)
  6432. WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
  6433. if (!disable_clkreq) {
  6434. struct pci_dev *root = rdev->pdev->bus->self;
  6435. u32 lnkcap;
  6436. clk_req_support = false;
  6437. pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
  6438. if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
  6439. clk_req_support = true;
  6440. } else {
  6441. clk_req_support = false;
  6442. }
  6443. if (clk_req_support) {
  6444. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
  6445. data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
  6446. if (orig != data)
  6447. WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
  6448. orig = data = RREG32(THM_CLK_CNTL);
  6449. data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
  6450. data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
  6451. if (orig != data)
  6452. WREG32(THM_CLK_CNTL, data);
  6453. orig = data = RREG32(MISC_CLK_CNTL);
  6454. data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
  6455. data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
  6456. if (orig != data)
  6457. WREG32(MISC_CLK_CNTL, data);
  6458. orig = data = RREG32(CG_CLKPIN_CNTL);
  6459. data &= ~BCLK_AS_XCLK;
  6460. if (orig != data)
  6461. WREG32(CG_CLKPIN_CNTL, data);
  6462. orig = data = RREG32(CG_CLKPIN_CNTL_2);
  6463. data &= ~FORCE_BIF_REFCLK_EN;
  6464. if (orig != data)
  6465. WREG32(CG_CLKPIN_CNTL_2, data);
  6466. orig = data = RREG32(MPLL_BYPASSCLK_SEL);
  6467. data &= ~MPLL_CLKOUT_SEL_MASK;
  6468. data |= MPLL_CLKOUT_SEL(4);
  6469. if (orig != data)
  6470. WREG32(MPLL_BYPASSCLK_SEL, data);
  6471. orig = data = RREG32(SPLL_CNTL_MODE);
  6472. data &= ~SPLL_REFCLK_SEL_MASK;
  6473. if (orig != data)
  6474. WREG32(SPLL_CNTL_MODE, data);
  6475. }
  6476. }
  6477. } else {
  6478. if (orig != data)
  6479. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  6480. }
  6481. orig = data = RREG32_PCIE(PCIE_CNTL2);
  6482. data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
  6483. if (orig != data)
  6484. WREG32_PCIE(PCIE_CNTL2, data);
  6485. if (!disable_l0s) {
  6486. data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
  6487. if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
  6488. data = RREG32_PCIE(PCIE_LC_STATUS1);
  6489. if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
  6490. orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
  6491. data &= ~LC_L0S_INACTIVITY_MASK;
  6492. if (orig != data)
  6493. WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
  6494. }
  6495. }
  6496. }
  6497. }