rv770.c 58 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016
  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/firmware.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include "radeon.h"
  33. #include "radeon_asic.h"
  34. #include <drm/radeon_drm.h>
  35. #include "rv770d.h"
  36. #include "atom.h"
  37. #include "avivod.h"
  38. #define R700_PFP_UCODE_SIZE 848
  39. #define R700_PM4_UCODE_SIZE 1360
  40. static void rv770_gpu_init(struct radeon_device *rdev);
  41. void rv770_fini(struct radeon_device *rdev);
  42. static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  43. int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  44. int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  45. {
  46. unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  47. int r;
  48. /* RV740 uses evergreen uvd clk programming */
  49. if (rdev->family == CHIP_RV740)
  50. return evergreen_set_uvd_clocks(rdev, vclk, dclk);
  51. /* bypass vclk and dclk with bclk */
  52. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  53. VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  54. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  55. if (!vclk || !dclk) {
  56. /* keep the Bypass mode, put PLL to sleep */
  57. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  58. return 0;
  59. }
  60. r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
  61. 43663, 0x03FFFFFE, 1, 30, ~0,
  62. &fb_div, &vclk_div, &dclk_div);
  63. if (r)
  64. return r;
  65. fb_div |= 1;
  66. vclk_div -= 1;
  67. dclk_div -= 1;
  68. /* set UPLL_FB_DIV to 0x50000 */
  69. WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
  70. /* deassert UPLL_RESET and UPLL_SLEEP */
  71. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
  72. /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
  73. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  74. WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
  75. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  76. if (r)
  77. return r;
  78. /* assert PLL_RESET */
  79. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  80. /* set the required FB_DIV, REF_DIV, Post divder values */
  81. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
  82. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  83. UPLL_SW_HILEN(vclk_div >> 1) |
  84. UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
  85. UPLL_SW_HILEN2(dclk_div >> 1) |
  86. UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
  87. ~UPLL_SW_MASK);
  88. WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
  89. ~UPLL_FB_DIV_MASK);
  90. /* give the PLL some time to settle */
  91. mdelay(15);
  92. /* deassert PLL_RESET */
  93. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
  94. mdelay(15);
  95. /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
  96. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
  97. WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
  98. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  99. if (r)
  100. return r;
  101. /* switch VCLK and DCLK selection */
  102. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  103. VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
  104. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  105. mdelay(100);
  106. return 0;
  107. }
  108. static const u32 r7xx_golden_registers[] =
  109. {
  110. 0x8d00, 0xffffffff, 0x0e0e0074,
  111. 0x8d04, 0xffffffff, 0x013a2b34,
  112. 0x9508, 0xffffffff, 0x00000002,
  113. 0x8b20, 0xffffffff, 0,
  114. 0x88c4, 0xffffffff, 0x000000c2,
  115. 0x28350, 0xffffffff, 0,
  116. 0x9058, 0xffffffff, 0x0fffc40f,
  117. 0x240c, 0xffffffff, 0x00000380,
  118. 0x733c, 0xffffffff, 0x00000002,
  119. 0x2650, 0x00040000, 0,
  120. 0x20bc, 0x00040000, 0,
  121. 0x7300, 0xffffffff, 0x001000f0
  122. };
  123. static const u32 r7xx_golden_dyn_gpr_registers[] =
  124. {
  125. 0x8db0, 0xffffffff, 0x98989898,
  126. 0x8db4, 0xffffffff, 0x98989898,
  127. 0x8db8, 0xffffffff, 0x98989898,
  128. 0x8dbc, 0xffffffff, 0x98989898,
  129. 0x8dc0, 0xffffffff, 0x98989898,
  130. 0x8dc4, 0xffffffff, 0x98989898,
  131. 0x8dc8, 0xffffffff, 0x98989898,
  132. 0x8dcc, 0xffffffff, 0x98989898,
  133. 0x88c4, 0xffffffff, 0x00000082
  134. };
  135. static const u32 rv770_golden_registers[] =
  136. {
  137. 0x562c, 0xffffffff, 0,
  138. 0x3f90, 0xffffffff, 0,
  139. 0x9148, 0xffffffff, 0,
  140. 0x3f94, 0xffffffff, 0,
  141. 0x914c, 0xffffffff, 0,
  142. 0x9698, 0x18000000, 0x18000000
  143. };
  144. static const u32 rv770ce_golden_registers[] =
  145. {
  146. 0x562c, 0xffffffff, 0,
  147. 0x3f90, 0xffffffff, 0x00cc0000,
  148. 0x9148, 0xffffffff, 0x00cc0000,
  149. 0x3f94, 0xffffffff, 0x00cc0000,
  150. 0x914c, 0xffffffff, 0x00cc0000,
  151. 0x9b7c, 0xffffffff, 0x00fa0000,
  152. 0x3f8c, 0xffffffff, 0x00fa0000,
  153. 0x9698, 0x18000000, 0x18000000
  154. };
  155. static const u32 rv770_mgcg_init[] =
  156. {
  157. 0x8bcc, 0xffffffff, 0x130300f9,
  158. 0x5448, 0xffffffff, 0x100,
  159. 0x55e4, 0xffffffff, 0x100,
  160. 0x160c, 0xffffffff, 0x100,
  161. 0x5644, 0xffffffff, 0x100,
  162. 0xc164, 0xffffffff, 0x100,
  163. 0x8a18, 0xffffffff, 0x100,
  164. 0x897c, 0xffffffff, 0x8000100,
  165. 0x8b28, 0xffffffff, 0x3c000100,
  166. 0x9144, 0xffffffff, 0x100,
  167. 0x9a1c, 0xffffffff, 0x10000,
  168. 0x9a50, 0xffffffff, 0x100,
  169. 0x9a1c, 0xffffffff, 0x10001,
  170. 0x9a50, 0xffffffff, 0x100,
  171. 0x9a1c, 0xffffffff, 0x10002,
  172. 0x9a50, 0xffffffff, 0x100,
  173. 0x9a1c, 0xffffffff, 0x10003,
  174. 0x9a50, 0xffffffff, 0x100,
  175. 0x9a1c, 0xffffffff, 0x0,
  176. 0x9870, 0xffffffff, 0x100,
  177. 0x8d58, 0xffffffff, 0x100,
  178. 0x9500, 0xffffffff, 0x0,
  179. 0x9510, 0xffffffff, 0x100,
  180. 0x9500, 0xffffffff, 0x1,
  181. 0x9510, 0xffffffff, 0x100,
  182. 0x9500, 0xffffffff, 0x2,
  183. 0x9510, 0xffffffff, 0x100,
  184. 0x9500, 0xffffffff, 0x3,
  185. 0x9510, 0xffffffff, 0x100,
  186. 0x9500, 0xffffffff, 0x4,
  187. 0x9510, 0xffffffff, 0x100,
  188. 0x9500, 0xffffffff, 0x5,
  189. 0x9510, 0xffffffff, 0x100,
  190. 0x9500, 0xffffffff, 0x6,
  191. 0x9510, 0xffffffff, 0x100,
  192. 0x9500, 0xffffffff, 0x7,
  193. 0x9510, 0xffffffff, 0x100,
  194. 0x9500, 0xffffffff, 0x8,
  195. 0x9510, 0xffffffff, 0x100,
  196. 0x9500, 0xffffffff, 0x9,
  197. 0x9510, 0xffffffff, 0x100,
  198. 0x9500, 0xffffffff, 0x8000,
  199. 0x9490, 0xffffffff, 0x0,
  200. 0x949c, 0xffffffff, 0x100,
  201. 0x9490, 0xffffffff, 0x1,
  202. 0x949c, 0xffffffff, 0x100,
  203. 0x9490, 0xffffffff, 0x2,
  204. 0x949c, 0xffffffff, 0x100,
  205. 0x9490, 0xffffffff, 0x3,
  206. 0x949c, 0xffffffff, 0x100,
  207. 0x9490, 0xffffffff, 0x4,
  208. 0x949c, 0xffffffff, 0x100,
  209. 0x9490, 0xffffffff, 0x5,
  210. 0x949c, 0xffffffff, 0x100,
  211. 0x9490, 0xffffffff, 0x6,
  212. 0x949c, 0xffffffff, 0x100,
  213. 0x9490, 0xffffffff, 0x7,
  214. 0x949c, 0xffffffff, 0x100,
  215. 0x9490, 0xffffffff, 0x8,
  216. 0x949c, 0xffffffff, 0x100,
  217. 0x9490, 0xffffffff, 0x9,
  218. 0x949c, 0xffffffff, 0x100,
  219. 0x9490, 0xffffffff, 0x8000,
  220. 0x9604, 0xffffffff, 0x0,
  221. 0x9654, 0xffffffff, 0x100,
  222. 0x9604, 0xffffffff, 0x1,
  223. 0x9654, 0xffffffff, 0x100,
  224. 0x9604, 0xffffffff, 0x2,
  225. 0x9654, 0xffffffff, 0x100,
  226. 0x9604, 0xffffffff, 0x3,
  227. 0x9654, 0xffffffff, 0x100,
  228. 0x9604, 0xffffffff, 0x4,
  229. 0x9654, 0xffffffff, 0x100,
  230. 0x9604, 0xffffffff, 0x5,
  231. 0x9654, 0xffffffff, 0x100,
  232. 0x9604, 0xffffffff, 0x6,
  233. 0x9654, 0xffffffff, 0x100,
  234. 0x9604, 0xffffffff, 0x7,
  235. 0x9654, 0xffffffff, 0x100,
  236. 0x9604, 0xffffffff, 0x8,
  237. 0x9654, 0xffffffff, 0x100,
  238. 0x9604, 0xffffffff, 0x9,
  239. 0x9654, 0xffffffff, 0x100,
  240. 0x9604, 0xffffffff, 0x80000000,
  241. 0x9030, 0xffffffff, 0x100,
  242. 0x9034, 0xffffffff, 0x100,
  243. 0x9038, 0xffffffff, 0x100,
  244. 0x903c, 0xffffffff, 0x100,
  245. 0x9040, 0xffffffff, 0x100,
  246. 0xa200, 0xffffffff, 0x100,
  247. 0xa204, 0xffffffff, 0x100,
  248. 0xa208, 0xffffffff, 0x100,
  249. 0xa20c, 0xffffffff, 0x100,
  250. 0x971c, 0xffffffff, 0x100,
  251. 0x915c, 0xffffffff, 0x00020001,
  252. 0x9160, 0xffffffff, 0x00040003,
  253. 0x916c, 0xffffffff, 0x00060005,
  254. 0x9170, 0xffffffff, 0x00080007,
  255. 0x9174, 0xffffffff, 0x000a0009,
  256. 0x9178, 0xffffffff, 0x000c000b,
  257. 0x917c, 0xffffffff, 0x000e000d,
  258. 0x9180, 0xffffffff, 0x0010000f,
  259. 0x918c, 0xffffffff, 0x00120011,
  260. 0x9190, 0xffffffff, 0x00140013,
  261. 0x9194, 0xffffffff, 0x00020001,
  262. 0x9198, 0xffffffff, 0x00040003,
  263. 0x919c, 0xffffffff, 0x00060005,
  264. 0x91a8, 0xffffffff, 0x00080007,
  265. 0x91ac, 0xffffffff, 0x000a0009,
  266. 0x91b0, 0xffffffff, 0x000c000b,
  267. 0x91b4, 0xffffffff, 0x000e000d,
  268. 0x91b8, 0xffffffff, 0x0010000f,
  269. 0x91c4, 0xffffffff, 0x00120011,
  270. 0x91c8, 0xffffffff, 0x00140013,
  271. 0x91cc, 0xffffffff, 0x00020001,
  272. 0x91d0, 0xffffffff, 0x00040003,
  273. 0x91d4, 0xffffffff, 0x00060005,
  274. 0x91e0, 0xffffffff, 0x00080007,
  275. 0x91e4, 0xffffffff, 0x000a0009,
  276. 0x91e8, 0xffffffff, 0x000c000b,
  277. 0x91ec, 0xffffffff, 0x00020001,
  278. 0x91f0, 0xffffffff, 0x00040003,
  279. 0x91f4, 0xffffffff, 0x00060005,
  280. 0x9200, 0xffffffff, 0x00080007,
  281. 0x9204, 0xffffffff, 0x000a0009,
  282. 0x9208, 0xffffffff, 0x000c000b,
  283. 0x920c, 0xffffffff, 0x000e000d,
  284. 0x9210, 0xffffffff, 0x0010000f,
  285. 0x921c, 0xffffffff, 0x00120011,
  286. 0x9220, 0xffffffff, 0x00140013,
  287. 0x9224, 0xffffffff, 0x00020001,
  288. 0x9228, 0xffffffff, 0x00040003,
  289. 0x922c, 0xffffffff, 0x00060005,
  290. 0x9238, 0xffffffff, 0x00080007,
  291. 0x923c, 0xffffffff, 0x000a0009,
  292. 0x9240, 0xffffffff, 0x000c000b,
  293. 0x9244, 0xffffffff, 0x000e000d,
  294. 0x9248, 0xffffffff, 0x0010000f,
  295. 0x9254, 0xffffffff, 0x00120011,
  296. 0x9258, 0xffffffff, 0x00140013,
  297. 0x925c, 0xffffffff, 0x00020001,
  298. 0x9260, 0xffffffff, 0x00040003,
  299. 0x9264, 0xffffffff, 0x00060005,
  300. 0x9270, 0xffffffff, 0x00080007,
  301. 0x9274, 0xffffffff, 0x000a0009,
  302. 0x9278, 0xffffffff, 0x000c000b,
  303. 0x927c, 0xffffffff, 0x000e000d,
  304. 0x9280, 0xffffffff, 0x0010000f,
  305. 0x928c, 0xffffffff, 0x00120011,
  306. 0x9290, 0xffffffff, 0x00140013,
  307. 0x9294, 0xffffffff, 0x00020001,
  308. 0x929c, 0xffffffff, 0x00040003,
  309. 0x92a0, 0xffffffff, 0x00060005,
  310. 0x92a4, 0xffffffff, 0x00080007
  311. };
  312. static const u32 rv710_golden_registers[] =
  313. {
  314. 0x3f90, 0x00ff0000, 0x00fc0000,
  315. 0x9148, 0x00ff0000, 0x00fc0000,
  316. 0x3f94, 0x00ff0000, 0x00fc0000,
  317. 0x914c, 0x00ff0000, 0x00fc0000,
  318. 0xb4c, 0x00000020, 0x00000020,
  319. 0xa180, 0xffffffff, 0x00003f3f
  320. };
  321. static const u32 rv710_mgcg_init[] =
  322. {
  323. 0x8bcc, 0xffffffff, 0x13030040,
  324. 0x5448, 0xffffffff, 0x100,
  325. 0x55e4, 0xffffffff, 0x100,
  326. 0x160c, 0xffffffff, 0x100,
  327. 0x5644, 0xffffffff, 0x100,
  328. 0xc164, 0xffffffff, 0x100,
  329. 0x8a18, 0xffffffff, 0x100,
  330. 0x897c, 0xffffffff, 0x8000100,
  331. 0x8b28, 0xffffffff, 0x3c000100,
  332. 0x9144, 0xffffffff, 0x100,
  333. 0x9a1c, 0xffffffff, 0x10000,
  334. 0x9a50, 0xffffffff, 0x100,
  335. 0x9a1c, 0xffffffff, 0x0,
  336. 0x9870, 0xffffffff, 0x100,
  337. 0x8d58, 0xffffffff, 0x100,
  338. 0x9500, 0xffffffff, 0x0,
  339. 0x9510, 0xffffffff, 0x100,
  340. 0x9500, 0xffffffff, 0x1,
  341. 0x9510, 0xffffffff, 0x100,
  342. 0x9500, 0xffffffff, 0x8000,
  343. 0x9490, 0xffffffff, 0x0,
  344. 0x949c, 0xffffffff, 0x100,
  345. 0x9490, 0xffffffff, 0x1,
  346. 0x949c, 0xffffffff, 0x100,
  347. 0x9490, 0xffffffff, 0x8000,
  348. 0x9604, 0xffffffff, 0x0,
  349. 0x9654, 0xffffffff, 0x100,
  350. 0x9604, 0xffffffff, 0x1,
  351. 0x9654, 0xffffffff, 0x100,
  352. 0x9604, 0xffffffff, 0x80000000,
  353. 0x9030, 0xffffffff, 0x100,
  354. 0x9034, 0xffffffff, 0x100,
  355. 0x9038, 0xffffffff, 0x100,
  356. 0x903c, 0xffffffff, 0x100,
  357. 0x9040, 0xffffffff, 0x100,
  358. 0xa200, 0xffffffff, 0x100,
  359. 0xa204, 0xffffffff, 0x100,
  360. 0xa208, 0xffffffff, 0x100,
  361. 0xa20c, 0xffffffff, 0x100,
  362. 0x971c, 0xffffffff, 0x100,
  363. 0x915c, 0xffffffff, 0x00020001,
  364. 0x9174, 0xffffffff, 0x00000003,
  365. 0x9178, 0xffffffff, 0x00050001,
  366. 0x917c, 0xffffffff, 0x00030002,
  367. 0x918c, 0xffffffff, 0x00000004,
  368. 0x9190, 0xffffffff, 0x00070006,
  369. 0x9194, 0xffffffff, 0x00050001,
  370. 0x9198, 0xffffffff, 0x00030002,
  371. 0x91a8, 0xffffffff, 0x00000004,
  372. 0x91ac, 0xffffffff, 0x00070006,
  373. 0x91e8, 0xffffffff, 0x00000001,
  374. 0x9294, 0xffffffff, 0x00000001,
  375. 0x929c, 0xffffffff, 0x00000002,
  376. 0x92a0, 0xffffffff, 0x00040003,
  377. 0x9150, 0xffffffff, 0x4d940000
  378. };
  379. static const u32 rv730_golden_registers[] =
  380. {
  381. 0x3f90, 0x00ff0000, 0x00f00000,
  382. 0x9148, 0x00ff0000, 0x00f00000,
  383. 0x3f94, 0x00ff0000, 0x00f00000,
  384. 0x914c, 0x00ff0000, 0x00f00000,
  385. 0x900c, 0xffffffff, 0x003b033f,
  386. 0xb4c, 0x00000020, 0x00000020,
  387. 0xa180, 0xffffffff, 0x00003f3f
  388. };
  389. static const u32 rv730_mgcg_init[] =
  390. {
  391. 0x8bcc, 0xffffffff, 0x130300f9,
  392. 0x5448, 0xffffffff, 0x100,
  393. 0x55e4, 0xffffffff, 0x100,
  394. 0x160c, 0xffffffff, 0x100,
  395. 0x5644, 0xffffffff, 0x100,
  396. 0xc164, 0xffffffff, 0x100,
  397. 0x8a18, 0xffffffff, 0x100,
  398. 0x897c, 0xffffffff, 0x8000100,
  399. 0x8b28, 0xffffffff, 0x3c000100,
  400. 0x9144, 0xffffffff, 0x100,
  401. 0x9a1c, 0xffffffff, 0x10000,
  402. 0x9a50, 0xffffffff, 0x100,
  403. 0x9a1c, 0xffffffff, 0x10001,
  404. 0x9a50, 0xffffffff, 0x100,
  405. 0x9a1c, 0xffffffff, 0x0,
  406. 0x9870, 0xffffffff, 0x100,
  407. 0x8d58, 0xffffffff, 0x100,
  408. 0x9500, 0xffffffff, 0x0,
  409. 0x9510, 0xffffffff, 0x100,
  410. 0x9500, 0xffffffff, 0x1,
  411. 0x9510, 0xffffffff, 0x100,
  412. 0x9500, 0xffffffff, 0x2,
  413. 0x9510, 0xffffffff, 0x100,
  414. 0x9500, 0xffffffff, 0x3,
  415. 0x9510, 0xffffffff, 0x100,
  416. 0x9500, 0xffffffff, 0x4,
  417. 0x9510, 0xffffffff, 0x100,
  418. 0x9500, 0xffffffff, 0x5,
  419. 0x9510, 0xffffffff, 0x100,
  420. 0x9500, 0xffffffff, 0x6,
  421. 0x9510, 0xffffffff, 0x100,
  422. 0x9500, 0xffffffff, 0x7,
  423. 0x9510, 0xffffffff, 0x100,
  424. 0x9500, 0xffffffff, 0x8000,
  425. 0x9490, 0xffffffff, 0x0,
  426. 0x949c, 0xffffffff, 0x100,
  427. 0x9490, 0xffffffff, 0x1,
  428. 0x949c, 0xffffffff, 0x100,
  429. 0x9490, 0xffffffff, 0x2,
  430. 0x949c, 0xffffffff, 0x100,
  431. 0x9490, 0xffffffff, 0x3,
  432. 0x949c, 0xffffffff, 0x100,
  433. 0x9490, 0xffffffff, 0x4,
  434. 0x949c, 0xffffffff, 0x100,
  435. 0x9490, 0xffffffff, 0x5,
  436. 0x949c, 0xffffffff, 0x100,
  437. 0x9490, 0xffffffff, 0x6,
  438. 0x949c, 0xffffffff, 0x100,
  439. 0x9490, 0xffffffff, 0x7,
  440. 0x949c, 0xffffffff, 0x100,
  441. 0x9490, 0xffffffff, 0x8000,
  442. 0x9604, 0xffffffff, 0x0,
  443. 0x9654, 0xffffffff, 0x100,
  444. 0x9604, 0xffffffff, 0x1,
  445. 0x9654, 0xffffffff, 0x100,
  446. 0x9604, 0xffffffff, 0x2,
  447. 0x9654, 0xffffffff, 0x100,
  448. 0x9604, 0xffffffff, 0x3,
  449. 0x9654, 0xffffffff, 0x100,
  450. 0x9604, 0xffffffff, 0x4,
  451. 0x9654, 0xffffffff, 0x100,
  452. 0x9604, 0xffffffff, 0x5,
  453. 0x9654, 0xffffffff, 0x100,
  454. 0x9604, 0xffffffff, 0x6,
  455. 0x9654, 0xffffffff, 0x100,
  456. 0x9604, 0xffffffff, 0x7,
  457. 0x9654, 0xffffffff, 0x100,
  458. 0x9604, 0xffffffff, 0x80000000,
  459. 0x9030, 0xffffffff, 0x100,
  460. 0x9034, 0xffffffff, 0x100,
  461. 0x9038, 0xffffffff, 0x100,
  462. 0x903c, 0xffffffff, 0x100,
  463. 0x9040, 0xffffffff, 0x100,
  464. 0xa200, 0xffffffff, 0x100,
  465. 0xa204, 0xffffffff, 0x100,
  466. 0xa208, 0xffffffff, 0x100,
  467. 0xa20c, 0xffffffff, 0x100,
  468. 0x971c, 0xffffffff, 0x100,
  469. 0x915c, 0xffffffff, 0x00020001,
  470. 0x916c, 0xffffffff, 0x00040003,
  471. 0x9170, 0xffffffff, 0x00000005,
  472. 0x9178, 0xffffffff, 0x00050001,
  473. 0x917c, 0xffffffff, 0x00030002,
  474. 0x918c, 0xffffffff, 0x00000004,
  475. 0x9190, 0xffffffff, 0x00070006,
  476. 0x9194, 0xffffffff, 0x00050001,
  477. 0x9198, 0xffffffff, 0x00030002,
  478. 0x91a8, 0xffffffff, 0x00000004,
  479. 0x91ac, 0xffffffff, 0x00070006,
  480. 0x91b0, 0xffffffff, 0x00050001,
  481. 0x91b4, 0xffffffff, 0x00030002,
  482. 0x91c4, 0xffffffff, 0x00000004,
  483. 0x91c8, 0xffffffff, 0x00070006,
  484. 0x91cc, 0xffffffff, 0x00050001,
  485. 0x91d0, 0xffffffff, 0x00030002,
  486. 0x91e0, 0xffffffff, 0x00000004,
  487. 0x91e4, 0xffffffff, 0x00070006,
  488. 0x91e8, 0xffffffff, 0x00000001,
  489. 0x91ec, 0xffffffff, 0x00050001,
  490. 0x91f0, 0xffffffff, 0x00030002,
  491. 0x9200, 0xffffffff, 0x00000004,
  492. 0x9204, 0xffffffff, 0x00070006,
  493. 0x9208, 0xffffffff, 0x00050001,
  494. 0x920c, 0xffffffff, 0x00030002,
  495. 0x921c, 0xffffffff, 0x00000004,
  496. 0x9220, 0xffffffff, 0x00070006,
  497. 0x9224, 0xffffffff, 0x00050001,
  498. 0x9228, 0xffffffff, 0x00030002,
  499. 0x9238, 0xffffffff, 0x00000004,
  500. 0x923c, 0xffffffff, 0x00070006,
  501. 0x9240, 0xffffffff, 0x00050001,
  502. 0x9244, 0xffffffff, 0x00030002,
  503. 0x9254, 0xffffffff, 0x00000004,
  504. 0x9258, 0xffffffff, 0x00070006,
  505. 0x9294, 0xffffffff, 0x00000001,
  506. 0x929c, 0xffffffff, 0x00000002,
  507. 0x92a0, 0xffffffff, 0x00040003,
  508. 0x92a4, 0xffffffff, 0x00000005
  509. };
  510. static const u32 rv740_golden_registers[] =
  511. {
  512. 0x88c4, 0xffffffff, 0x00000082,
  513. 0x28a50, 0xfffffffc, 0x00000004,
  514. 0x2650, 0x00040000, 0,
  515. 0x20bc, 0x00040000, 0,
  516. 0x733c, 0xffffffff, 0x00000002,
  517. 0x7300, 0xffffffff, 0x001000f0,
  518. 0x3f90, 0x00ff0000, 0,
  519. 0x9148, 0x00ff0000, 0,
  520. 0x3f94, 0x00ff0000, 0,
  521. 0x914c, 0x00ff0000, 0,
  522. 0x240c, 0xffffffff, 0x00000380,
  523. 0x8a14, 0x00000007, 0x00000007,
  524. 0x8b24, 0xffffffff, 0x00ff0fff,
  525. 0x28a4c, 0xffffffff, 0x00004000,
  526. 0xa180, 0xffffffff, 0x00003f3f,
  527. 0x8d00, 0xffffffff, 0x0e0e003a,
  528. 0x8d04, 0xffffffff, 0x013a0e2a,
  529. 0x8c00, 0xffffffff, 0xe400000f,
  530. 0x8db0, 0xffffffff, 0x98989898,
  531. 0x8db4, 0xffffffff, 0x98989898,
  532. 0x8db8, 0xffffffff, 0x98989898,
  533. 0x8dbc, 0xffffffff, 0x98989898,
  534. 0x8dc0, 0xffffffff, 0x98989898,
  535. 0x8dc4, 0xffffffff, 0x98989898,
  536. 0x8dc8, 0xffffffff, 0x98989898,
  537. 0x8dcc, 0xffffffff, 0x98989898,
  538. 0x9058, 0xffffffff, 0x0fffc40f,
  539. 0x900c, 0xffffffff, 0x003b033f,
  540. 0x28350, 0xffffffff, 0,
  541. 0x8cf0, 0x1fffffff, 0x08e00420,
  542. 0x9508, 0xffffffff, 0x00000002,
  543. 0x88c4, 0xffffffff, 0x000000c2,
  544. 0x9698, 0x18000000, 0x18000000
  545. };
  546. static const u32 rv740_mgcg_init[] =
  547. {
  548. 0x8bcc, 0xffffffff, 0x13030100,
  549. 0x5448, 0xffffffff, 0x100,
  550. 0x55e4, 0xffffffff, 0x100,
  551. 0x160c, 0xffffffff, 0x100,
  552. 0x5644, 0xffffffff, 0x100,
  553. 0xc164, 0xffffffff, 0x100,
  554. 0x8a18, 0xffffffff, 0x100,
  555. 0x897c, 0xffffffff, 0x100,
  556. 0x8b28, 0xffffffff, 0x100,
  557. 0x9144, 0xffffffff, 0x100,
  558. 0x9a1c, 0xffffffff, 0x10000,
  559. 0x9a50, 0xffffffff, 0x100,
  560. 0x9a1c, 0xffffffff, 0x10001,
  561. 0x9a50, 0xffffffff, 0x100,
  562. 0x9a1c, 0xffffffff, 0x10002,
  563. 0x9a50, 0xffffffff, 0x100,
  564. 0x9a1c, 0xffffffff, 0x10003,
  565. 0x9a50, 0xffffffff, 0x100,
  566. 0x9a1c, 0xffffffff, 0x0,
  567. 0x9870, 0xffffffff, 0x100,
  568. 0x8d58, 0xffffffff, 0x100,
  569. 0x9500, 0xffffffff, 0x0,
  570. 0x9510, 0xffffffff, 0x100,
  571. 0x9500, 0xffffffff, 0x1,
  572. 0x9510, 0xffffffff, 0x100,
  573. 0x9500, 0xffffffff, 0x2,
  574. 0x9510, 0xffffffff, 0x100,
  575. 0x9500, 0xffffffff, 0x3,
  576. 0x9510, 0xffffffff, 0x100,
  577. 0x9500, 0xffffffff, 0x4,
  578. 0x9510, 0xffffffff, 0x100,
  579. 0x9500, 0xffffffff, 0x5,
  580. 0x9510, 0xffffffff, 0x100,
  581. 0x9500, 0xffffffff, 0x6,
  582. 0x9510, 0xffffffff, 0x100,
  583. 0x9500, 0xffffffff, 0x7,
  584. 0x9510, 0xffffffff, 0x100,
  585. 0x9500, 0xffffffff, 0x8000,
  586. 0x9490, 0xffffffff, 0x0,
  587. 0x949c, 0xffffffff, 0x100,
  588. 0x9490, 0xffffffff, 0x1,
  589. 0x949c, 0xffffffff, 0x100,
  590. 0x9490, 0xffffffff, 0x2,
  591. 0x949c, 0xffffffff, 0x100,
  592. 0x9490, 0xffffffff, 0x3,
  593. 0x949c, 0xffffffff, 0x100,
  594. 0x9490, 0xffffffff, 0x4,
  595. 0x949c, 0xffffffff, 0x100,
  596. 0x9490, 0xffffffff, 0x5,
  597. 0x949c, 0xffffffff, 0x100,
  598. 0x9490, 0xffffffff, 0x6,
  599. 0x949c, 0xffffffff, 0x100,
  600. 0x9490, 0xffffffff, 0x7,
  601. 0x949c, 0xffffffff, 0x100,
  602. 0x9490, 0xffffffff, 0x8000,
  603. 0x9604, 0xffffffff, 0x0,
  604. 0x9654, 0xffffffff, 0x100,
  605. 0x9604, 0xffffffff, 0x1,
  606. 0x9654, 0xffffffff, 0x100,
  607. 0x9604, 0xffffffff, 0x2,
  608. 0x9654, 0xffffffff, 0x100,
  609. 0x9604, 0xffffffff, 0x3,
  610. 0x9654, 0xffffffff, 0x100,
  611. 0x9604, 0xffffffff, 0x4,
  612. 0x9654, 0xffffffff, 0x100,
  613. 0x9604, 0xffffffff, 0x5,
  614. 0x9654, 0xffffffff, 0x100,
  615. 0x9604, 0xffffffff, 0x6,
  616. 0x9654, 0xffffffff, 0x100,
  617. 0x9604, 0xffffffff, 0x7,
  618. 0x9654, 0xffffffff, 0x100,
  619. 0x9604, 0xffffffff, 0x80000000,
  620. 0x9030, 0xffffffff, 0x100,
  621. 0x9034, 0xffffffff, 0x100,
  622. 0x9038, 0xffffffff, 0x100,
  623. 0x903c, 0xffffffff, 0x100,
  624. 0x9040, 0xffffffff, 0x100,
  625. 0xa200, 0xffffffff, 0x100,
  626. 0xa204, 0xffffffff, 0x100,
  627. 0xa208, 0xffffffff, 0x100,
  628. 0xa20c, 0xffffffff, 0x100,
  629. 0x971c, 0xffffffff, 0x100,
  630. 0x915c, 0xffffffff, 0x00020001,
  631. 0x9160, 0xffffffff, 0x00040003,
  632. 0x916c, 0xffffffff, 0x00060005,
  633. 0x9170, 0xffffffff, 0x00080007,
  634. 0x9174, 0xffffffff, 0x000a0009,
  635. 0x9178, 0xffffffff, 0x000c000b,
  636. 0x917c, 0xffffffff, 0x000e000d,
  637. 0x9180, 0xffffffff, 0x0010000f,
  638. 0x918c, 0xffffffff, 0x00120011,
  639. 0x9190, 0xffffffff, 0x00140013,
  640. 0x9194, 0xffffffff, 0x00020001,
  641. 0x9198, 0xffffffff, 0x00040003,
  642. 0x919c, 0xffffffff, 0x00060005,
  643. 0x91a8, 0xffffffff, 0x00080007,
  644. 0x91ac, 0xffffffff, 0x000a0009,
  645. 0x91b0, 0xffffffff, 0x000c000b,
  646. 0x91b4, 0xffffffff, 0x000e000d,
  647. 0x91b8, 0xffffffff, 0x0010000f,
  648. 0x91c4, 0xffffffff, 0x00120011,
  649. 0x91c8, 0xffffffff, 0x00140013,
  650. 0x91cc, 0xffffffff, 0x00020001,
  651. 0x91d0, 0xffffffff, 0x00040003,
  652. 0x91d4, 0xffffffff, 0x00060005,
  653. 0x91e0, 0xffffffff, 0x00080007,
  654. 0x91e4, 0xffffffff, 0x000a0009,
  655. 0x91e8, 0xffffffff, 0x000c000b,
  656. 0x91ec, 0xffffffff, 0x00020001,
  657. 0x91f0, 0xffffffff, 0x00040003,
  658. 0x91f4, 0xffffffff, 0x00060005,
  659. 0x9200, 0xffffffff, 0x00080007,
  660. 0x9204, 0xffffffff, 0x000a0009,
  661. 0x9208, 0xffffffff, 0x000c000b,
  662. 0x920c, 0xffffffff, 0x000e000d,
  663. 0x9210, 0xffffffff, 0x0010000f,
  664. 0x921c, 0xffffffff, 0x00120011,
  665. 0x9220, 0xffffffff, 0x00140013,
  666. 0x9224, 0xffffffff, 0x00020001,
  667. 0x9228, 0xffffffff, 0x00040003,
  668. 0x922c, 0xffffffff, 0x00060005,
  669. 0x9238, 0xffffffff, 0x00080007,
  670. 0x923c, 0xffffffff, 0x000a0009,
  671. 0x9240, 0xffffffff, 0x000c000b,
  672. 0x9244, 0xffffffff, 0x000e000d,
  673. 0x9248, 0xffffffff, 0x0010000f,
  674. 0x9254, 0xffffffff, 0x00120011,
  675. 0x9258, 0xffffffff, 0x00140013,
  676. 0x9294, 0xffffffff, 0x00020001,
  677. 0x929c, 0xffffffff, 0x00040003,
  678. 0x92a0, 0xffffffff, 0x00060005,
  679. 0x92a4, 0xffffffff, 0x00080007
  680. };
  681. static void rv770_init_golden_registers(struct radeon_device *rdev)
  682. {
  683. switch (rdev->family) {
  684. case CHIP_RV770:
  685. radeon_program_register_sequence(rdev,
  686. r7xx_golden_registers,
  687. (const u32)ARRAY_SIZE(r7xx_golden_registers));
  688. radeon_program_register_sequence(rdev,
  689. r7xx_golden_dyn_gpr_registers,
  690. (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
  691. if (rdev->pdev->device == 0x994e)
  692. radeon_program_register_sequence(rdev,
  693. rv770ce_golden_registers,
  694. (const u32)ARRAY_SIZE(rv770ce_golden_registers));
  695. else
  696. radeon_program_register_sequence(rdev,
  697. rv770_golden_registers,
  698. (const u32)ARRAY_SIZE(rv770_golden_registers));
  699. radeon_program_register_sequence(rdev,
  700. rv770_mgcg_init,
  701. (const u32)ARRAY_SIZE(rv770_mgcg_init));
  702. break;
  703. case CHIP_RV730:
  704. radeon_program_register_sequence(rdev,
  705. r7xx_golden_registers,
  706. (const u32)ARRAY_SIZE(r7xx_golden_registers));
  707. radeon_program_register_sequence(rdev,
  708. r7xx_golden_dyn_gpr_registers,
  709. (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
  710. radeon_program_register_sequence(rdev,
  711. rv730_golden_registers,
  712. (const u32)ARRAY_SIZE(rv730_golden_registers));
  713. radeon_program_register_sequence(rdev,
  714. rv730_mgcg_init,
  715. (const u32)ARRAY_SIZE(rv730_mgcg_init));
  716. break;
  717. case CHIP_RV710:
  718. radeon_program_register_sequence(rdev,
  719. r7xx_golden_registers,
  720. (const u32)ARRAY_SIZE(r7xx_golden_registers));
  721. radeon_program_register_sequence(rdev,
  722. r7xx_golden_dyn_gpr_registers,
  723. (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
  724. radeon_program_register_sequence(rdev,
  725. rv710_golden_registers,
  726. (const u32)ARRAY_SIZE(rv710_golden_registers));
  727. radeon_program_register_sequence(rdev,
  728. rv710_mgcg_init,
  729. (const u32)ARRAY_SIZE(rv710_mgcg_init));
  730. break;
  731. case CHIP_RV740:
  732. radeon_program_register_sequence(rdev,
  733. rv740_golden_registers,
  734. (const u32)ARRAY_SIZE(rv740_golden_registers));
  735. radeon_program_register_sequence(rdev,
  736. rv740_mgcg_init,
  737. (const u32)ARRAY_SIZE(rv740_mgcg_init));
  738. break;
  739. default:
  740. break;
  741. }
  742. }
  743. #define PCIE_BUS_CLK 10000
  744. #define TCLK (PCIE_BUS_CLK / 10)
  745. /**
  746. * rv770_get_xclk - get the xclk
  747. *
  748. * @rdev: radeon_device pointer
  749. *
  750. * Returns the reference clock used by the gfx engine
  751. * (r7xx-cayman).
  752. */
  753. u32 rv770_get_xclk(struct radeon_device *rdev)
  754. {
  755. u32 reference_clock = rdev->clock.spll.reference_freq;
  756. u32 tmp = RREG32(CG_CLKPIN_CNTL);
  757. if (tmp & MUX_TCLK_TO_XCLK)
  758. return TCLK;
  759. if (tmp & XTALIN_DIVIDE)
  760. return reference_clock / 4;
  761. return reference_clock;
  762. }
  763. u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  764. {
  765. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  766. u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  767. int i;
  768. /* Lock the graphics update lock */
  769. tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  770. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  771. /* update the scanout addresses */
  772. if (radeon_crtc->crtc_id) {
  773. WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  774. WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  775. } else {
  776. WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  777. WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  778. }
  779. WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  780. (u32)crtc_base);
  781. WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  782. (u32)crtc_base);
  783. /* Wait for update_pending to go high. */
  784. for (i = 0; i < rdev->usec_timeout; i++) {
  785. if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
  786. break;
  787. udelay(1);
  788. }
  789. DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  790. /* Unlock the lock, so double-buffering can take place inside vblank */
  791. tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  792. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  793. /* Return current update_pending status: */
  794. return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  795. }
  796. /* get temperature in millidegrees */
  797. int rv770_get_temp(struct radeon_device *rdev)
  798. {
  799. u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  800. ASIC_T_SHIFT;
  801. int actual_temp;
  802. if (temp & 0x400)
  803. actual_temp = -256;
  804. else if (temp & 0x200)
  805. actual_temp = 255;
  806. else if (temp & 0x100) {
  807. actual_temp = temp & 0x1ff;
  808. actual_temp |= ~0x1ff;
  809. } else
  810. actual_temp = temp & 0xff;
  811. return (actual_temp * 1000) / 2;
  812. }
  813. void rv770_pm_misc(struct radeon_device *rdev)
  814. {
  815. int req_ps_idx = rdev->pm.requested_power_state_index;
  816. int req_cm_idx = rdev->pm.requested_clock_mode_index;
  817. struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  818. struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  819. if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
  820. /* 0xff01 is a flag rather then an actual voltage */
  821. if (voltage->voltage == 0xff01)
  822. return;
  823. if (voltage->voltage != rdev->pm.current_vddc) {
  824. radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
  825. rdev->pm.current_vddc = voltage->voltage;
  826. DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
  827. }
  828. }
  829. }
  830. /*
  831. * GART
  832. */
  833. static int rv770_pcie_gart_enable(struct radeon_device *rdev)
  834. {
  835. u32 tmp;
  836. int r, i;
  837. if (rdev->gart.robj == NULL) {
  838. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  839. return -EINVAL;
  840. }
  841. r = radeon_gart_table_vram_pin(rdev);
  842. if (r)
  843. return r;
  844. radeon_gart_restore(rdev);
  845. /* Setup L2 cache */
  846. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  847. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  848. EFFECTIVE_L2_QUEUE_SIZE(7));
  849. WREG32(VM_L2_CNTL2, 0);
  850. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  851. /* Setup TLB control */
  852. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  853. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  854. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  855. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  856. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  857. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  858. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  859. if (rdev->family == CHIP_RV740)
  860. WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
  861. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  862. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  863. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  864. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  865. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  866. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  867. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  868. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  869. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  870. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  871. (u32)(rdev->dummy_page.addr >> 12));
  872. for (i = 1; i < 7; i++)
  873. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  874. r600_pcie_gart_tlb_flush(rdev);
  875. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  876. (unsigned)(rdev->mc.gtt_size >> 20),
  877. (unsigned long long)rdev->gart.table_addr);
  878. rdev->gart.ready = true;
  879. return 0;
  880. }
  881. static void rv770_pcie_gart_disable(struct radeon_device *rdev)
  882. {
  883. u32 tmp;
  884. int i;
  885. /* Disable all tables */
  886. for (i = 0; i < 7; i++)
  887. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  888. /* Setup L2 cache */
  889. WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
  890. EFFECTIVE_L2_QUEUE_SIZE(7));
  891. WREG32(VM_L2_CNTL2, 0);
  892. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  893. /* Setup TLB control */
  894. tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  895. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  896. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  897. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  898. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  899. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  900. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  901. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  902. radeon_gart_table_vram_unpin(rdev);
  903. }
  904. static void rv770_pcie_gart_fini(struct radeon_device *rdev)
  905. {
  906. radeon_gart_fini(rdev);
  907. rv770_pcie_gart_disable(rdev);
  908. radeon_gart_table_vram_free(rdev);
  909. }
  910. static void rv770_agp_enable(struct radeon_device *rdev)
  911. {
  912. u32 tmp;
  913. int i;
  914. /* Setup L2 cache */
  915. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  916. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  917. EFFECTIVE_L2_QUEUE_SIZE(7));
  918. WREG32(VM_L2_CNTL2, 0);
  919. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  920. /* Setup TLB control */
  921. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  922. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  923. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  924. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  925. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  926. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  927. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  928. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  929. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  930. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  931. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  932. for (i = 0; i < 7; i++)
  933. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  934. }
  935. static void rv770_mc_program(struct radeon_device *rdev)
  936. {
  937. struct rv515_mc_save save;
  938. u32 tmp;
  939. int i, j;
  940. /* Initialize HDP */
  941. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  942. WREG32((0x2c14 + j), 0x00000000);
  943. WREG32((0x2c18 + j), 0x00000000);
  944. WREG32((0x2c1c + j), 0x00000000);
  945. WREG32((0x2c20 + j), 0x00000000);
  946. WREG32((0x2c24 + j), 0x00000000);
  947. }
  948. /* r7xx hw bug. Read from HDP_DEBUG1 rather
  949. * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
  950. */
  951. tmp = RREG32(HDP_DEBUG1);
  952. rv515_mc_stop(rdev, &save);
  953. if (r600_mc_wait_for_idle(rdev)) {
  954. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  955. }
  956. /* Lockout access through VGA aperture*/
  957. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  958. /* Update configuration */
  959. if (rdev->flags & RADEON_IS_AGP) {
  960. if (rdev->mc.vram_start < rdev->mc.gtt_start) {
  961. /* VRAM before AGP */
  962. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  963. rdev->mc.vram_start >> 12);
  964. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  965. rdev->mc.gtt_end >> 12);
  966. } else {
  967. /* VRAM after AGP */
  968. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  969. rdev->mc.gtt_start >> 12);
  970. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  971. rdev->mc.vram_end >> 12);
  972. }
  973. } else {
  974. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  975. rdev->mc.vram_start >> 12);
  976. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  977. rdev->mc.vram_end >> 12);
  978. }
  979. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
  980. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  981. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  982. WREG32(MC_VM_FB_LOCATION, tmp);
  983. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  984. WREG32(HDP_NONSURFACE_INFO, (2 << 7));
  985. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  986. if (rdev->flags & RADEON_IS_AGP) {
  987. WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
  988. WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
  989. WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
  990. } else {
  991. WREG32(MC_VM_AGP_BASE, 0);
  992. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  993. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  994. }
  995. if (r600_mc_wait_for_idle(rdev)) {
  996. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  997. }
  998. rv515_mc_resume(rdev, &save);
  999. /* we need to own VRAM, so turn off the VGA renderer here
  1000. * to stop it overwriting our objects */
  1001. rv515_vga_render_disable(rdev);
  1002. }
  1003. /*
  1004. * CP.
  1005. */
  1006. void r700_cp_stop(struct radeon_device *rdev)
  1007. {
  1008. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  1009. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
  1010. WREG32(SCRATCH_UMSK, 0);
  1011. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  1012. }
  1013. static int rv770_cp_load_microcode(struct radeon_device *rdev)
  1014. {
  1015. const __be32 *fw_data;
  1016. int i;
  1017. if (!rdev->me_fw || !rdev->pfp_fw)
  1018. return -EINVAL;
  1019. r700_cp_stop(rdev);
  1020. WREG32(CP_RB_CNTL,
  1021. #ifdef __BIG_ENDIAN
  1022. BUF_SWAP_32BIT |
  1023. #endif
  1024. RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
  1025. /* Reset cp */
  1026. WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
  1027. RREG32(GRBM_SOFT_RESET);
  1028. mdelay(15);
  1029. WREG32(GRBM_SOFT_RESET, 0);
  1030. fw_data = (const __be32 *)rdev->pfp_fw->data;
  1031. WREG32(CP_PFP_UCODE_ADDR, 0);
  1032. for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
  1033. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  1034. WREG32(CP_PFP_UCODE_ADDR, 0);
  1035. fw_data = (const __be32 *)rdev->me_fw->data;
  1036. WREG32(CP_ME_RAM_WADDR, 0);
  1037. for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
  1038. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  1039. WREG32(CP_PFP_UCODE_ADDR, 0);
  1040. WREG32(CP_ME_RAM_WADDR, 0);
  1041. WREG32(CP_ME_RAM_RADDR, 0);
  1042. return 0;
  1043. }
  1044. void r700_cp_fini(struct radeon_device *rdev)
  1045. {
  1046. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1047. r700_cp_stop(rdev);
  1048. radeon_ring_fini(rdev, ring);
  1049. radeon_scratch_free(rdev, ring->rptr_save_reg);
  1050. }
  1051. /*
  1052. * Core functions
  1053. */
  1054. static void rv770_gpu_init(struct radeon_device *rdev)
  1055. {
  1056. int i, j, num_qd_pipes;
  1057. u32 ta_aux_cntl;
  1058. u32 sx_debug_1;
  1059. u32 smx_dc_ctl0;
  1060. u32 db_debug3;
  1061. u32 num_gs_verts_per_thread;
  1062. u32 vgt_gs_per_es;
  1063. u32 gs_prim_buffer_depth = 0;
  1064. u32 sq_ms_fifo_sizes;
  1065. u32 sq_config;
  1066. u32 sq_thread_resource_mgmt;
  1067. u32 hdp_host_path_cntl;
  1068. u32 sq_dyn_gpr_size_simd_ab_0;
  1069. u32 gb_tiling_config = 0;
  1070. u32 cc_rb_backend_disable = 0;
  1071. u32 cc_gc_shader_pipe_config = 0;
  1072. u32 mc_arb_ramcfg;
  1073. u32 db_debug4, tmp;
  1074. u32 inactive_pipes, shader_pipe_config;
  1075. u32 disabled_rb_mask;
  1076. unsigned active_number;
  1077. /* setup chip specs */
  1078. rdev->config.rv770.tiling_group_size = 256;
  1079. switch (rdev->family) {
  1080. case CHIP_RV770:
  1081. rdev->config.rv770.max_pipes = 4;
  1082. rdev->config.rv770.max_tile_pipes = 8;
  1083. rdev->config.rv770.max_simds = 10;
  1084. rdev->config.rv770.max_backends = 4;
  1085. rdev->config.rv770.max_gprs = 256;
  1086. rdev->config.rv770.max_threads = 248;
  1087. rdev->config.rv770.max_stack_entries = 512;
  1088. rdev->config.rv770.max_hw_contexts = 8;
  1089. rdev->config.rv770.max_gs_threads = 16 * 2;
  1090. rdev->config.rv770.sx_max_export_size = 128;
  1091. rdev->config.rv770.sx_max_export_pos_size = 16;
  1092. rdev->config.rv770.sx_max_export_smx_size = 112;
  1093. rdev->config.rv770.sq_num_cf_insts = 2;
  1094. rdev->config.rv770.sx_num_of_sets = 7;
  1095. rdev->config.rv770.sc_prim_fifo_size = 0xF9;
  1096. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  1097. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  1098. break;
  1099. case CHIP_RV730:
  1100. rdev->config.rv770.max_pipes = 2;
  1101. rdev->config.rv770.max_tile_pipes = 4;
  1102. rdev->config.rv770.max_simds = 8;
  1103. rdev->config.rv770.max_backends = 2;
  1104. rdev->config.rv770.max_gprs = 128;
  1105. rdev->config.rv770.max_threads = 248;
  1106. rdev->config.rv770.max_stack_entries = 256;
  1107. rdev->config.rv770.max_hw_contexts = 8;
  1108. rdev->config.rv770.max_gs_threads = 16 * 2;
  1109. rdev->config.rv770.sx_max_export_size = 256;
  1110. rdev->config.rv770.sx_max_export_pos_size = 32;
  1111. rdev->config.rv770.sx_max_export_smx_size = 224;
  1112. rdev->config.rv770.sq_num_cf_insts = 2;
  1113. rdev->config.rv770.sx_num_of_sets = 7;
  1114. rdev->config.rv770.sc_prim_fifo_size = 0xf9;
  1115. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  1116. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  1117. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  1118. rdev->config.rv770.sx_max_export_pos_size -= 16;
  1119. rdev->config.rv770.sx_max_export_smx_size += 16;
  1120. }
  1121. break;
  1122. case CHIP_RV710:
  1123. rdev->config.rv770.max_pipes = 2;
  1124. rdev->config.rv770.max_tile_pipes = 2;
  1125. rdev->config.rv770.max_simds = 2;
  1126. rdev->config.rv770.max_backends = 1;
  1127. rdev->config.rv770.max_gprs = 256;
  1128. rdev->config.rv770.max_threads = 192;
  1129. rdev->config.rv770.max_stack_entries = 256;
  1130. rdev->config.rv770.max_hw_contexts = 4;
  1131. rdev->config.rv770.max_gs_threads = 8 * 2;
  1132. rdev->config.rv770.sx_max_export_size = 128;
  1133. rdev->config.rv770.sx_max_export_pos_size = 16;
  1134. rdev->config.rv770.sx_max_export_smx_size = 112;
  1135. rdev->config.rv770.sq_num_cf_insts = 1;
  1136. rdev->config.rv770.sx_num_of_sets = 7;
  1137. rdev->config.rv770.sc_prim_fifo_size = 0x40;
  1138. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  1139. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  1140. break;
  1141. case CHIP_RV740:
  1142. rdev->config.rv770.max_pipes = 4;
  1143. rdev->config.rv770.max_tile_pipes = 4;
  1144. rdev->config.rv770.max_simds = 8;
  1145. rdev->config.rv770.max_backends = 4;
  1146. rdev->config.rv770.max_gprs = 256;
  1147. rdev->config.rv770.max_threads = 248;
  1148. rdev->config.rv770.max_stack_entries = 512;
  1149. rdev->config.rv770.max_hw_contexts = 8;
  1150. rdev->config.rv770.max_gs_threads = 16 * 2;
  1151. rdev->config.rv770.sx_max_export_size = 256;
  1152. rdev->config.rv770.sx_max_export_pos_size = 32;
  1153. rdev->config.rv770.sx_max_export_smx_size = 224;
  1154. rdev->config.rv770.sq_num_cf_insts = 2;
  1155. rdev->config.rv770.sx_num_of_sets = 7;
  1156. rdev->config.rv770.sc_prim_fifo_size = 0x100;
  1157. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  1158. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  1159. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  1160. rdev->config.rv770.sx_max_export_pos_size -= 16;
  1161. rdev->config.rv770.sx_max_export_smx_size += 16;
  1162. }
  1163. break;
  1164. default:
  1165. break;
  1166. }
  1167. /* Initialize HDP */
  1168. j = 0;
  1169. for (i = 0; i < 32; i++) {
  1170. WREG32((0x2c14 + j), 0x00000000);
  1171. WREG32((0x2c18 + j), 0x00000000);
  1172. WREG32((0x2c1c + j), 0x00000000);
  1173. WREG32((0x2c20 + j), 0x00000000);
  1174. WREG32((0x2c24 + j), 0x00000000);
  1175. j += 0x18;
  1176. }
  1177. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  1178. /* setup tiling, simd, pipe config */
  1179. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  1180. shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
  1181. inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
  1182. for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
  1183. if (!(inactive_pipes & tmp)) {
  1184. active_number++;
  1185. }
  1186. tmp <<= 1;
  1187. }
  1188. if (active_number == 1) {
  1189. WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
  1190. } else {
  1191. WREG32(SPI_CONFIG_CNTL, 0);
  1192. }
  1193. cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
  1194. tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
  1195. if (tmp < rdev->config.rv770.max_backends) {
  1196. rdev->config.rv770.max_backends = tmp;
  1197. }
  1198. cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
  1199. tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
  1200. if (tmp < rdev->config.rv770.max_pipes) {
  1201. rdev->config.rv770.max_pipes = tmp;
  1202. }
  1203. tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
  1204. if (tmp < rdev->config.rv770.max_simds) {
  1205. rdev->config.rv770.max_simds = tmp;
  1206. }
  1207. switch (rdev->config.rv770.max_tile_pipes) {
  1208. case 1:
  1209. default:
  1210. gb_tiling_config = PIPE_TILING(0);
  1211. break;
  1212. case 2:
  1213. gb_tiling_config = PIPE_TILING(1);
  1214. break;
  1215. case 4:
  1216. gb_tiling_config = PIPE_TILING(2);
  1217. break;
  1218. case 8:
  1219. gb_tiling_config = PIPE_TILING(3);
  1220. break;
  1221. }
  1222. rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
  1223. disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
  1224. tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
  1225. tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
  1226. R7XX_MAX_BACKENDS, disabled_rb_mask);
  1227. gb_tiling_config |= tmp << 16;
  1228. rdev->config.rv770.backend_map = tmp;
  1229. if (rdev->family == CHIP_RV770)
  1230. gb_tiling_config |= BANK_TILING(1);
  1231. else {
  1232. if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
  1233. gb_tiling_config |= BANK_TILING(1);
  1234. else
  1235. gb_tiling_config |= BANK_TILING(0);
  1236. }
  1237. rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
  1238. gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
  1239. if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
  1240. gb_tiling_config |= ROW_TILING(3);
  1241. gb_tiling_config |= SAMPLE_SPLIT(3);
  1242. } else {
  1243. gb_tiling_config |=
  1244. ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  1245. gb_tiling_config |=
  1246. SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  1247. }
  1248. gb_tiling_config |= BANK_SWAPS(1);
  1249. rdev->config.rv770.tile_config = gb_tiling_config;
  1250. WREG32(GB_TILING_CONFIG, gb_tiling_config);
  1251. WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1252. WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1253. WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1254. WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
  1255. if (rdev->family == CHIP_RV730) {
  1256. WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1257. WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1258. WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
  1259. }
  1260. WREG32(CGTS_SYS_TCC_DISABLE, 0);
  1261. WREG32(CGTS_TCC_DISABLE, 0);
  1262. WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
  1263. WREG32(CGTS_USER_TCC_DISABLE, 0);
  1264. num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
  1265. WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
  1266. WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
  1267. /* set HW defaults for 3D engine */
  1268. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  1269. ROQ_IB2_START(0x2b)));
  1270. WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
  1271. ta_aux_cntl = RREG32(TA_CNTL_AUX);
  1272. WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
  1273. sx_debug_1 = RREG32(SX_DEBUG_1);
  1274. sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
  1275. WREG32(SX_DEBUG_1, sx_debug_1);
  1276. smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
  1277. smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
  1278. smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
  1279. WREG32(SMX_DC_CTL0, smx_dc_ctl0);
  1280. if (rdev->family != CHIP_RV740)
  1281. WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
  1282. GS_FLUSH_CTL(4) |
  1283. ACK_FLUSH_CTL(3) |
  1284. SYNC_FLUSH_CTL));
  1285. if (rdev->family != CHIP_RV770)
  1286. WREG32(SMX_SAR_CTL0, 0x00003f3f);
  1287. db_debug3 = RREG32(DB_DEBUG3);
  1288. db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
  1289. switch (rdev->family) {
  1290. case CHIP_RV770:
  1291. case CHIP_RV740:
  1292. db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
  1293. break;
  1294. case CHIP_RV710:
  1295. case CHIP_RV730:
  1296. default:
  1297. db_debug3 |= DB_CLK_OFF_DELAY(2);
  1298. break;
  1299. }
  1300. WREG32(DB_DEBUG3, db_debug3);
  1301. if (rdev->family != CHIP_RV770) {
  1302. db_debug4 = RREG32(DB_DEBUG4);
  1303. db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
  1304. WREG32(DB_DEBUG4, db_debug4);
  1305. }
  1306. WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
  1307. POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
  1308. SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
  1309. WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
  1310. SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
  1311. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
  1312. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  1313. WREG32(VGT_NUM_INSTANCES, 1);
  1314. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  1315. WREG32(CP_PERFMON_CNTL, 0);
  1316. sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
  1317. DONE_FIFO_HIWATER(0xe0) |
  1318. ALU_UPDATE_FIFO_HIWATER(0x8));
  1319. switch (rdev->family) {
  1320. case CHIP_RV770:
  1321. case CHIP_RV730:
  1322. case CHIP_RV710:
  1323. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
  1324. break;
  1325. case CHIP_RV740:
  1326. default:
  1327. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
  1328. break;
  1329. }
  1330. WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
  1331. /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
  1332. * should be adjusted as needed by the 2D/3D drivers. This just sets default values
  1333. */
  1334. sq_config = RREG32(SQ_CONFIG);
  1335. sq_config &= ~(PS_PRIO(3) |
  1336. VS_PRIO(3) |
  1337. GS_PRIO(3) |
  1338. ES_PRIO(3));
  1339. sq_config |= (DX9_CONSTS |
  1340. VC_ENABLE |
  1341. EXPORT_SRC_C |
  1342. PS_PRIO(0) |
  1343. VS_PRIO(1) |
  1344. GS_PRIO(2) |
  1345. ES_PRIO(3));
  1346. if (rdev->family == CHIP_RV710)
  1347. /* no vertex cache */
  1348. sq_config &= ~VC_ENABLE;
  1349. WREG32(SQ_CONFIG, sq_config);
  1350. WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  1351. NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  1352. NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
  1353. WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
  1354. NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
  1355. sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
  1356. NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
  1357. NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
  1358. if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
  1359. sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
  1360. else
  1361. sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
  1362. WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
  1363. WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  1364. NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  1365. WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  1366. NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  1367. sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  1368. SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
  1369. SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  1370. SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
  1371. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
  1372. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
  1373. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
  1374. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
  1375. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
  1376. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
  1377. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
  1378. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
  1379. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  1380. FORCE_EOV_MAX_REZ_CNT(255)));
  1381. if (rdev->family == CHIP_RV710)
  1382. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
  1383. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  1384. else
  1385. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
  1386. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  1387. switch (rdev->family) {
  1388. case CHIP_RV770:
  1389. case CHIP_RV730:
  1390. case CHIP_RV740:
  1391. gs_prim_buffer_depth = 384;
  1392. break;
  1393. case CHIP_RV710:
  1394. gs_prim_buffer_depth = 128;
  1395. break;
  1396. default:
  1397. break;
  1398. }
  1399. num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
  1400. vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
  1401. /* Max value for this is 256 */
  1402. if (vgt_gs_per_es > 256)
  1403. vgt_gs_per_es = 256;
  1404. WREG32(VGT_ES_PER_GS, 128);
  1405. WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
  1406. WREG32(VGT_GS_PER_VS, 2);
  1407. /* more default values. 2D/3D driver should adjust as needed */
  1408. WREG32(VGT_GS_VERTEX_REUSE, 16);
  1409. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  1410. WREG32(VGT_STRMOUT_EN, 0);
  1411. WREG32(SX_MISC, 0);
  1412. WREG32(PA_SC_MODE_CNTL, 0);
  1413. WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
  1414. WREG32(PA_SC_AA_CONFIG, 0);
  1415. WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
  1416. WREG32(PA_SC_LINE_STIPPLE, 0);
  1417. WREG32(SPI_INPUT_Z, 0);
  1418. WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
  1419. WREG32(CB_COLOR7_FRAG, 0);
  1420. /* clear render buffer base addresses */
  1421. WREG32(CB_COLOR0_BASE, 0);
  1422. WREG32(CB_COLOR1_BASE, 0);
  1423. WREG32(CB_COLOR2_BASE, 0);
  1424. WREG32(CB_COLOR3_BASE, 0);
  1425. WREG32(CB_COLOR4_BASE, 0);
  1426. WREG32(CB_COLOR5_BASE, 0);
  1427. WREG32(CB_COLOR6_BASE, 0);
  1428. WREG32(CB_COLOR7_BASE, 0);
  1429. WREG32(TCP_CNTL, 0);
  1430. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  1431. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  1432. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  1433. WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
  1434. NUM_CLIP_SEQ(3)));
  1435. WREG32(VC_ENHANCE, 0);
  1436. }
  1437. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  1438. {
  1439. u64 size_bf, size_af;
  1440. if (mc->mc_vram_size > 0xE0000000) {
  1441. /* leave room for at least 512M GTT */
  1442. dev_warn(rdev->dev, "limiting VRAM\n");
  1443. mc->real_vram_size = 0xE0000000;
  1444. mc->mc_vram_size = 0xE0000000;
  1445. }
  1446. if (rdev->flags & RADEON_IS_AGP) {
  1447. size_bf = mc->gtt_start;
  1448. size_af = mc->mc_mask - mc->gtt_end;
  1449. if (size_bf > size_af) {
  1450. if (mc->mc_vram_size > size_bf) {
  1451. dev_warn(rdev->dev, "limiting VRAM\n");
  1452. mc->real_vram_size = size_bf;
  1453. mc->mc_vram_size = size_bf;
  1454. }
  1455. mc->vram_start = mc->gtt_start - mc->mc_vram_size;
  1456. } else {
  1457. if (mc->mc_vram_size > size_af) {
  1458. dev_warn(rdev->dev, "limiting VRAM\n");
  1459. mc->real_vram_size = size_af;
  1460. mc->mc_vram_size = size_af;
  1461. }
  1462. mc->vram_start = mc->gtt_end + 1;
  1463. }
  1464. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  1465. dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
  1466. mc->mc_vram_size >> 20, mc->vram_start,
  1467. mc->vram_end, mc->real_vram_size >> 20);
  1468. } else {
  1469. radeon_vram_location(rdev, &rdev->mc, 0);
  1470. rdev->mc.gtt_base_align = 0;
  1471. radeon_gtt_location(rdev, mc);
  1472. }
  1473. }
  1474. static int rv770_mc_init(struct radeon_device *rdev)
  1475. {
  1476. u32 tmp;
  1477. int chansize, numchan;
  1478. /* Get VRAM informations */
  1479. rdev->mc.vram_is_ddr = true;
  1480. tmp = RREG32(MC_ARB_RAMCFG);
  1481. if (tmp & CHANSIZE_OVERRIDE) {
  1482. chansize = 16;
  1483. } else if (tmp & CHANSIZE_MASK) {
  1484. chansize = 64;
  1485. } else {
  1486. chansize = 32;
  1487. }
  1488. tmp = RREG32(MC_SHARED_CHMAP);
  1489. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  1490. case 0:
  1491. default:
  1492. numchan = 1;
  1493. break;
  1494. case 1:
  1495. numchan = 2;
  1496. break;
  1497. case 2:
  1498. numchan = 4;
  1499. break;
  1500. case 3:
  1501. numchan = 8;
  1502. break;
  1503. }
  1504. rdev->mc.vram_width = numchan * chansize;
  1505. /* Could aper size report 0 ? */
  1506. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  1507. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  1508. /* Setup GPU memory space */
  1509. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
  1510. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
  1511. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  1512. r700_vram_gtt_location(rdev, &rdev->mc);
  1513. radeon_update_bandwidth_info(rdev);
  1514. return 0;
  1515. }
  1516. static int rv770_startup(struct radeon_device *rdev)
  1517. {
  1518. struct radeon_ring *ring;
  1519. int r;
  1520. /* enable pcie gen2 link */
  1521. rv770_pcie_gen2_enable(rdev);
  1522. /* scratch needs to be initialized before MC */
  1523. r = r600_vram_scratch_init(rdev);
  1524. if (r)
  1525. return r;
  1526. rv770_mc_program(rdev);
  1527. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  1528. r = r600_init_microcode(rdev);
  1529. if (r) {
  1530. DRM_ERROR("Failed to load firmware!\n");
  1531. return r;
  1532. }
  1533. }
  1534. if (rdev->flags & RADEON_IS_AGP) {
  1535. rv770_agp_enable(rdev);
  1536. } else {
  1537. r = rv770_pcie_gart_enable(rdev);
  1538. if (r)
  1539. return r;
  1540. }
  1541. rv770_gpu_init(rdev);
  1542. /* allocate wb buffer */
  1543. r = radeon_wb_init(rdev);
  1544. if (r)
  1545. return r;
  1546. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  1547. if (r) {
  1548. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  1549. return r;
  1550. }
  1551. r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
  1552. if (r) {
  1553. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  1554. return r;
  1555. }
  1556. r = uvd_v2_2_resume(rdev);
  1557. if (!r) {
  1558. r = radeon_fence_driver_start_ring(rdev,
  1559. R600_RING_TYPE_UVD_INDEX);
  1560. if (r)
  1561. dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
  1562. }
  1563. if (r)
  1564. rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
  1565. /* Enable IRQ */
  1566. if (!rdev->irq.installed) {
  1567. r = radeon_irq_kms_init(rdev);
  1568. if (r)
  1569. return r;
  1570. }
  1571. r = r600_irq_init(rdev);
  1572. if (r) {
  1573. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  1574. radeon_irq_kms_fini(rdev);
  1575. return r;
  1576. }
  1577. r600_irq_set(rdev);
  1578. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1579. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  1580. R600_CP_RB_RPTR, R600_CP_RB_WPTR,
  1581. RADEON_CP_PACKET2);
  1582. if (r)
  1583. return r;
  1584. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  1585. r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
  1586. DMA_RB_RPTR, DMA_RB_WPTR,
  1587. DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
  1588. if (r)
  1589. return r;
  1590. r = rv770_cp_load_microcode(rdev);
  1591. if (r)
  1592. return r;
  1593. r = r600_cp_resume(rdev);
  1594. if (r)
  1595. return r;
  1596. r = r600_dma_resume(rdev);
  1597. if (r)
  1598. return r;
  1599. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  1600. if (ring->ring_size) {
  1601. r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
  1602. UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
  1603. RADEON_CP_PACKET2);
  1604. if (!r)
  1605. r = uvd_v1_0_init(rdev);
  1606. if (r)
  1607. DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
  1608. }
  1609. r = radeon_ib_pool_init(rdev);
  1610. if (r) {
  1611. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  1612. return r;
  1613. }
  1614. r = r600_audio_init(rdev);
  1615. if (r) {
  1616. DRM_ERROR("radeon: audio init failed\n");
  1617. return r;
  1618. }
  1619. return 0;
  1620. }
  1621. int rv770_resume(struct radeon_device *rdev)
  1622. {
  1623. int r;
  1624. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  1625. * posting will perform necessary task to bring back GPU into good
  1626. * shape.
  1627. */
  1628. /* post card */
  1629. atom_asic_init(rdev->mode_info.atom_context);
  1630. /* init golden registers */
  1631. rv770_init_golden_registers(rdev);
  1632. rdev->accel_working = true;
  1633. r = rv770_startup(rdev);
  1634. if (r) {
  1635. DRM_ERROR("r600 startup failed on resume\n");
  1636. rdev->accel_working = false;
  1637. return r;
  1638. }
  1639. return r;
  1640. }
  1641. int rv770_suspend(struct radeon_device *rdev)
  1642. {
  1643. r600_audio_fini(rdev);
  1644. uvd_v1_0_fini(rdev);
  1645. radeon_uvd_suspend(rdev);
  1646. r700_cp_stop(rdev);
  1647. r600_dma_stop(rdev);
  1648. r600_irq_suspend(rdev);
  1649. radeon_wb_disable(rdev);
  1650. rv770_pcie_gart_disable(rdev);
  1651. return 0;
  1652. }
  1653. /* Plan is to move initialization in that function and use
  1654. * helper function so that radeon_device_init pretty much
  1655. * do nothing more than calling asic specific function. This
  1656. * should also allow to remove a bunch of callback function
  1657. * like vram_info.
  1658. */
  1659. int rv770_init(struct radeon_device *rdev)
  1660. {
  1661. int r;
  1662. /* Read BIOS */
  1663. if (!radeon_get_bios(rdev)) {
  1664. if (ASIC_IS_AVIVO(rdev))
  1665. return -EINVAL;
  1666. }
  1667. /* Must be an ATOMBIOS */
  1668. if (!rdev->is_atom_bios) {
  1669. dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
  1670. return -EINVAL;
  1671. }
  1672. r = radeon_atombios_init(rdev);
  1673. if (r)
  1674. return r;
  1675. /* Post card if necessary */
  1676. if (!radeon_card_posted(rdev)) {
  1677. if (!rdev->bios) {
  1678. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  1679. return -EINVAL;
  1680. }
  1681. DRM_INFO("GPU not posted. posting now...\n");
  1682. atom_asic_init(rdev->mode_info.atom_context);
  1683. }
  1684. /* init golden registers */
  1685. rv770_init_golden_registers(rdev);
  1686. /* Initialize scratch registers */
  1687. r600_scratch_init(rdev);
  1688. /* Initialize surface registers */
  1689. radeon_surface_init(rdev);
  1690. /* Initialize clocks */
  1691. radeon_get_clock_info(rdev->ddev);
  1692. /* Fence driver */
  1693. r = radeon_fence_driver_init(rdev);
  1694. if (r)
  1695. return r;
  1696. /* initialize AGP */
  1697. if (rdev->flags & RADEON_IS_AGP) {
  1698. r = radeon_agp_init(rdev);
  1699. if (r)
  1700. radeon_agp_disable(rdev);
  1701. }
  1702. r = rv770_mc_init(rdev);
  1703. if (r)
  1704. return r;
  1705. /* Memory manager */
  1706. r = radeon_bo_init(rdev);
  1707. if (r)
  1708. return r;
  1709. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
  1710. r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
  1711. rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
  1712. r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
  1713. r = radeon_uvd_init(rdev);
  1714. if (!r) {
  1715. rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
  1716. r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
  1717. 4096);
  1718. }
  1719. rdev->ih.ring_obj = NULL;
  1720. r600_ih_ring_init(rdev, 64 * 1024);
  1721. r = r600_pcie_gart_init(rdev);
  1722. if (r)
  1723. return r;
  1724. rdev->accel_working = true;
  1725. r = rv770_startup(rdev);
  1726. if (r) {
  1727. dev_err(rdev->dev, "disabling GPU acceleration\n");
  1728. r700_cp_fini(rdev);
  1729. r600_dma_fini(rdev);
  1730. r600_irq_fini(rdev);
  1731. radeon_wb_fini(rdev);
  1732. radeon_ib_pool_fini(rdev);
  1733. radeon_irq_kms_fini(rdev);
  1734. rv770_pcie_gart_fini(rdev);
  1735. rdev->accel_working = false;
  1736. }
  1737. return 0;
  1738. }
  1739. void rv770_fini(struct radeon_device *rdev)
  1740. {
  1741. r700_cp_fini(rdev);
  1742. r600_dma_fini(rdev);
  1743. r600_irq_fini(rdev);
  1744. radeon_wb_fini(rdev);
  1745. radeon_ib_pool_fini(rdev);
  1746. radeon_irq_kms_fini(rdev);
  1747. rv770_pcie_gart_fini(rdev);
  1748. uvd_v1_0_fini(rdev);
  1749. radeon_uvd_fini(rdev);
  1750. r600_vram_scratch_fini(rdev);
  1751. radeon_gem_fini(rdev);
  1752. radeon_fence_driver_fini(rdev);
  1753. radeon_agp_fini(rdev);
  1754. radeon_bo_fini(rdev);
  1755. radeon_atombios_fini(rdev);
  1756. kfree(rdev->bios);
  1757. rdev->bios = NULL;
  1758. }
  1759. static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
  1760. {
  1761. u32 link_width_cntl, lanes, speed_cntl, tmp;
  1762. u16 link_cntl2;
  1763. if (radeon_pcie_gen2 == 0)
  1764. return;
  1765. if (rdev->flags & RADEON_IS_IGP)
  1766. return;
  1767. if (!(rdev->flags & RADEON_IS_PCIE))
  1768. return;
  1769. /* x2 cards have a special sequence */
  1770. if (ASIC_IS_X2(rdev))
  1771. return;
  1772. if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
  1773. (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
  1774. return;
  1775. DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
  1776. /* advertise upconfig capability */
  1777. link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  1778. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  1779. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1780. link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  1781. if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
  1782. lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
  1783. link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
  1784. LC_RECONFIG_ARC_MISSING_ESCAPE);
  1785. link_width_cntl |= lanes | LC_RECONFIG_NOW |
  1786. LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
  1787. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1788. } else {
  1789. link_width_cntl |= LC_UPCONFIGURE_DIS;
  1790. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1791. }
  1792. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1793. if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  1794. (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  1795. tmp = RREG32(0x541c);
  1796. WREG32(0x541c, tmp | 0x8);
  1797. WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
  1798. link_cntl2 = RREG16(0x4088);
  1799. link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
  1800. link_cntl2 |= 0x2;
  1801. WREG16(0x4088, link_cntl2);
  1802. WREG32(MM_CFGREGS_CNTL, 0);
  1803. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1804. speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
  1805. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1806. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1807. speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
  1808. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1809. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1810. speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
  1811. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1812. speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  1813. speed_cntl |= LC_GEN2_EN_STRAP;
  1814. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
  1815. } else {
  1816. link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
  1817. /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
  1818. if (1)
  1819. link_width_cntl |= LC_UPCONFIGURE_DIS;
  1820. else
  1821. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  1822. WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1823. }
  1824. }