rv515.c 40 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305
  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include "rv515d.h"
  32. #include "radeon.h"
  33. #include "radeon_asic.h"
  34. #include "atom.h"
  35. #include "rv515_reg_safe.h"
  36. /* This files gather functions specifics to: rv515 */
  37. static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  38. static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  39. static void rv515_gpu_init(struct radeon_device *rdev);
  40. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  41. static const u32 crtc_offsets[2] =
  42. {
  43. 0,
  44. AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  45. };
  46. void rv515_debugfs(struct radeon_device *rdev)
  47. {
  48. if (r100_debugfs_rbbm_init(rdev)) {
  49. DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  50. }
  51. if (rv515_debugfs_pipes_info_init(rdev)) {
  52. DRM_ERROR("Failed to register debugfs file for pipes !\n");
  53. }
  54. if (rv515_debugfs_ga_info_init(rdev)) {
  55. DRM_ERROR("Failed to register debugfs file for pipes !\n");
  56. }
  57. }
  58. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  59. {
  60. int r;
  61. r = radeon_ring_lock(rdev, ring, 64);
  62. if (r) {
  63. return;
  64. }
  65. radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
  66. radeon_ring_write(ring,
  67. ISYNC_ANY2D_IDLE3D |
  68. ISYNC_ANY3D_IDLE2D |
  69. ISYNC_WAIT_IDLEGUI |
  70. ISYNC_CPSCRATCH_IDLEGUI);
  71. radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  72. radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  73. radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  74. radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  75. radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
  76. radeon_ring_write(ring, 0);
  77. radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
  78. radeon_ring_write(ring, 0);
  79. radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
  80. radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
  81. radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
  82. radeon_ring_write(ring, 0);
  83. radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  84. radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  85. radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  86. radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  87. radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  88. radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  89. radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
  90. radeon_ring_write(ring, 0);
  91. radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  92. radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  93. radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  94. radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  95. radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
  96. radeon_ring_write(ring,
  97. ((6 << MS_X0_SHIFT) |
  98. (6 << MS_Y0_SHIFT) |
  99. (6 << MS_X1_SHIFT) |
  100. (6 << MS_Y1_SHIFT) |
  101. (6 << MS_X2_SHIFT) |
  102. (6 << MS_Y2_SHIFT) |
  103. (6 << MSBD0_Y_SHIFT) |
  104. (6 << MSBD0_X_SHIFT)));
  105. radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
  106. radeon_ring_write(ring,
  107. ((6 << MS_X3_SHIFT) |
  108. (6 << MS_Y3_SHIFT) |
  109. (6 << MS_X4_SHIFT) |
  110. (6 << MS_Y4_SHIFT) |
  111. (6 << MS_X5_SHIFT) |
  112. (6 << MS_Y5_SHIFT) |
  113. (6 << MSBD1_SHIFT)));
  114. radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
  115. radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
  116. radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
  117. radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
  118. radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
  119. radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
  120. radeon_ring_write(ring, PACKET0(0x20C8, 0));
  121. radeon_ring_write(ring, 0);
  122. radeon_ring_unlock_commit(rdev, ring);
  123. }
  124. int rv515_mc_wait_for_idle(struct radeon_device *rdev)
  125. {
  126. unsigned i;
  127. uint32_t tmp;
  128. for (i = 0; i < rdev->usec_timeout; i++) {
  129. /* read MC_STATUS */
  130. tmp = RREG32_MC(MC_STATUS);
  131. if (tmp & MC_STATUS_IDLE) {
  132. return 0;
  133. }
  134. DRM_UDELAY(1);
  135. }
  136. return -1;
  137. }
  138. void rv515_vga_render_disable(struct radeon_device *rdev)
  139. {
  140. WREG32(R_000300_VGA_RENDER_CONTROL,
  141. RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
  142. }
  143. static void rv515_gpu_init(struct radeon_device *rdev)
  144. {
  145. unsigned pipe_select_current, gb_pipe_select, tmp;
  146. if (r100_gui_wait_for_idle(rdev)) {
  147. printk(KERN_WARNING "Failed to wait GUI idle while "
  148. "resetting GPU. Bad things might happen.\n");
  149. }
  150. rv515_vga_render_disable(rdev);
  151. r420_pipes_init(rdev);
  152. gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
  153. tmp = RREG32(R300_DST_PIPE_CONFIG);
  154. pipe_select_current = (tmp >> 2) & 3;
  155. tmp = (1 << pipe_select_current) |
  156. (((gb_pipe_select >> 8) & 0xF) << 4);
  157. WREG32_PLL(0x000D, tmp);
  158. if (r100_gui_wait_for_idle(rdev)) {
  159. printk(KERN_WARNING "Failed to wait GUI idle while "
  160. "resetting GPU. Bad things might happen.\n");
  161. }
  162. if (rv515_mc_wait_for_idle(rdev)) {
  163. printk(KERN_WARNING "Failed to wait MC idle while "
  164. "programming pipes. Bad things might happen.\n");
  165. }
  166. }
  167. static void rv515_vram_get_type(struct radeon_device *rdev)
  168. {
  169. uint32_t tmp;
  170. rdev->mc.vram_width = 128;
  171. rdev->mc.vram_is_ddr = true;
  172. tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
  173. switch (tmp) {
  174. case 0:
  175. rdev->mc.vram_width = 64;
  176. break;
  177. case 1:
  178. rdev->mc.vram_width = 128;
  179. break;
  180. default:
  181. rdev->mc.vram_width = 128;
  182. break;
  183. }
  184. }
  185. static void rv515_mc_init(struct radeon_device *rdev)
  186. {
  187. rv515_vram_get_type(rdev);
  188. r100_vram_init_sizes(rdev);
  189. radeon_vram_location(rdev, &rdev->mc, 0);
  190. rdev->mc.gtt_base_align = 0;
  191. if (!(rdev->flags & RADEON_IS_AGP))
  192. radeon_gtt_location(rdev, &rdev->mc);
  193. radeon_update_bandwidth_info(rdev);
  194. }
  195. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  196. {
  197. unsigned long flags;
  198. uint32_t r;
  199. spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  200. WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
  201. r = RREG32(MC_IND_DATA);
  202. WREG32(MC_IND_INDEX, 0);
  203. spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  204. return r;
  205. }
  206. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  207. {
  208. unsigned long flags;
  209. spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  210. WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
  211. WREG32(MC_IND_DATA, (v));
  212. WREG32(MC_IND_INDEX, 0);
  213. spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  214. }
  215. #if defined(CONFIG_DEBUG_FS)
  216. static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
  217. {
  218. struct drm_info_node *node = (struct drm_info_node *) m->private;
  219. struct drm_device *dev = node->minor->dev;
  220. struct radeon_device *rdev = dev->dev_private;
  221. uint32_t tmp;
  222. tmp = RREG32(GB_PIPE_SELECT);
  223. seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
  224. tmp = RREG32(SU_REG_DEST);
  225. seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
  226. tmp = RREG32(GB_TILE_CONFIG);
  227. seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
  228. tmp = RREG32(DST_PIPE_CONFIG);
  229. seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
  230. return 0;
  231. }
  232. static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
  233. {
  234. struct drm_info_node *node = (struct drm_info_node *) m->private;
  235. struct drm_device *dev = node->minor->dev;
  236. struct radeon_device *rdev = dev->dev_private;
  237. uint32_t tmp;
  238. tmp = RREG32(0x2140);
  239. seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
  240. radeon_asic_reset(rdev);
  241. tmp = RREG32(0x425C);
  242. seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
  243. return 0;
  244. }
  245. static struct drm_info_list rv515_pipes_info_list[] = {
  246. {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
  247. };
  248. static struct drm_info_list rv515_ga_info_list[] = {
  249. {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
  250. };
  251. #endif
  252. static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
  253. {
  254. #if defined(CONFIG_DEBUG_FS)
  255. return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
  256. #else
  257. return 0;
  258. #endif
  259. }
  260. static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
  261. {
  262. #if defined(CONFIG_DEBUG_FS)
  263. return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
  264. #else
  265. return 0;
  266. #endif
  267. }
  268. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
  269. {
  270. u32 crtc_enabled, tmp, frame_count, blackout;
  271. int i, j;
  272. save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
  273. save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
  274. /* disable VGA render */
  275. WREG32(R_000300_VGA_RENDER_CONTROL, 0);
  276. /* blank the display controllers */
  277. for (i = 0; i < rdev->num_crtc; i++) {
  278. crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
  279. if (crtc_enabled) {
  280. save->crtc_enabled[i] = true;
  281. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  282. if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
  283. radeon_wait_for_vblank(rdev, i);
  284. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  285. tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  286. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  287. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  288. }
  289. /* wait for the next frame */
  290. frame_count = radeon_get_vblank_counter(rdev, i);
  291. for (j = 0; j < rdev->usec_timeout; j++) {
  292. if (radeon_get_vblank_counter(rdev, i) != frame_count)
  293. break;
  294. udelay(1);
  295. }
  296. /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
  297. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  298. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  299. tmp &= ~AVIVO_CRTC_EN;
  300. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  301. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  302. save->crtc_enabled[i] = false;
  303. /* ***** */
  304. } else {
  305. save->crtc_enabled[i] = false;
  306. }
  307. }
  308. radeon_mc_wait_for_idle(rdev);
  309. if (rdev->family >= CHIP_R600) {
  310. if (rdev->family >= CHIP_RV770)
  311. blackout = RREG32(R700_MC_CITF_CNTL);
  312. else
  313. blackout = RREG32(R600_CITF_CNTL);
  314. if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
  315. /* Block CPU access */
  316. WREG32(R600_BIF_FB_EN, 0);
  317. /* blackout the MC */
  318. blackout |= R600_BLACKOUT_MASK;
  319. if (rdev->family >= CHIP_RV770)
  320. WREG32(R700_MC_CITF_CNTL, blackout);
  321. else
  322. WREG32(R600_CITF_CNTL, blackout);
  323. }
  324. }
  325. /* wait for the MC to settle */
  326. udelay(100);
  327. /* lock double buffered regs */
  328. for (i = 0; i < rdev->num_crtc; i++) {
  329. if (save->crtc_enabled[i]) {
  330. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  331. if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
  332. tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  333. WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
  334. }
  335. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
  336. if (!(tmp & 1)) {
  337. tmp |= 1;
  338. WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  339. }
  340. }
  341. }
  342. }
  343. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
  344. {
  345. u32 tmp, frame_count;
  346. int i, j;
  347. /* update crtc base addresses */
  348. for (i = 0; i < rdev->num_crtc; i++) {
  349. if (rdev->family >= CHIP_RV770) {
  350. if (i == 0) {
  351. WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
  352. upper_32_bits(rdev->mc.vram_start));
  353. WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
  354. upper_32_bits(rdev->mc.vram_start));
  355. } else {
  356. WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
  357. upper_32_bits(rdev->mc.vram_start));
  358. WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
  359. upper_32_bits(rdev->mc.vram_start));
  360. }
  361. }
  362. WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
  363. (u32)rdev->mc.vram_start);
  364. WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
  365. (u32)rdev->mc.vram_start);
  366. }
  367. WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
  368. /* unlock regs and wait for update */
  369. for (i = 0; i < rdev->num_crtc; i++) {
  370. if (save->crtc_enabled[i]) {
  371. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
  372. if ((tmp & 0x3) != 0) {
  373. tmp &= ~0x3;
  374. WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
  375. }
  376. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  377. if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
  378. tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  379. WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
  380. }
  381. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
  382. if (tmp & 1) {
  383. tmp &= ~1;
  384. WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  385. }
  386. for (j = 0; j < rdev->usec_timeout; j++) {
  387. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  388. if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
  389. break;
  390. udelay(1);
  391. }
  392. }
  393. }
  394. if (rdev->family >= CHIP_R600) {
  395. /* unblackout the MC */
  396. if (rdev->family >= CHIP_RV770)
  397. tmp = RREG32(R700_MC_CITF_CNTL);
  398. else
  399. tmp = RREG32(R600_CITF_CNTL);
  400. tmp &= ~R600_BLACKOUT_MASK;
  401. if (rdev->family >= CHIP_RV770)
  402. WREG32(R700_MC_CITF_CNTL, tmp);
  403. else
  404. WREG32(R600_CITF_CNTL, tmp);
  405. /* allow CPU access */
  406. WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
  407. }
  408. for (i = 0; i < rdev->num_crtc; i++) {
  409. if (save->crtc_enabled[i]) {
  410. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  411. tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  412. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  413. /* wait for the next frame */
  414. frame_count = radeon_get_vblank_counter(rdev, i);
  415. for (j = 0; j < rdev->usec_timeout; j++) {
  416. if (radeon_get_vblank_counter(rdev, i) != frame_count)
  417. break;
  418. udelay(1);
  419. }
  420. }
  421. }
  422. /* Unlock vga access */
  423. WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
  424. mdelay(1);
  425. WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
  426. }
  427. static void rv515_mc_program(struct radeon_device *rdev)
  428. {
  429. struct rv515_mc_save save;
  430. /* Stops all mc clients */
  431. rv515_mc_stop(rdev, &save);
  432. /* Wait for mc idle */
  433. if (rv515_mc_wait_for_idle(rdev))
  434. dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  435. /* Write VRAM size in case we are limiting it */
  436. WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  437. /* Program MC, should be a 32bits limited address space */
  438. WREG32_MC(R_000001_MC_FB_LOCATION,
  439. S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
  440. S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
  441. WREG32(R_000134_HDP_FB_LOCATION,
  442. S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  443. if (rdev->flags & RADEON_IS_AGP) {
  444. WREG32_MC(R_000002_MC_AGP_LOCATION,
  445. S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  446. S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  447. WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  448. WREG32_MC(R_000004_MC_AGP_BASE_2,
  449. S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
  450. } else {
  451. WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
  452. WREG32_MC(R_000003_MC_AGP_BASE, 0);
  453. WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
  454. }
  455. rv515_mc_resume(rdev, &save);
  456. }
  457. void rv515_clock_startup(struct radeon_device *rdev)
  458. {
  459. if (radeon_dynclks != -1 && radeon_dynclks)
  460. radeon_atom_set_clock_gating(rdev, 1);
  461. /* We need to force on some of the block */
  462. WREG32_PLL(R_00000F_CP_DYN_CNTL,
  463. RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
  464. WREG32_PLL(R_000011_E2_DYN_CNTL,
  465. RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
  466. WREG32_PLL(R_000013_IDCT_DYN_CNTL,
  467. RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
  468. }
  469. static int rv515_startup(struct radeon_device *rdev)
  470. {
  471. int r;
  472. rv515_mc_program(rdev);
  473. /* Resume clock */
  474. rv515_clock_startup(rdev);
  475. /* Initialize GPU configuration (# pipes, ...) */
  476. rv515_gpu_init(rdev);
  477. /* Initialize GART (initialize after TTM so we can allocate
  478. * memory through TTM but finalize after TTM) */
  479. if (rdev->flags & RADEON_IS_PCIE) {
  480. r = rv370_pcie_gart_enable(rdev);
  481. if (r)
  482. return r;
  483. }
  484. /* allocate wb buffer */
  485. r = radeon_wb_init(rdev);
  486. if (r)
  487. return r;
  488. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  489. if (r) {
  490. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  491. return r;
  492. }
  493. /* Enable IRQ */
  494. if (!rdev->irq.installed) {
  495. r = radeon_irq_kms_init(rdev);
  496. if (r)
  497. return r;
  498. }
  499. rs600_irq_set(rdev);
  500. rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  501. /* 1M ring buffer */
  502. r = r100_cp_init(rdev, 1024 * 1024);
  503. if (r) {
  504. dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  505. return r;
  506. }
  507. r = radeon_ib_pool_init(rdev);
  508. if (r) {
  509. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  510. return r;
  511. }
  512. return 0;
  513. }
  514. int rv515_resume(struct radeon_device *rdev)
  515. {
  516. int r;
  517. /* Make sur GART are not working */
  518. if (rdev->flags & RADEON_IS_PCIE)
  519. rv370_pcie_gart_disable(rdev);
  520. /* Resume clock before doing reset */
  521. rv515_clock_startup(rdev);
  522. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  523. if (radeon_asic_reset(rdev)) {
  524. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  525. RREG32(R_000E40_RBBM_STATUS),
  526. RREG32(R_0007C0_CP_STAT));
  527. }
  528. /* post */
  529. atom_asic_init(rdev->mode_info.atom_context);
  530. /* Resume clock after posting */
  531. rv515_clock_startup(rdev);
  532. /* Initialize surface registers */
  533. radeon_surface_init(rdev);
  534. rdev->accel_working = true;
  535. r = rv515_startup(rdev);
  536. if (r) {
  537. rdev->accel_working = false;
  538. }
  539. return r;
  540. }
  541. int rv515_suspend(struct radeon_device *rdev)
  542. {
  543. r100_cp_disable(rdev);
  544. radeon_wb_disable(rdev);
  545. rs600_irq_disable(rdev);
  546. if (rdev->flags & RADEON_IS_PCIE)
  547. rv370_pcie_gart_disable(rdev);
  548. return 0;
  549. }
  550. void rv515_set_safe_registers(struct radeon_device *rdev)
  551. {
  552. rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
  553. rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
  554. }
  555. void rv515_fini(struct radeon_device *rdev)
  556. {
  557. r100_cp_fini(rdev);
  558. radeon_wb_fini(rdev);
  559. radeon_ib_pool_fini(rdev);
  560. radeon_gem_fini(rdev);
  561. rv370_pcie_gart_fini(rdev);
  562. radeon_agp_fini(rdev);
  563. radeon_irq_kms_fini(rdev);
  564. radeon_fence_driver_fini(rdev);
  565. radeon_bo_fini(rdev);
  566. radeon_atombios_fini(rdev);
  567. kfree(rdev->bios);
  568. rdev->bios = NULL;
  569. }
  570. int rv515_init(struct radeon_device *rdev)
  571. {
  572. int r;
  573. /* Initialize scratch registers */
  574. radeon_scratch_init(rdev);
  575. /* Initialize surface registers */
  576. radeon_surface_init(rdev);
  577. /* TODO: disable VGA need to use VGA request */
  578. /* restore some register to sane defaults */
  579. r100_restore_sanity(rdev);
  580. /* BIOS*/
  581. if (!radeon_get_bios(rdev)) {
  582. if (ASIC_IS_AVIVO(rdev))
  583. return -EINVAL;
  584. }
  585. if (rdev->is_atom_bios) {
  586. r = radeon_atombios_init(rdev);
  587. if (r)
  588. return r;
  589. } else {
  590. dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
  591. return -EINVAL;
  592. }
  593. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  594. if (radeon_asic_reset(rdev)) {
  595. dev_warn(rdev->dev,
  596. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  597. RREG32(R_000E40_RBBM_STATUS),
  598. RREG32(R_0007C0_CP_STAT));
  599. }
  600. /* check if cards are posted or not */
  601. if (radeon_boot_test_post_card(rdev) == false)
  602. return -EINVAL;
  603. /* Initialize clocks */
  604. radeon_get_clock_info(rdev->ddev);
  605. /* initialize AGP */
  606. if (rdev->flags & RADEON_IS_AGP) {
  607. r = radeon_agp_init(rdev);
  608. if (r) {
  609. radeon_agp_disable(rdev);
  610. }
  611. }
  612. /* initialize memory controller */
  613. rv515_mc_init(rdev);
  614. rv515_debugfs(rdev);
  615. /* Fence driver */
  616. r = radeon_fence_driver_init(rdev);
  617. if (r)
  618. return r;
  619. /* Memory manager */
  620. r = radeon_bo_init(rdev);
  621. if (r)
  622. return r;
  623. r = rv370_pcie_gart_init(rdev);
  624. if (r)
  625. return r;
  626. rv515_set_safe_registers(rdev);
  627. rdev->accel_working = true;
  628. r = rv515_startup(rdev);
  629. if (r) {
  630. /* Somethings want wront with the accel init stop accel */
  631. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  632. r100_cp_fini(rdev);
  633. radeon_wb_fini(rdev);
  634. radeon_ib_pool_fini(rdev);
  635. radeon_irq_kms_fini(rdev);
  636. rv370_pcie_gart_fini(rdev);
  637. radeon_agp_fini(rdev);
  638. rdev->accel_working = false;
  639. }
  640. return 0;
  641. }
  642. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
  643. {
  644. int index_reg = 0x6578 + crtc->crtc_offset;
  645. int data_reg = 0x657c + crtc->crtc_offset;
  646. WREG32(0x659C + crtc->crtc_offset, 0x0);
  647. WREG32(0x6594 + crtc->crtc_offset, 0x705);
  648. WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
  649. WREG32(0x65D8 + crtc->crtc_offset, 0x0);
  650. WREG32(0x65B0 + crtc->crtc_offset, 0x0);
  651. WREG32(0x65C0 + crtc->crtc_offset, 0x0);
  652. WREG32(0x65D4 + crtc->crtc_offset, 0x0);
  653. WREG32(index_reg, 0x0);
  654. WREG32(data_reg, 0x841880A8);
  655. WREG32(index_reg, 0x1);
  656. WREG32(data_reg, 0x84208680);
  657. WREG32(index_reg, 0x2);
  658. WREG32(data_reg, 0xBFF880B0);
  659. WREG32(index_reg, 0x100);
  660. WREG32(data_reg, 0x83D88088);
  661. WREG32(index_reg, 0x101);
  662. WREG32(data_reg, 0x84608680);
  663. WREG32(index_reg, 0x102);
  664. WREG32(data_reg, 0xBFF080D0);
  665. WREG32(index_reg, 0x200);
  666. WREG32(data_reg, 0x83988068);
  667. WREG32(index_reg, 0x201);
  668. WREG32(data_reg, 0x84A08680);
  669. WREG32(index_reg, 0x202);
  670. WREG32(data_reg, 0xBFF080F8);
  671. WREG32(index_reg, 0x300);
  672. WREG32(data_reg, 0x83588058);
  673. WREG32(index_reg, 0x301);
  674. WREG32(data_reg, 0x84E08660);
  675. WREG32(index_reg, 0x302);
  676. WREG32(data_reg, 0xBFF88120);
  677. WREG32(index_reg, 0x400);
  678. WREG32(data_reg, 0x83188040);
  679. WREG32(index_reg, 0x401);
  680. WREG32(data_reg, 0x85008660);
  681. WREG32(index_reg, 0x402);
  682. WREG32(data_reg, 0xBFF88150);
  683. WREG32(index_reg, 0x500);
  684. WREG32(data_reg, 0x82D88030);
  685. WREG32(index_reg, 0x501);
  686. WREG32(data_reg, 0x85408640);
  687. WREG32(index_reg, 0x502);
  688. WREG32(data_reg, 0xBFF88180);
  689. WREG32(index_reg, 0x600);
  690. WREG32(data_reg, 0x82A08018);
  691. WREG32(index_reg, 0x601);
  692. WREG32(data_reg, 0x85808620);
  693. WREG32(index_reg, 0x602);
  694. WREG32(data_reg, 0xBFF081B8);
  695. WREG32(index_reg, 0x700);
  696. WREG32(data_reg, 0x82608010);
  697. WREG32(index_reg, 0x701);
  698. WREG32(data_reg, 0x85A08600);
  699. WREG32(index_reg, 0x702);
  700. WREG32(data_reg, 0x800081F0);
  701. WREG32(index_reg, 0x800);
  702. WREG32(data_reg, 0x8228BFF8);
  703. WREG32(index_reg, 0x801);
  704. WREG32(data_reg, 0x85E085E0);
  705. WREG32(index_reg, 0x802);
  706. WREG32(data_reg, 0xBFF88228);
  707. WREG32(index_reg, 0x10000);
  708. WREG32(data_reg, 0x82A8BF00);
  709. WREG32(index_reg, 0x10001);
  710. WREG32(data_reg, 0x82A08CC0);
  711. WREG32(index_reg, 0x10002);
  712. WREG32(data_reg, 0x8008BEF8);
  713. WREG32(index_reg, 0x10100);
  714. WREG32(data_reg, 0x81F0BF28);
  715. WREG32(index_reg, 0x10101);
  716. WREG32(data_reg, 0x83608CA0);
  717. WREG32(index_reg, 0x10102);
  718. WREG32(data_reg, 0x8018BED0);
  719. WREG32(index_reg, 0x10200);
  720. WREG32(data_reg, 0x8148BF38);
  721. WREG32(index_reg, 0x10201);
  722. WREG32(data_reg, 0x84408C80);
  723. WREG32(index_reg, 0x10202);
  724. WREG32(data_reg, 0x8008BEB8);
  725. WREG32(index_reg, 0x10300);
  726. WREG32(data_reg, 0x80B0BF78);
  727. WREG32(index_reg, 0x10301);
  728. WREG32(data_reg, 0x85008C20);
  729. WREG32(index_reg, 0x10302);
  730. WREG32(data_reg, 0x8020BEA0);
  731. WREG32(index_reg, 0x10400);
  732. WREG32(data_reg, 0x8028BF90);
  733. WREG32(index_reg, 0x10401);
  734. WREG32(data_reg, 0x85E08BC0);
  735. WREG32(index_reg, 0x10402);
  736. WREG32(data_reg, 0x8018BE90);
  737. WREG32(index_reg, 0x10500);
  738. WREG32(data_reg, 0xBFB8BFB0);
  739. WREG32(index_reg, 0x10501);
  740. WREG32(data_reg, 0x86C08B40);
  741. WREG32(index_reg, 0x10502);
  742. WREG32(data_reg, 0x8010BE90);
  743. WREG32(index_reg, 0x10600);
  744. WREG32(data_reg, 0xBF58BFC8);
  745. WREG32(index_reg, 0x10601);
  746. WREG32(data_reg, 0x87A08AA0);
  747. WREG32(index_reg, 0x10602);
  748. WREG32(data_reg, 0x8010BE98);
  749. WREG32(index_reg, 0x10700);
  750. WREG32(data_reg, 0xBF10BFF0);
  751. WREG32(index_reg, 0x10701);
  752. WREG32(data_reg, 0x886089E0);
  753. WREG32(index_reg, 0x10702);
  754. WREG32(data_reg, 0x8018BEB0);
  755. WREG32(index_reg, 0x10800);
  756. WREG32(data_reg, 0xBED8BFE8);
  757. WREG32(index_reg, 0x10801);
  758. WREG32(data_reg, 0x89408940);
  759. WREG32(index_reg, 0x10802);
  760. WREG32(data_reg, 0xBFE8BED8);
  761. WREG32(index_reg, 0x20000);
  762. WREG32(data_reg, 0x80008000);
  763. WREG32(index_reg, 0x20001);
  764. WREG32(data_reg, 0x90008000);
  765. WREG32(index_reg, 0x20002);
  766. WREG32(data_reg, 0x80008000);
  767. WREG32(index_reg, 0x20003);
  768. WREG32(data_reg, 0x80008000);
  769. WREG32(index_reg, 0x20100);
  770. WREG32(data_reg, 0x80108000);
  771. WREG32(index_reg, 0x20101);
  772. WREG32(data_reg, 0x8FE0BF70);
  773. WREG32(index_reg, 0x20102);
  774. WREG32(data_reg, 0xBFE880C0);
  775. WREG32(index_reg, 0x20103);
  776. WREG32(data_reg, 0x80008000);
  777. WREG32(index_reg, 0x20200);
  778. WREG32(data_reg, 0x8018BFF8);
  779. WREG32(index_reg, 0x20201);
  780. WREG32(data_reg, 0x8F80BF08);
  781. WREG32(index_reg, 0x20202);
  782. WREG32(data_reg, 0xBFD081A0);
  783. WREG32(index_reg, 0x20203);
  784. WREG32(data_reg, 0xBFF88000);
  785. WREG32(index_reg, 0x20300);
  786. WREG32(data_reg, 0x80188000);
  787. WREG32(index_reg, 0x20301);
  788. WREG32(data_reg, 0x8EE0BEC0);
  789. WREG32(index_reg, 0x20302);
  790. WREG32(data_reg, 0xBFB082A0);
  791. WREG32(index_reg, 0x20303);
  792. WREG32(data_reg, 0x80008000);
  793. WREG32(index_reg, 0x20400);
  794. WREG32(data_reg, 0x80188000);
  795. WREG32(index_reg, 0x20401);
  796. WREG32(data_reg, 0x8E00BEA0);
  797. WREG32(index_reg, 0x20402);
  798. WREG32(data_reg, 0xBF8883C0);
  799. WREG32(index_reg, 0x20403);
  800. WREG32(data_reg, 0x80008000);
  801. WREG32(index_reg, 0x20500);
  802. WREG32(data_reg, 0x80188000);
  803. WREG32(index_reg, 0x20501);
  804. WREG32(data_reg, 0x8D00BE90);
  805. WREG32(index_reg, 0x20502);
  806. WREG32(data_reg, 0xBF588500);
  807. WREG32(index_reg, 0x20503);
  808. WREG32(data_reg, 0x80008008);
  809. WREG32(index_reg, 0x20600);
  810. WREG32(data_reg, 0x80188000);
  811. WREG32(index_reg, 0x20601);
  812. WREG32(data_reg, 0x8BC0BE98);
  813. WREG32(index_reg, 0x20602);
  814. WREG32(data_reg, 0xBF308660);
  815. WREG32(index_reg, 0x20603);
  816. WREG32(data_reg, 0x80008008);
  817. WREG32(index_reg, 0x20700);
  818. WREG32(data_reg, 0x80108000);
  819. WREG32(index_reg, 0x20701);
  820. WREG32(data_reg, 0x8A80BEB0);
  821. WREG32(index_reg, 0x20702);
  822. WREG32(data_reg, 0xBF0087C0);
  823. WREG32(index_reg, 0x20703);
  824. WREG32(data_reg, 0x80008008);
  825. WREG32(index_reg, 0x20800);
  826. WREG32(data_reg, 0x80108000);
  827. WREG32(index_reg, 0x20801);
  828. WREG32(data_reg, 0x8920BED0);
  829. WREG32(index_reg, 0x20802);
  830. WREG32(data_reg, 0xBED08920);
  831. WREG32(index_reg, 0x20803);
  832. WREG32(data_reg, 0x80008010);
  833. WREG32(index_reg, 0x30000);
  834. WREG32(data_reg, 0x90008000);
  835. WREG32(index_reg, 0x30001);
  836. WREG32(data_reg, 0x80008000);
  837. WREG32(index_reg, 0x30100);
  838. WREG32(data_reg, 0x8FE0BF90);
  839. WREG32(index_reg, 0x30101);
  840. WREG32(data_reg, 0xBFF880A0);
  841. WREG32(index_reg, 0x30200);
  842. WREG32(data_reg, 0x8F60BF40);
  843. WREG32(index_reg, 0x30201);
  844. WREG32(data_reg, 0xBFE88180);
  845. WREG32(index_reg, 0x30300);
  846. WREG32(data_reg, 0x8EC0BF00);
  847. WREG32(index_reg, 0x30301);
  848. WREG32(data_reg, 0xBFC88280);
  849. WREG32(index_reg, 0x30400);
  850. WREG32(data_reg, 0x8DE0BEE0);
  851. WREG32(index_reg, 0x30401);
  852. WREG32(data_reg, 0xBFA083A0);
  853. WREG32(index_reg, 0x30500);
  854. WREG32(data_reg, 0x8CE0BED0);
  855. WREG32(index_reg, 0x30501);
  856. WREG32(data_reg, 0xBF7884E0);
  857. WREG32(index_reg, 0x30600);
  858. WREG32(data_reg, 0x8BA0BED8);
  859. WREG32(index_reg, 0x30601);
  860. WREG32(data_reg, 0xBF508640);
  861. WREG32(index_reg, 0x30700);
  862. WREG32(data_reg, 0x8A60BEE8);
  863. WREG32(index_reg, 0x30701);
  864. WREG32(data_reg, 0xBF2087A0);
  865. WREG32(index_reg, 0x30800);
  866. WREG32(data_reg, 0x8900BF00);
  867. WREG32(index_reg, 0x30801);
  868. WREG32(data_reg, 0xBF008900);
  869. }
  870. struct rv515_watermark {
  871. u32 lb_request_fifo_depth;
  872. fixed20_12 num_line_pair;
  873. fixed20_12 estimated_width;
  874. fixed20_12 worst_case_latency;
  875. fixed20_12 consumption_rate;
  876. fixed20_12 active_time;
  877. fixed20_12 dbpp;
  878. fixed20_12 priority_mark_max;
  879. fixed20_12 priority_mark;
  880. fixed20_12 sclk;
  881. };
  882. static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
  883. struct radeon_crtc *crtc,
  884. struct rv515_watermark *wm,
  885. bool low)
  886. {
  887. struct drm_display_mode *mode = &crtc->base.mode;
  888. fixed20_12 a, b, c;
  889. fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
  890. fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
  891. fixed20_12 sclk;
  892. u32 selected_sclk;
  893. if (!crtc->base.enabled) {
  894. /* FIXME: wouldn't it better to set priority mark to maximum */
  895. wm->lb_request_fifo_depth = 4;
  896. return;
  897. }
  898. /* rv6xx, rv7xx */
  899. if ((rdev->family >= CHIP_RV610) &&
  900. (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
  901. selected_sclk = radeon_dpm_get_sclk(rdev, low);
  902. else
  903. selected_sclk = rdev->pm.current_sclk;
  904. /* sclk in Mhz */
  905. a.full = dfixed_const(100);
  906. sclk.full = dfixed_const(selected_sclk);
  907. sclk.full = dfixed_div(sclk, a);
  908. if (crtc->vsc.full > dfixed_const(2))
  909. wm->num_line_pair.full = dfixed_const(2);
  910. else
  911. wm->num_line_pair.full = dfixed_const(1);
  912. b.full = dfixed_const(mode->crtc_hdisplay);
  913. c.full = dfixed_const(256);
  914. a.full = dfixed_div(b, c);
  915. request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
  916. request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
  917. if (a.full < dfixed_const(4)) {
  918. wm->lb_request_fifo_depth = 4;
  919. } else {
  920. wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
  921. }
  922. /* Determine consumption rate
  923. * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
  924. * vtaps = number of vertical taps,
  925. * vsc = vertical scaling ratio, defined as source/destination
  926. * hsc = horizontal scaling ration, defined as source/destination
  927. */
  928. a.full = dfixed_const(mode->clock);
  929. b.full = dfixed_const(1000);
  930. a.full = dfixed_div(a, b);
  931. pclk.full = dfixed_div(b, a);
  932. if (crtc->rmx_type != RMX_OFF) {
  933. b.full = dfixed_const(2);
  934. if (crtc->vsc.full > b.full)
  935. b.full = crtc->vsc.full;
  936. b.full = dfixed_mul(b, crtc->hsc);
  937. c.full = dfixed_const(2);
  938. b.full = dfixed_div(b, c);
  939. consumption_time.full = dfixed_div(pclk, b);
  940. } else {
  941. consumption_time.full = pclk.full;
  942. }
  943. a.full = dfixed_const(1);
  944. wm->consumption_rate.full = dfixed_div(a, consumption_time);
  945. /* Determine line time
  946. * LineTime = total time for one line of displayhtotal
  947. * LineTime = total number of horizontal pixels
  948. * pclk = pixel clock period(ns)
  949. */
  950. a.full = dfixed_const(crtc->base.mode.crtc_htotal);
  951. line_time.full = dfixed_mul(a, pclk);
  952. /* Determine active time
  953. * ActiveTime = time of active region of display within one line,
  954. * hactive = total number of horizontal active pixels
  955. * htotal = total number of horizontal pixels
  956. */
  957. a.full = dfixed_const(crtc->base.mode.crtc_htotal);
  958. b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
  959. wm->active_time.full = dfixed_mul(line_time, b);
  960. wm->active_time.full = dfixed_div(wm->active_time, a);
  961. /* Determine chunk time
  962. * ChunkTime = the time it takes the DCP to send one chunk of data
  963. * to the LB which consists of pipeline delay and inter chunk gap
  964. * sclk = system clock(Mhz)
  965. */
  966. a.full = dfixed_const(600 * 1000);
  967. chunk_time.full = dfixed_div(a, sclk);
  968. read_delay_latency.full = dfixed_const(1000);
  969. /* Determine the worst case latency
  970. * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
  971. * WorstCaseLatency = worst case time from urgent to when the MC starts
  972. * to return data
  973. * READ_DELAY_IDLE_MAX = constant of 1us
  974. * ChunkTime = time it takes the DCP to send one chunk of data to the LB
  975. * which consists of pipeline delay and inter chunk gap
  976. */
  977. if (dfixed_trunc(wm->num_line_pair) > 1) {
  978. a.full = dfixed_const(3);
  979. wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
  980. wm->worst_case_latency.full += read_delay_latency.full;
  981. } else {
  982. wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
  983. }
  984. /* Determine the tolerable latency
  985. * TolerableLatency = Any given request has only 1 line time
  986. * for the data to be returned
  987. * LBRequestFifoDepth = Number of chunk requests the LB can
  988. * put into the request FIFO for a display
  989. * LineTime = total time for one line of display
  990. * ChunkTime = the time it takes the DCP to send one chunk
  991. * of data to the LB which consists of
  992. * pipeline delay and inter chunk gap
  993. */
  994. if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
  995. tolerable_latency.full = line_time.full;
  996. } else {
  997. tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
  998. tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
  999. tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
  1000. tolerable_latency.full = line_time.full - tolerable_latency.full;
  1001. }
  1002. /* We assume worst case 32bits (4 bytes) */
  1003. wm->dbpp.full = dfixed_const(2 * 16);
  1004. /* Determine the maximum priority mark
  1005. * width = viewport width in pixels
  1006. */
  1007. a.full = dfixed_const(16);
  1008. wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
  1009. wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
  1010. wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
  1011. /* Determine estimated width */
  1012. estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
  1013. estimated_width.full = dfixed_div(estimated_width, consumption_time);
  1014. if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
  1015. wm->priority_mark.full = wm->priority_mark_max.full;
  1016. } else {
  1017. a.full = dfixed_const(16);
  1018. wm->priority_mark.full = dfixed_div(estimated_width, a);
  1019. wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
  1020. wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
  1021. }
  1022. }
  1023. static void rv515_compute_mode_priority(struct radeon_device *rdev,
  1024. struct rv515_watermark *wm0,
  1025. struct rv515_watermark *wm1,
  1026. struct drm_display_mode *mode0,
  1027. struct drm_display_mode *mode1,
  1028. u32 *d1mode_priority_a_cnt,
  1029. u32 *d2mode_priority_a_cnt)
  1030. {
  1031. fixed20_12 priority_mark02, priority_mark12, fill_rate;
  1032. fixed20_12 a, b;
  1033. *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
  1034. *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
  1035. if (mode0 && mode1) {
  1036. if (dfixed_trunc(wm0->dbpp) > 64)
  1037. a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
  1038. else
  1039. a.full = wm0->num_line_pair.full;
  1040. if (dfixed_trunc(wm1->dbpp) > 64)
  1041. b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
  1042. else
  1043. b.full = wm1->num_line_pair.full;
  1044. a.full += b.full;
  1045. fill_rate.full = dfixed_div(wm0->sclk, a);
  1046. if (wm0->consumption_rate.full > fill_rate.full) {
  1047. b.full = wm0->consumption_rate.full - fill_rate.full;
  1048. b.full = dfixed_mul(b, wm0->active_time);
  1049. a.full = dfixed_const(16);
  1050. b.full = dfixed_div(b, a);
  1051. a.full = dfixed_mul(wm0->worst_case_latency,
  1052. wm0->consumption_rate);
  1053. priority_mark02.full = a.full + b.full;
  1054. } else {
  1055. a.full = dfixed_mul(wm0->worst_case_latency,
  1056. wm0->consumption_rate);
  1057. b.full = dfixed_const(16 * 1000);
  1058. priority_mark02.full = dfixed_div(a, b);
  1059. }
  1060. if (wm1->consumption_rate.full > fill_rate.full) {
  1061. b.full = wm1->consumption_rate.full - fill_rate.full;
  1062. b.full = dfixed_mul(b, wm1->active_time);
  1063. a.full = dfixed_const(16);
  1064. b.full = dfixed_div(b, a);
  1065. a.full = dfixed_mul(wm1->worst_case_latency,
  1066. wm1->consumption_rate);
  1067. priority_mark12.full = a.full + b.full;
  1068. } else {
  1069. a.full = dfixed_mul(wm1->worst_case_latency,
  1070. wm1->consumption_rate);
  1071. b.full = dfixed_const(16 * 1000);
  1072. priority_mark12.full = dfixed_div(a, b);
  1073. }
  1074. if (wm0->priority_mark.full > priority_mark02.full)
  1075. priority_mark02.full = wm0->priority_mark.full;
  1076. if (dfixed_trunc(priority_mark02) < 0)
  1077. priority_mark02.full = 0;
  1078. if (wm0->priority_mark_max.full > priority_mark02.full)
  1079. priority_mark02.full = wm0->priority_mark_max.full;
  1080. if (wm1->priority_mark.full > priority_mark12.full)
  1081. priority_mark12.full = wm1->priority_mark.full;
  1082. if (dfixed_trunc(priority_mark12) < 0)
  1083. priority_mark12.full = 0;
  1084. if (wm1->priority_mark_max.full > priority_mark12.full)
  1085. priority_mark12.full = wm1->priority_mark_max.full;
  1086. *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
  1087. *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
  1088. if (rdev->disp_priority == 2) {
  1089. *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1090. *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1091. }
  1092. } else if (mode0) {
  1093. if (dfixed_trunc(wm0->dbpp) > 64)
  1094. a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
  1095. else
  1096. a.full = wm0->num_line_pair.full;
  1097. fill_rate.full = dfixed_div(wm0->sclk, a);
  1098. if (wm0->consumption_rate.full > fill_rate.full) {
  1099. b.full = wm0->consumption_rate.full - fill_rate.full;
  1100. b.full = dfixed_mul(b, wm0->active_time);
  1101. a.full = dfixed_const(16);
  1102. b.full = dfixed_div(b, a);
  1103. a.full = dfixed_mul(wm0->worst_case_latency,
  1104. wm0->consumption_rate);
  1105. priority_mark02.full = a.full + b.full;
  1106. } else {
  1107. a.full = dfixed_mul(wm0->worst_case_latency,
  1108. wm0->consumption_rate);
  1109. b.full = dfixed_const(16);
  1110. priority_mark02.full = dfixed_div(a, b);
  1111. }
  1112. if (wm0->priority_mark.full > priority_mark02.full)
  1113. priority_mark02.full = wm0->priority_mark.full;
  1114. if (dfixed_trunc(priority_mark02) < 0)
  1115. priority_mark02.full = 0;
  1116. if (wm0->priority_mark_max.full > priority_mark02.full)
  1117. priority_mark02.full = wm0->priority_mark_max.full;
  1118. *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
  1119. if (rdev->disp_priority == 2)
  1120. *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1121. } else if (mode1) {
  1122. if (dfixed_trunc(wm1->dbpp) > 64)
  1123. a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
  1124. else
  1125. a.full = wm1->num_line_pair.full;
  1126. fill_rate.full = dfixed_div(wm1->sclk, a);
  1127. if (wm1->consumption_rate.full > fill_rate.full) {
  1128. b.full = wm1->consumption_rate.full - fill_rate.full;
  1129. b.full = dfixed_mul(b, wm1->active_time);
  1130. a.full = dfixed_const(16);
  1131. b.full = dfixed_div(b, a);
  1132. a.full = dfixed_mul(wm1->worst_case_latency,
  1133. wm1->consumption_rate);
  1134. priority_mark12.full = a.full + b.full;
  1135. } else {
  1136. a.full = dfixed_mul(wm1->worst_case_latency,
  1137. wm1->consumption_rate);
  1138. b.full = dfixed_const(16 * 1000);
  1139. priority_mark12.full = dfixed_div(a, b);
  1140. }
  1141. if (wm1->priority_mark.full > priority_mark12.full)
  1142. priority_mark12.full = wm1->priority_mark.full;
  1143. if (dfixed_trunc(priority_mark12) < 0)
  1144. priority_mark12.full = 0;
  1145. if (wm1->priority_mark_max.full > priority_mark12.full)
  1146. priority_mark12.full = wm1->priority_mark_max.full;
  1147. *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
  1148. if (rdev->disp_priority == 2)
  1149. *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1150. }
  1151. }
  1152. void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
  1153. {
  1154. struct drm_display_mode *mode0 = NULL;
  1155. struct drm_display_mode *mode1 = NULL;
  1156. struct rv515_watermark wm0_high, wm0_low;
  1157. struct rv515_watermark wm1_high, wm1_low;
  1158. u32 tmp;
  1159. u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
  1160. u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
  1161. if (rdev->mode_info.crtcs[0]->base.enabled)
  1162. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  1163. if (rdev->mode_info.crtcs[1]->base.enabled)
  1164. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  1165. rs690_line_buffer_adjust(rdev, mode0, mode1);
  1166. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
  1167. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
  1168. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
  1169. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
  1170. tmp = wm0_high.lb_request_fifo_depth;
  1171. tmp |= wm1_high.lb_request_fifo_depth << 16;
  1172. WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
  1173. rv515_compute_mode_priority(rdev,
  1174. &wm0_high, &wm1_high,
  1175. mode0, mode1,
  1176. &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
  1177. rv515_compute_mode_priority(rdev,
  1178. &wm0_low, &wm1_low,
  1179. mode0, mode1,
  1180. &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
  1181. WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
  1182. WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
  1183. WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
  1184. WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
  1185. }
  1186. void rv515_bandwidth_update(struct radeon_device *rdev)
  1187. {
  1188. uint32_t tmp;
  1189. struct drm_display_mode *mode0 = NULL;
  1190. struct drm_display_mode *mode1 = NULL;
  1191. radeon_update_display_priority(rdev);
  1192. if (rdev->mode_info.crtcs[0]->base.enabled)
  1193. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  1194. if (rdev->mode_info.crtcs[1]->base.enabled)
  1195. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  1196. /*
  1197. * Set display0/1 priority up in the memory controller for
  1198. * modes if the user specifies HIGH for displaypriority
  1199. * option.
  1200. */
  1201. if ((rdev->disp_priority == 2) &&
  1202. (rdev->family == CHIP_RV515)) {
  1203. tmp = RREG32_MC(MC_MISC_LAT_TIMER);
  1204. tmp &= ~MC_DISP1R_INIT_LAT_MASK;
  1205. tmp &= ~MC_DISP0R_INIT_LAT_MASK;
  1206. if (mode1)
  1207. tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
  1208. if (mode0)
  1209. tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
  1210. WREG32_MC(MC_MISC_LAT_TIMER, tmp);
  1211. }
  1212. rv515_bandwidth_avivo_update(rdev);
  1213. }