rs600.c 31 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29. *
  30. * This file gather function specific to RS600 which is the IGP of
  31. * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32. * is the X1250/X1270 supporting AMD CPU). The display engine are
  33. * the avivo one, bios is an atombios, 3D block are the one of the
  34. * R4XX family. The GART is different from the RS400 one and is very
  35. * close to the one of the R600 family (R600 likely being an evolution
  36. * of the RS600 GART block).
  37. */
  38. #include <drm/drmP.h>
  39. #include "radeon.h"
  40. #include "radeon_asic.h"
  41. #include "atom.h"
  42. #include "rs600d.h"
  43. #include "rs600_reg_safe.h"
  44. static void rs600_gpu_init(struct radeon_device *rdev);
  45. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  46. static const u32 crtc_offsets[2] =
  47. {
  48. 0,
  49. AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  50. };
  51. static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
  52. {
  53. if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  54. return true;
  55. else
  56. return false;
  57. }
  58. static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
  59. {
  60. u32 pos1, pos2;
  61. pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  62. pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  63. if (pos1 != pos2)
  64. return true;
  65. else
  66. return false;
  67. }
  68. /**
  69. * avivo_wait_for_vblank - vblank wait asic callback.
  70. *
  71. * @rdev: radeon_device pointer
  72. * @crtc: crtc to wait for vblank on
  73. *
  74. * Wait for vblank on the requested crtc (r5xx-r7xx).
  75. */
  76. void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  77. {
  78. unsigned i = 0;
  79. if (crtc >= rdev->num_crtc)
  80. return;
  81. if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
  82. return;
  83. /* depending on when we hit vblank, we may be close to active; if so,
  84. * wait for another frame.
  85. */
  86. while (avivo_is_in_vblank(rdev, crtc)) {
  87. if (i++ % 100 == 0) {
  88. if (!avivo_is_counter_moving(rdev, crtc))
  89. break;
  90. }
  91. }
  92. while (!avivo_is_in_vblank(rdev, crtc)) {
  93. if (i++ % 100 == 0) {
  94. if (!avivo_is_counter_moving(rdev, crtc))
  95. break;
  96. }
  97. }
  98. }
  99. void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
  100. {
  101. /* enable the pflip int */
  102. radeon_irq_kms_pflip_irq_get(rdev, crtc);
  103. }
  104. void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
  105. {
  106. /* disable the pflip int */
  107. radeon_irq_kms_pflip_irq_put(rdev, crtc);
  108. }
  109. u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  110. {
  111. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  112. u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  113. int i;
  114. /* Lock the graphics update lock */
  115. tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  116. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  117. /* update the scanout addresses */
  118. WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  119. (u32)crtc_base);
  120. WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  121. (u32)crtc_base);
  122. /* Wait for update_pending to go high. */
  123. for (i = 0; i < rdev->usec_timeout; i++) {
  124. if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
  125. break;
  126. udelay(1);
  127. }
  128. DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  129. /* Unlock the lock, so double-buffering can take place inside vblank */
  130. tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  131. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  132. /* Return current update_pending status: */
  133. return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  134. }
  135. void rs600_pm_misc(struct radeon_device *rdev)
  136. {
  137. int requested_index = rdev->pm.requested_power_state_index;
  138. struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
  139. struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
  140. u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
  141. u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
  142. if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
  143. if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
  144. tmp = RREG32(voltage->gpio.reg);
  145. if (voltage->active_high)
  146. tmp |= voltage->gpio.mask;
  147. else
  148. tmp &= ~(voltage->gpio.mask);
  149. WREG32(voltage->gpio.reg, tmp);
  150. if (voltage->delay)
  151. udelay(voltage->delay);
  152. } else {
  153. tmp = RREG32(voltage->gpio.reg);
  154. if (voltage->active_high)
  155. tmp &= ~voltage->gpio.mask;
  156. else
  157. tmp |= voltage->gpio.mask;
  158. WREG32(voltage->gpio.reg, tmp);
  159. if (voltage->delay)
  160. udelay(voltage->delay);
  161. }
  162. } else if (voltage->type == VOLTAGE_VDDC)
  163. radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
  164. dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
  165. dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
  166. dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
  167. if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
  168. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
  169. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
  170. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
  171. } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
  172. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
  173. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
  174. }
  175. } else {
  176. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
  177. dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
  178. }
  179. WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
  180. dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
  181. if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
  182. dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
  183. if (voltage->delay) {
  184. dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
  185. dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
  186. } else
  187. dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
  188. } else
  189. dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
  190. WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
  191. hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
  192. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
  193. hdp_dyn_cntl &= ~HDP_FORCEON;
  194. else
  195. hdp_dyn_cntl |= HDP_FORCEON;
  196. WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
  197. #if 0
  198. /* mc_host_dyn seems to cause hangs from time to time */
  199. mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
  200. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
  201. mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
  202. else
  203. mc_host_dyn_cntl |= MC_HOST_FORCEON;
  204. WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
  205. #endif
  206. dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
  207. if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
  208. dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
  209. else
  210. dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
  211. WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
  212. /* set pcie lanes */
  213. if ((rdev->flags & RADEON_IS_PCIE) &&
  214. !(rdev->flags & RADEON_IS_IGP) &&
  215. rdev->asic->pm.set_pcie_lanes &&
  216. (ps->pcie_lanes !=
  217. rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
  218. radeon_set_pcie_lanes(rdev,
  219. ps->pcie_lanes);
  220. DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
  221. }
  222. }
  223. void rs600_pm_prepare(struct radeon_device *rdev)
  224. {
  225. struct drm_device *ddev = rdev->ddev;
  226. struct drm_crtc *crtc;
  227. struct radeon_crtc *radeon_crtc;
  228. u32 tmp;
  229. /* disable any active CRTCs */
  230. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  231. radeon_crtc = to_radeon_crtc(crtc);
  232. if (radeon_crtc->enabled) {
  233. tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
  234. tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  235. WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  236. }
  237. }
  238. }
  239. void rs600_pm_finish(struct radeon_device *rdev)
  240. {
  241. struct drm_device *ddev = rdev->ddev;
  242. struct drm_crtc *crtc;
  243. struct radeon_crtc *radeon_crtc;
  244. u32 tmp;
  245. /* enable any active CRTCs */
  246. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  247. radeon_crtc = to_radeon_crtc(crtc);
  248. if (radeon_crtc->enabled) {
  249. tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
  250. tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  251. WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  252. }
  253. }
  254. }
  255. /* hpd for digital panel detect/disconnect */
  256. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  257. {
  258. u32 tmp;
  259. bool connected = false;
  260. switch (hpd) {
  261. case RADEON_HPD_1:
  262. tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  263. if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  264. connected = true;
  265. break;
  266. case RADEON_HPD_2:
  267. tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  268. if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  269. connected = true;
  270. break;
  271. default:
  272. break;
  273. }
  274. return connected;
  275. }
  276. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  277. enum radeon_hpd_id hpd)
  278. {
  279. u32 tmp;
  280. bool connected = rs600_hpd_sense(rdev, hpd);
  281. switch (hpd) {
  282. case RADEON_HPD_1:
  283. tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  284. if (connected)
  285. tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  286. else
  287. tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  288. WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  289. break;
  290. case RADEON_HPD_2:
  291. tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  292. if (connected)
  293. tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  294. else
  295. tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  296. WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  297. break;
  298. default:
  299. break;
  300. }
  301. }
  302. void rs600_hpd_init(struct radeon_device *rdev)
  303. {
  304. struct drm_device *dev = rdev->ddev;
  305. struct drm_connector *connector;
  306. unsigned enable = 0;
  307. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  308. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  309. switch (radeon_connector->hpd.hpd) {
  310. case RADEON_HPD_1:
  311. WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  312. S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
  313. break;
  314. case RADEON_HPD_2:
  315. WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  316. S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
  317. break;
  318. default:
  319. break;
  320. }
  321. enable |= 1 << radeon_connector->hpd.hpd;
  322. radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
  323. }
  324. radeon_irq_kms_enable_hpd(rdev, enable);
  325. }
  326. void rs600_hpd_fini(struct radeon_device *rdev)
  327. {
  328. struct drm_device *dev = rdev->ddev;
  329. struct drm_connector *connector;
  330. unsigned disable = 0;
  331. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  332. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  333. switch (radeon_connector->hpd.hpd) {
  334. case RADEON_HPD_1:
  335. WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  336. S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
  337. break;
  338. case RADEON_HPD_2:
  339. WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  340. S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
  341. break;
  342. default:
  343. break;
  344. }
  345. disable |= 1 << radeon_connector->hpd.hpd;
  346. }
  347. radeon_irq_kms_disable_hpd(rdev, disable);
  348. }
  349. int rs600_asic_reset(struct radeon_device *rdev)
  350. {
  351. struct rv515_mc_save save;
  352. u32 status, tmp;
  353. int ret = 0;
  354. status = RREG32(R_000E40_RBBM_STATUS);
  355. if (!G_000E40_GUI_ACTIVE(status)) {
  356. return 0;
  357. }
  358. /* Stops all mc clients */
  359. rv515_mc_stop(rdev, &save);
  360. status = RREG32(R_000E40_RBBM_STATUS);
  361. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  362. /* stop CP */
  363. WREG32(RADEON_CP_CSQ_CNTL, 0);
  364. tmp = RREG32(RADEON_CP_RB_CNTL);
  365. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  366. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  367. WREG32(RADEON_CP_RB_WPTR, 0);
  368. WREG32(RADEON_CP_RB_CNTL, tmp);
  369. pci_save_state(rdev->pdev);
  370. /* disable bus mastering */
  371. pci_clear_master(rdev->pdev);
  372. mdelay(1);
  373. /* reset GA+VAP */
  374. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
  375. S_0000F0_SOFT_RESET_GA(1));
  376. RREG32(R_0000F0_RBBM_SOFT_RESET);
  377. mdelay(500);
  378. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  379. mdelay(1);
  380. status = RREG32(R_000E40_RBBM_STATUS);
  381. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  382. /* reset CP */
  383. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
  384. RREG32(R_0000F0_RBBM_SOFT_RESET);
  385. mdelay(500);
  386. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  387. mdelay(1);
  388. status = RREG32(R_000E40_RBBM_STATUS);
  389. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  390. /* reset MC */
  391. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
  392. RREG32(R_0000F0_RBBM_SOFT_RESET);
  393. mdelay(500);
  394. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  395. mdelay(1);
  396. status = RREG32(R_000E40_RBBM_STATUS);
  397. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  398. /* restore PCI & busmastering */
  399. pci_restore_state(rdev->pdev);
  400. /* Check if GPU is idle */
  401. if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
  402. dev_err(rdev->dev, "failed to reset GPU\n");
  403. ret = -1;
  404. } else
  405. dev_info(rdev->dev, "GPU reset succeed\n");
  406. rv515_mc_resume(rdev, &save);
  407. return ret;
  408. }
  409. /*
  410. * GART.
  411. */
  412. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  413. {
  414. uint32_t tmp;
  415. tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  416. tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  417. WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  418. tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  419. tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
  420. WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  421. tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  422. tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  423. WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  424. tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  425. }
  426. static int rs600_gart_init(struct radeon_device *rdev)
  427. {
  428. int r;
  429. if (rdev->gart.robj) {
  430. WARN(1, "RS600 GART already initialized\n");
  431. return 0;
  432. }
  433. /* Initialize common gart structure */
  434. r = radeon_gart_init(rdev);
  435. if (r) {
  436. return r;
  437. }
  438. rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  439. return radeon_gart_table_vram_alloc(rdev);
  440. }
  441. static int rs600_gart_enable(struct radeon_device *rdev)
  442. {
  443. u32 tmp;
  444. int r, i;
  445. if (rdev->gart.robj == NULL) {
  446. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  447. return -EINVAL;
  448. }
  449. r = radeon_gart_table_vram_pin(rdev);
  450. if (r)
  451. return r;
  452. radeon_gart_restore(rdev);
  453. /* Enable bus master */
  454. tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
  455. WREG32(RADEON_BUS_CNTL, tmp);
  456. /* FIXME: setup default page */
  457. WREG32_MC(R_000100_MC_PT0_CNTL,
  458. (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  459. S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  460. for (i = 0; i < 19; i++) {
  461. WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  462. S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  463. S_00016C_SYSTEM_ACCESS_MODE_MASK(
  464. V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
  465. S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  466. V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
  467. S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
  468. S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  469. S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
  470. }
  471. /* enable first context */
  472. WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  473. S_000102_ENABLE_PAGE_TABLE(1) |
  474. S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  475. /* disable all other contexts */
  476. for (i = 1; i < 8; i++)
  477. WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  478. /* setup the page table */
  479. WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  480. rdev->gart.table_addr);
  481. WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  482. WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  483. WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  484. /* System context maps to VRAM space */
  485. WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
  486. WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
  487. /* enable page tables */
  488. tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  489. WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  490. tmp = RREG32_MC(R_000009_MC_CNTL1);
  491. WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  492. rs600_gart_tlb_flush(rdev);
  493. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  494. (unsigned)(rdev->mc.gtt_size >> 20),
  495. (unsigned long long)rdev->gart.table_addr);
  496. rdev->gart.ready = true;
  497. return 0;
  498. }
  499. static void rs600_gart_disable(struct radeon_device *rdev)
  500. {
  501. u32 tmp;
  502. /* FIXME: disable out of gart access */
  503. WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  504. tmp = RREG32_MC(R_000009_MC_CNTL1);
  505. WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  506. radeon_gart_table_vram_unpin(rdev);
  507. }
  508. static void rs600_gart_fini(struct radeon_device *rdev)
  509. {
  510. radeon_gart_fini(rdev);
  511. rs600_gart_disable(rdev);
  512. radeon_gart_table_vram_free(rdev);
  513. }
  514. #define R600_PTE_VALID (1 << 0)
  515. #define R600_PTE_SYSTEM (1 << 1)
  516. #define R600_PTE_SNOOPED (1 << 2)
  517. #define R600_PTE_READABLE (1 << 5)
  518. #define R600_PTE_WRITEABLE (1 << 6)
  519. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  520. {
  521. void __iomem *ptr = (void *)rdev->gart.ptr;
  522. if (i < 0 || i > rdev->gart.num_gpu_pages) {
  523. return -EINVAL;
  524. }
  525. addr = addr & 0xFFFFFFFFFFFFF000ULL;
  526. addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  527. addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  528. writeq(addr, ptr + (i * 8));
  529. return 0;
  530. }
  531. int rs600_irq_set(struct radeon_device *rdev)
  532. {
  533. uint32_t tmp = 0;
  534. uint32_t mode_int = 0;
  535. u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
  536. ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  537. u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
  538. ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  539. u32 hdmi0;
  540. if (ASIC_IS_DCE2(rdev))
  541. hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
  542. ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
  543. else
  544. hdmi0 = 0;
  545. if (!rdev->irq.installed) {
  546. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  547. WREG32(R_000040_GEN_INT_CNTL, 0);
  548. return -EINVAL;
  549. }
  550. if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
  551. tmp |= S_000040_SW_INT_EN(1);
  552. }
  553. if (rdev->irq.crtc_vblank_int[0] ||
  554. atomic_read(&rdev->irq.pflip[0])) {
  555. mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
  556. }
  557. if (rdev->irq.crtc_vblank_int[1] ||
  558. atomic_read(&rdev->irq.pflip[1])) {
  559. mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
  560. }
  561. if (rdev->irq.hpd[0]) {
  562. hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  563. }
  564. if (rdev->irq.hpd[1]) {
  565. hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  566. }
  567. if (rdev->irq.afmt[0]) {
  568. hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
  569. }
  570. WREG32(R_000040_GEN_INT_CNTL, tmp);
  571. WREG32(R_006540_DxMODE_INT_MASK, mode_int);
  572. WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  573. WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  574. if (ASIC_IS_DCE2(rdev))
  575. WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
  576. return 0;
  577. }
  578. static inline u32 rs600_irq_ack(struct radeon_device *rdev)
  579. {
  580. uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  581. uint32_t irq_mask = S_000044_SW_INT(1);
  582. u32 tmp;
  583. if (G_000044_DISPLAY_INT_STAT(irqs)) {
  584. rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  585. if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  586. WREG32(R_006534_D1MODE_VBLANK_STATUS,
  587. S_006534_D1MODE_VBLANK_ACK(1));
  588. }
  589. if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  590. WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  591. S_006D34_D2MODE_VBLANK_ACK(1));
  592. }
  593. if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  594. tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  595. tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
  596. WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  597. }
  598. if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  599. tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  600. tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
  601. WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  602. }
  603. } else {
  604. rdev->irq.stat_regs.r500.disp_int = 0;
  605. }
  606. if (ASIC_IS_DCE2(rdev)) {
  607. rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
  608. S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
  609. if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
  610. tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
  611. tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
  612. WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
  613. }
  614. } else
  615. rdev->irq.stat_regs.r500.hdmi0_status = 0;
  616. if (irqs) {
  617. WREG32(R_000044_GEN_INT_STATUS, irqs);
  618. }
  619. return irqs & irq_mask;
  620. }
  621. void rs600_irq_disable(struct radeon_device *rdev)
  622. {
  623. u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
  624. ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
  625. WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
  626. WREG32(R_000040_GEN_INT_CNTL, 0);
  627. WREG32(R_006540_DxMODE_INT_MASK, 0);
  628. /* Wait and acknowledge irq */
  629. mdelay(1);
  630. rs600_irq_ack(rdev);
  631. }
  632. int rs600_irq_process(struct radeon_device *rdev)
  633. {
  634. u32 status, msi_rearm;
  635. bool queue_hotplug = false;
  636. bool queue_hdmi = false;
  637. status = rs600_irq_ack(rdev);
  638. if (!status &&
  639. !rdev->irq.stat_regs.r500.disp_int &&
  640. !rdev->irq.stat_regs.r500.hdmi0_status) {
  641. return IRQ_NONE;
  642. }
  643. while (status ||
  644. rdev->irq.stat_regs.r500.disp_int ||
  645. rdev->irq.stat_regs.r500.hdmi0_status) {
  646. /* SW interrupt */
  647. if (G_000044_SW_INT(status)) {
  648. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  649. }
  650. /* Vertical blank interrupts */
  651. if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  652. if (rdev->irq.crtc_vblank_int[0]) {
  653. drm_handle_vblank(rdev->ddev, 0);
  654. rdev->pm.vblank_sync = true;
  655. wake_up(&rdev->irq.vblank_queue);
  656. }
  657. if (atomic_read(&rdev->irq.pflip[0]))
  658. radeon_crtc_handle_flip(rdev, 0);
  659. }
  660. if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  661. if (rdev->irq.crtc_vblank_int[1]) {
  662. drm_handle_vblank(rdev->ddev, 1);
  663. rdev->pm.vblank_sync = true;
  664. wake_up(&rdev->irq.vblank_queue);
  665. }
  666. if (atomic_read(&rdev->irq.pflip[1]))
  667. radeon_crtc_handle_flip(rdev, 1);
  668. }
  669. if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  670. queue_hotplug = true;
  671. DRM_DEBUG("HPD1\n");
  672. }
  673. if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  674. queue_hotplug = true;
  675. DRM_DEBUG("HPD2\n");
  676. }
  677. if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
  678. queue_hdmi = true;
  679. DRM_DEBUG("HDMI0\n");
  680. }
  681. status = rs600_irq_ack(rdev);
  682. }
  683. if (queue_hotplug)
  684. schedule_work(&rdev->hotplug_work);
  685. if (queue_hdmi)
  686. schedule_work(&rdev->audio_work);
  687. if (rdev->msi_enabled) {
  688. switch (rdev->family) {
  689. case CHIP_RS600:
  690. case CHIP_RS690:
  691. case CHIP_RS740:
  692. msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
  693. WREG32(RADEON_BUS_CNTL, msi_rearm);
  694. WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
  695. break;
  696. default:
  697. WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
  698. break;
  699. }
  700. }
  701. return IRQ_HANDLED;
  702. }
  703. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  704. {
  705. if (crtc == 0)
  706. return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  707. else
  708. return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  709. }
  710. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  711. {
  712. unsigned i;
  713. for (i = 0; i < rdev->usec_timeout; i++) {
  714. if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  715. return 0;
  716. udelay(1);
  717. }
  718. return -1;
  719. }
  720. static void rs600_gpu_init(struct radeon_device *rdev)
  721. {
  722. r420_pipes_init(rdev);
  723. /* Wait for mc idle */
  724. if (rs600_mc_wait_for_idle(rdev))
  725. dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  726. }
  727. static void rs600_mc_init(struct radeon_device *rdev)
  728. {
  729. u64 base;
  730. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  731. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  732. rdev->mc.vram_is_ddr = true;
  733. rdev->mc.vram_width = 128;
  734. rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  735. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  736. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  737. rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  738. base = RREG32_MC(R_000004_MC_FB_LOCATION);
  739. base = G_000004_MC_FB_START(base) << 16;
  740. radeon_vram_location(rdev, &rdev->mc, base);
  741. rdev->mc.gtt_base_align = 0;
  742. radeon_gtt_location(rdev, &rdev->mc);
  743. radeon_update_bandwidth_info(rdev);
  744. }
  745. void rs600_bandwidth_update(struct radeon_device *rdev)
  746. {
  747. struct drm_display_mode *mode0 = NULL;
  748. struct drm_display_mode *mode1 = NULL;
  749. u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
  750. /* FIXME: implement full support */
  751. radeon_update_display_priority(rdev);
  752. if (rdev->mode_info.crtcs[0]->base.enabled)
  753. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  754. if (rdev->mode_info.crtcs[1]->base.enabled)
  755. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  756. rs690_line_buffer_adjust(rdev, mode0, mode1);
  757. if (rdev->disp_priority == 2) {
  758. d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
  759. d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
  760. d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
  761. d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
  762. WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
  763. WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
  764. WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
  765. WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
  766. }
  767. }
  768. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  769. {
  770. unsigned long flags;
  771. u32 r;
  772. spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  773. WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  774. S_000070_MC_IND_CITF_ARB0(1));
  775. r = RREG32(R_000074_MC_IND_DATA);
  776. spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  777. return r;
  778. }
  779. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  780. {
  781. unsigned long flags;
  782. spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  783. WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  784. S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  785. WREG32(R_000074_MC_IND_DATA, v);
  786. spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  787. }
  788. static void rs600_debugfs(struct radeon_device *rdev)
  789. {
  790. if (r100_debugfs_rbbm_init(rdev))
  791. DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  792. }
  793. void rs600_set_safe_registers(struct radeon_device *rdev)
  794. {
  795. rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  796. rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  797. }
  798. static void rs600_mc_program(struct radeon_device *rdev)
  799. {
  800. struct rv515_mc_save save;
  801. /* Stops all mc clients */
  802. rv515_mc_stop(rdev, &save);
  803. /* Wait for mc idle */
  804. if (rs600_mc_wait_for_idle(rdev))
  805. dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  806. /* FIXME: What does AGP means for such chipset ? */
  807. WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  808. WREG32_MC(R_000006_AGP_BASE, 0);
  809. WREG32_MC(R_000007_AGP_BASE_2, 0);
  810. /* Program MC */
  811. WREG32_MC(R_000004_MC_FB_LOCATION,
  812. S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  813. S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  814. WREG32(R_000134_HDP_FB_LOCATION,
  815. S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  816. rv515_mc_resume(rdev, &save);
  817. }
  818. static int rs600_startup(struct radeon_device *rdev)
  819. {
  820. int r;
  821. rs600_mc_program(rdev);
  822. /* Resume clock */
  823. rv515_clock_startup(rdev);
  824. /* Initialize GPU configuration (# pipes, ...) */
  825. rs600_gpu_init(rdev);
  826. /* Initialize GART (initialize after TTM so we can allocate
  827. * memory through TTM but finalize after TTM) */
  828. r = rs600_gart_enable(rdev);
  829. if (r)
  830. return r;
  831. /* allocate wb buffer */
  832. r = radeon_wb_init(rdev);
  833. if (r)
  834. return r;
  835. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  836. if (r) {
  837. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  838. return r;
  839. }
  840. /* Enable IRQ */
  841. if (!rdev->irq.installed) {
  842. r = radeon_irq_kms_init(rdev);
  843. if (r)
  844. return r;
  845. }
  846. rs600_irq_set(rdev);
  847. rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  848. /* 1M ring buffer */
  849. r = r100_cp_init(rdev, 1024 * 1024);
  850. if (r) {
  851. dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  852. return r;
  853. }
  854. r = radeon_ib_pool_init(rdev);
  855. if (r) {
  856. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  857. return r;
  858. }
  859. r = r600_audio_init(rdev);
  860. if (r) {
  861. dev_err(rdev->dev, "failed initializing audio\n");
  862. return r;
  863. }
  864. return 0;
  865. }
  866. int rs600_resume(struct radeon_device *rdev)
  867. {
  868. int r;
  869. /* Make sur GART are not working */
  870. rs600_gart_disable(rdev);
  871. /* Resume clock before doing reset */
  872. rv515_clock_startup(rdev);
  873. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  874. if (radeon_asic_reset(rdev)) {
  875. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  876. RREG32(R_000E40_RBBM_STATUS),
  877. RREG32(R_0007C0_CP_STAT));
  878. }
  879. /* post */
  880. atom_asic_init(rdev->mode_info.atom_context);
  881. /* Resume clock after posting */
  882. rv515_clock_startup(rdev);
  883. /* Initialize surface registers */
  884. radeon_surface_init(rdev);
  885. rdev->accel_working = true;
  886. r = rs600_startup(rdev);
  887. if (r) {
  888. rdev->accel_working = false;
  889. }
  890. return r;
  891. }
  892. int rs600_suspend(struct radeon_device *rdev)
  893. {
  894. r600_audio_fini(rdev);
  895. r100_cp_disable(rdev);
  896. radeon_wb_disable(rdev);
  897. rs600_irq_disable(rdev);
  898. rs600_gart_disable(rdev);
  899. return 0;
  900. }
  901. void rs600_fini(struct radeon_device *rdev)
  902. {
  903. r600_audio_fini(rdev);
  904. r100_cp_fini(rdev);
  905. radeon_wb_fini(rdev);
  906. radeon_ib_pool_fini(rdev);
  907. radeon_gem_fini(rdev);
  908. rs600_gart_fini(rdev);
  909. radeon_irq_kms_fini(rdev);
  910. radeon_fence_driver_fini(rdev);
  911. radeon_bo_fini(rdev);
  912. radeon_atombios_fini(rdev);
  913. kfree(rdev->bios);
  914. rdev->bios = NULL;
  915. }
  916. int rs600_init(struct radeon_device *rdev)
  917. {
  918. int r;
  919. /* Disable VGA */
  920. rv515_vga_render_disable(rdev);
  921. /* Initialize scratch registers */
  922. radeon_scratch_init(rdev);
  923. /* Initialize surface registers */
  924. radeon_surface_init(rdev);
  925. /* restore some register to sane defaults */
  926. r100_restore_sanity(rdev);
  927. /* BIOS */
  928. if (!radeon_get_bios(rdev)) {
  929. if (ASIC_IS_AVIVO(rdev))
  930. return -EINVAL;
  931. }
  932. if (rdev->is_atom_bios) {
  933. r = radeon_atombios_init(rdev);
  934. if (r)
  935. return r;
  936. } else {
  937. dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  938. return -EINVAL;
  939. }
  940. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  941. if (radeon_asic_reset(rdev)) {
  942. dev_warn(rdev->dev,
  943. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  944. RREG32(R_000E40_RBBM_STATUS),
  945. RREG32(R_0007C0_CP_STAT));
  946. }
  947. /* check if cards are posted or not */
  948. if (radeon_boot_test_post_card(rdev) == false)
  949. return -EINVAL;
  950. /* Initialize clocks */
  951. radeon_get_clock_info(rdev->ddev);
  952. /* initialize memory controller */
  953. rs600_mc_init(rdev);
  954. rs600_debugfs(rdev);
  955. /* Fence driver */
  956. r = radeon_fence_driver_init(rdev);
  957. if (r)
  958. return r;
  959. /* Memory manager */
  960. r = radeon_bo_init(rdev);
  961. if (r)
  962. return r;
  963. r = rs600_gart_init(rdev);
  964. if (r)
  965. return r;
  966. rs600_set_safe_registers(rdev);
  967. rdev->accel_working = true;
  968. r = rs600_startup(rdev);
  969. if (r) {
  970. /* Somethings want wront with the accel init stop accel */
  971. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  972. r100_cp_fini(rdev);
  973. radeon_wb_fini(rdev);
  974. radeon_ib_pool_fini(rdev);
  975. rs600_gart_fini(rdev);
  976. radeon_irq_kms_fini(rdev);
  977. rdev->accel_working = false;
  978. }
  979. return 0;
  980. }