radeon_ring.c 25 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. * Christian König
  28. */
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "atom.h"
  36. /*
  37. * IB
  38. * IBs (Indirect Buffers) and areas of GPU accessible memory where
  39. * commands are stored. You can put a pointer to the IB in the
  40. * command ring and the hw will fetch the commands from the IB
  41. * and execute them. Generally userspace acceleration drivers
  42. * produce command buffers which are send to the kernel and
  43. * put in IBs for execution by the requested ring.
  44. */
  45. static int radeon_debugfs_sa_init(struct radeon_device *rdev);
  46. /**
  47. * radeon_ib_get - request an IB (Indirect Buffer)
  48. *
  49. * @rdev: radeon_device pointer
  50. * @ring: ring index the IB is associated with
  51. * @ib: IB object returned
  52. * @size: requested IB size
  53. *
  54. * Request an IB (all asics). IBs are allocated using the
  55. * suballocator.
  56. * Returns 0 on success, error on failure.
  57. */
  58. int radeon_ib_get(struct radeon_device *rdev, int ring,
  59. struct radeon_ib *ib, struct radeon_vm *vm,
  60. unsigned size)
  61. {
  62. int i, r;
  63. r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
  64. if (r) {
  65. dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
  66. return r;
  67. }
  68. r = radeon_semaphore_create(rdev, &ib->semaphore);
  69. if (r) {
  70. return r;
  71. }
  72. ib->ring = ring;
  73. ib->fence = NULL;
  74. ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
  75. ib->vm = vm;
  76. if (vm) {
  77. /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
  78. * space and soffset is the offset inside the pool bo
  79. */
  80. ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
  81. } else {
  82. ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
  83. }
  84. ib->is_const_ib = false;
  85. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  86. ib->sync_to[i] = NULL;
  87. return 0;
  88. }
  89. /**
  90. * radeon_ib_free - free an IB (Indirect Buffer)
  91. *
  92. * @rdev: radeon_device pointer
  93. * @ib: IB object to free
  94. *
  95. * Free an IB (all asics).
  96. */
  97. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
  98. {
  99. radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
  100. radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
  101. radeon_fence_unref(&ib->fence);
  102. }
  103. /**
  104. * radeon_ib_sync_to - sync to fence before executing the IB
  105. *
  106. * @ib: IB object to add fence to
  107. * @fence: fence to sync to
  108. *
  109. * Sync to the fence before executing the IB
  110. */
  111. void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
  112. {
  113. struct radeon_fence *other;
  114. if (!fence)
  115. return;
  116. other = ib->sync_to[fence->ring];
  117. ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
  118. }
  119. /**
  120. * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  121. *
  122. * @rdev: radeon_device pointer
  123. * @ib: IB object to schedule
  124. * @const_ib: Const IB to schedule (SI only)
  125. *
  126. * Schedule an IB on the associated ring (all asics).
  127. * Returns 0 on success, error on failure.
  128. *
  129. * On SI, there are two parallel engines fed from the primary ring,
  130. * the CE (Constant Engine) and the DE (Drawing Engine). Since
  131. * resource descriptors have moved to memory, the CE allows you to
  132. * prime the caches while the DE is updating register state so that
  133. * the resource descriptors will be already in cache when the draw is
  134. * processed. To accomplish this, the userspace driver submits two
  135. * IBs, one for the CE and one for the DE. If there is a CE IB (called
  136. * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
  137. * to SI there was just a DE IB.
  138. */
  139. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
  140. struct radeon_ib *const_ib)
  141. {
  142. struct radeon_ring *ring = &rdev->ring[ib->ring];
  143. bool need_sync = false;
  144. int i, r = 0;
  145. if (!ib->length_dw || !ring->ready) {
  146. /* TODO: Nothings in the ib we should report. */
  147. dev_err(rdev->dev, "couldn't schedule ib\n");
  148. return -EINVAL;
  149. }
  150. /* 64 dwords should be enough for fence too */
  151. r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
  152. if (r) {
  153. dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
  154. return r;
  155. }
  156. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  157. struct radeon_fence *fence = ib->sync_to[i];
  158. if (radeon_fence_need_sync(fence, ib->ring)) {
  159. need_sync = true;
  160. radeon_semaphore_sync_rings(rdev, ib->semaphore,
  161. fence->ring, ib->ring);
  162. radeon_fence_note_sync(fence, ib->ring);
  163. }
  164. }
  165. /* immediately free semaphore when we don't need to sync */
  166. if (!need_sync) {
  167. radeon_semaphore_free(rdev, &ib->semaphore, NULL);
  168. }
  169. /* if we can't remember our last VM flush then flush now! */
  170. /* XXX figure out why we have to flush for every IB */
  171. if (ib->vm /*&& !ib->vm->last_flush*/) {
  172. radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
  173. }
  174. if (const_ib) {
  175. radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
  176. radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
  177. }
  178. radeon_ring_ib_execute(rdev, ib->ring, ib);
  179. r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
  180. if (r) {
  181. dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
  182. radeon_ring_unlock_undo(rdev, ring);
  183. return r;
  184. }
  185. if (const_ib) {
  186. const_ib->fence = radeon_fence_ref(ib->fence);
  187. }
  188. /* we just flushed the VM, remember that */
  189. if (ib->vm && !ib->vm->last_flush) {
  190. ib->vm->last_flush = radeon_fence_ref(ib->fence);
  191. }
  192. radeon_ring_unlock_commit(rdev, ring);
  193. return 0;
  194. }
  195. /**
  196. * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
  197. *
  198. * @rdev: radeon_device pointer
  199. *
  200. * Initialize the suballocator to manage a pool of memory
  201. * for use as IBs (all asics).
  202. * Returns 0 on success, error on failure.
  203. */
  204. int radeon_ib_pool_init(struct radeon_device *rdev)
  205. {
  206. int r;
  207. if (rdev->ib_pool_ready) {
  208. return 0;
  209. }
  210. r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
  211. RADEON_IB_POOL_SIZE*64*1024,
  212. RADEON_GPU_PAGE_SIZE,
  213. RADEON_GEM_DOMAIN_GTT);
  214. if (r) {
  215. return r;
  216. }
  217. r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
  218. if (r) {
  219. return r;
  220. }
  221. rdev->ib_pool_ready = true;
  222. if (radeon_debugfs_sa_init(rdev)) {
  223. dev_err(rdev->dev, "failed to register debugfs file for SA\n");
  224. }
  225. return 0;
  226. }
  227. /**
  228. * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
  229. *
  230. * @rdev: radeon_device pointer
  231. *
  232. * Tear down the suballocator managing the pool of memory
  233. * for use as IBs (all asics).
  234. */
  235. void radeon_ib_pool_fini(struct radeon_device *rdev)
  236. {
  237. if (rdev->ib_pool_ready) {
  238. radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
  239. radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
  240. rdev->ib_pool_ready = false;
  241. }
  242. }
  243. /**
  244. * radeon_ib_ring_tests - test IBs on the rings
  245. *
  246. * @rdev: radeon_device pointer
  247. *
  248. * Test an IB (Indirect Buffer) on each ring.
  249. * If the test fails, disable the ring.
  250. * Returns 0 on success, error if the primary GFX ring
  251. * IB test fails.
  252. */
  253. int radeon_ib_ring_tests(struct radeon_device *rdev)
  254. {
  255. unsigned i;
  256. int r;
  257. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  258. struct radeon_ring *ring = &rdev->ring[i];
  259. if (!ring->ready)
  260. continue;
  261. r = radeon_ib_test(rdev, i, ring);
  262. if (r) {
  263. ring->ready = false;
  264. if (i == RADEON_RING_TYPE_GFX_INDEX) {
  265. /* oh, oh, that's really bad */
  266. DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
  267. rdev->accel_working = false;
  268. return r;
  269. } else {
  270. /* still not good, but we can live with it */
  271. DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
  272. }
  273. }
  274. }
  275. return 0;
  276. }
  277. /*
  278. * Rings
  279. * Most engines on the GPU are fed via ring buffers. Ring
  280. * buffers are areas of GPU accessible memory that the host
  281. * writes commands into and the GPU reads commands out of.
  282. * There is a rptr (read pointer) that determines where the
  283. * GPU is currently reading, and a wptr (write pointer)
  284. * which determines where the host has written. When the
  285. * pointers are equal, the ring is idle. When the host
  286. * writes commands to the ring buffer, it increments the
  287. * wptr. The GPU then starts fetching commands and executes
  288. * them until the pointers are equal again.
  289. */
  290. static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
  291. /**
  292. * radeon_ring_write - write a value to the ring
  293. *
  294. * @ring: radeon_ring structure holding ring information
  295. * @v: dword (dw) value to write
  296. *
  297. * Write a value to the requested ring buffer (all asics).
  298. */
  299. void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  300. {
  301. #if DRM_DEBUG_CODE
  302. if (ring->count_dw <= 0) {
  303. DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
  304. }
  305. #endif
  306. ring->ring[ring->wptr++] = v;
  307. ring->wptr &= ring->ptr_mask;
  308. ring->count_dw--;
  309. ring->ring_free_dw--;
  310. }
  311. /**
  312. * radeon_ring_supports_scratch_reg - check if the ring supports
  313. * writing to scratch registers
  314. *
  315. * @rdev: radeon_device pointer
  316. * @ring: radeon_ring structure holding ring information
  317. *
  318. * Check if a specific ring supports writing to scratch registers (all asics).
  319. * Returns true if the ring supports writing to scratch regs, false if not.
  320. */
  321. bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
  322. struct radeon_ring *ring)
  323. {
  324. switch (ring->idx) {
  325. case RADEON_RING_TYPE_GFX_INDEX:
  326. case CAYMAN_RING_TYPE_CP1_INDEX:
  327. case CAYMAN_RING_TYPE_CP2_INDEX:
  328. return true;
  329. default:
  330. return false;
  331. }
  332. }
  333. u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
  334. struct radeon_ring *ring)
  335. {
  336. u32 rptr;
  337. if (rdev->wb.enabled)
  338. rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
  339. else
  340. rptr = RREG32(ring->rptr_reg);
  341. return rptr;
  342. }
  343. u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
  344. struct radeon_ring *ring)
  345. {
  346. u32 wptr;
  347. wptr = RREG32(ring->wptr_reg);
  348. return wptr;
  349. }
  350. void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
  351. struct radeon_ring *ring)
  352. {
  353. WREG32(ring->wptr_reg, ring->wptr);
  354. (void)RREG32(ring->wptr_reg);
  355. }
  356. /**
  357. * radeon_ring_free_size - update the free size
  358. *
  359. * @rdev: radeon_device pointer
  360. * @ring: radeon_ring structure holding ring information
  361. *
  362. * Update the free dw slots in the ring buffer (all asics).
  363. */
  364. void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
  365. {
  366. ring->rptr = radeon_ring_get_rptr(rdev, ring);
  367. /* This works because ring_size is a power of 2 */
  368. ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
  369. ring->ring_free_dw -= ring->wptr;
  370. ring->ring_free_dw &= ring->ptr_mask;
  371. if (!ring->ring_free_dw) {
  372. ring->ring_free_dw = ring->ring_size / 4;
  373. }
  374. }
  375. /**
  376. * radeon_ring_alloc - allocate space on the ring buffer
  377. *
  378. * @rdev: radeon_device pointer
  379. * @ring: radeon_ring structure holding ring information
  380. * @ndw: number of dwords to allocate in the ring buffer
  381. *
  382. * Allocate @ndw dwords in the ring buffer (all asics).
  383. * Returns 0 on success, error on failure.
  384. */
  385. int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
  386. {
  387. int r;
  388. /* make sure we aren't trying to allocate more space than there is on the ring */
  389. if (ndw > (ring->ring_size / 4))
  390. return -ENOMEM;
  391. /* Align requested size with padding so unlock_commit can
  392. * pad safely */
  393. radeon_ring_free_size(rdev, ring);
  394. if (ring->ring_free_dw == (ring->ring_size / 4)) {
  395. /* This is an empty ring update lockup info to avoid
  396. * false positive.
  397. */
  398. radeon_ring_lockup_update(ring);
  399. }
  400. ndw = (ndw + ring->align_mask) & ~ring->align_mask;
  401. while (ndw > (ring->ring_free_dw - 1)) {
  402. radeon_ring_free_size(rdev, ring);
  403. if (ndw < ring->ring_free_dw) {
  404. break;
  405. }
  406. r = radeon_fence_wait_next_locked(rdev, ring->idx);
  407. if (r)
  408. return r;
  409. }
  410. ring->count_dw = ndw;
  411. ring->wptr_old = ring->wptr;
  412. return 0;
  413. }
  414. /**
  415. * radeon_ring_lock - lock the ring and allocate space on it
  416. *
  417. * @rdev: radeon_device pointer
  418. * @ring: radeon_ring structure holding ring information
  419. * @ndw: number of dwords to allocate in the ring buffer
  420. *
  421. * Lock the ring and allocate @ndw dwords in the ring buffer
  422. * (all asics).
  423. * Returns 0 on success, error on failure.
  424. */
  425. int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
  426. {
  427. int r;
  428. mutex_lock(&rdev->ring_lock);
  429. r = radeon_ring_alloc(rdev, ring, ndw);
  430. if (r) {
  431. mutex_unlock(&rdev->ring_lock);
  432. return r;
  433. }
  434. return 0;
  435. }
  436. /**
  437. * radeon_ring_commit - tell the GPU to execute the new
  438. * commands on the ring buffer
  439. *
  440. * @rdev: radeon_device pointer
  441. * @ring: radeon_ring structure holding ring information
  442. *
  443. * Update the wptr (write pointer) to tell the GPU to
  444. * execute new commands on the ring buffer (all asics).
  445. */
  446. void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
  447. {
  448. /* We pad to match fetch size */
  449. while (ring->wptr & ring->align_mask) {
  450. radeon_ring_write(ring, ring->nop);
  451. }
  452. DRM_MEMORYBARRIER();
  453. radeon_ring_set_wptr(rdev, ring);
  454. }
  455. /**
  456. * radeon_ring_unlock_commit - tell the GPU to execute the new
  457. * commands on the ring buffer and unlock it
  458. *
  459. * @rdev: radeon_device pointer
  460. * @ring: radeon_ring structure holding ring information
  461. *
  462. * Call radeon_ring_commit() then unlock the ring (all asics).
  463. */
  464. void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
  465. {
  466. radeon_ring_commit(rdev, ring);
  467. mutex_unlock(&rdev->ring_lock);
  468. }
  469. /**
  470. * radeon_ring_undo - reset the wptr
  471. *
  472. * @ring: radeon_ring structure holding ring information
  473. *
  474. * Reset the driver's copy of the wptr (all asics).
  475. */
  476. void radeon_ring_undo(struct radeon_ring *ring)
  477. {
  478. ring->wptr = ring->wptr_old;
  479. }
  480. /**
  481. * radeon_ring_unlock_undo - reset the wptr and unlock the ring
  482. *
  483. * @ring: radeon_ring structure holding ring information
  484. *
  485. * Call radeon_ring_undo() then unlock the ring (all asics).
  486. */
  487. void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
  488. {
  489. radeon_ring_undo(ring);
  490. mutex_unlock(&rdev->ring_lock);
  491. }
  492. /**
  493. * radeon_ring_force_activity - add some nop packets to the ring
  494. *
  495. * @rdev: radeon_device pointer
  496. * @ring: radeon_ring structure holding ring information
  497. *
  498. * Add some nop packets to the ring to force activity (all asics).
  499. * Used for lockup detection to see if the rptr is advancing.
  500. */
  501. void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
  502. {
  503. int r;
  504. radeon_ring_free_size(rdev, ring);
  505. if (ring->rptr == ring->wptr) {
  506. r = radeon_ring_alloc(rdev, ring, 1);
  507. if (!r) {
  508. radeon_ring_write(ring, ring->nop);
  509. radeon_ring_commit(rdev, ring);
  510. }
  511. }
  512. }
  513. /**
  514. * radeon_ring_lockup_update - update lockup variables
  515. *
  516. * @ring: radeon_ring structure holding ring information
  517. *
  518. * Update the last rptr value and timestamp (all asics).
  519. */
  520. void radeon_ring_lockup_update(struct radeon_ring *ring)
  521. {
  522. ring->last_rptr = ring->rptr;
  523. ring->last_activity = jiffies;
  524. }
  525. /**
  526. * radeon_ring_test_lockup() - check if ring is lockedup by recording information
  527. * @rdev: radeon device structure
  528. * @ring: radeon_ring structure holding ring information
  529. *
  530. * We don't need to initialize the lockup tracking information as we will either
  531. * have CP rptr to a different value of jiffies wrap around which will force
  532. * initialization of the lockup tracking informations.
  533. *
  534. * A possible false positivie is if we get call after while and last_cp_rptr ==
  535. * the current CP rptr, even if it's unlikely it might happen. To avoid this
  536. * if the elapsed time since last call is bigger than 2 second than we return
  537. * false and update the tracking information. Due to this the caller must call
  538. * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
  539. * the fencing code should be cautious about that.
  540. *
  541. * Caller should write to the ring to force CP to do something so we don't get
  542. * false positive when CP is just gived nothing to do.
  543. *
  544. **/
  545. bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  546. {
  547. unsigned long cjiffies, elapsed;
  548. cjiffies = jiffies;
  549. if (!time_after(cjiffies, ring->last_activity)) {
  550. /* likely a wrap around */
  551. radeon_ring_lockup_update(ring);
  552. return false;
  553. }
  554. ring->rptr = radeon_ring_get_rptr(rdev, ring);
  555. if (ring->rptr != ring->last_rptr) {
  556. /* CP is still working no lockup */
  557. radeon_ring_lockup_update(ring);
  558. return false;
  559. }
  560. elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
  561. if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
  562. dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
  563. return true;
  564. }
  565. /* give a chance to the GPU ... */
  566. return false;
  567. }
  568. /**
  569. * radeon_ring_backup - Back up the content of a ring
  570. *
  571. * @rdev: radeon_device pointer
  572. * @ring: the ring we want to back up
  573. *
  574. * Saves all unprocessed commits from a ring, returns the number of dwords saved.
  575. */
  576. unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
  577. uint32_t **data)
  578. {
  579. unsigned size, ptr, i;
  580. /* just in case lock the ring */
  581. mutex_lock(&rdev->ring_lock);
  582. *data = NULL;
  583. if (ring->ring_obj == NULL) {
  584. mutex_unlock(&rdev->ring_lock);
  585. return 0;
  586. }
  587. /* it doesn't make sense to save anything if all fences are signaled */
  588. if (!radeon_fence_count_emitted(rdev, ring->idx)) {
  589. mutex_unlock(&rdev->ring_lock);
  590. return 0;
  591. }
  592. /* calculate the number of dw on the ring */
  593. if (ring->rptr_save_reg)
  594. ptr = RREG32(ring->rptr_save_reg);
  595. else if (rdev->wb.enabled)
  596. ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
  597. else {
  598. /* no way to read back the next rptr */
  599. mutex_unlock(&rdev->ring_lock);
  600. return 0;
  601. }
  602. size = ring->wptr + (ring->ring_size / 4);
  603. size -= ptr;
  604. size &= ring->ptr_mask;
  605. if (size == 0) {
  606. mutex_unlock(&rdev->ring_lock);
  607. return 0;
  608. }
  609. /* and then save the content of the ring */
  610. *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
  611. if (!*data) {
  612. mutex_unlock(&rdev->ring_lock);
  613. return 0;
  614. }
  615. for (i = 0; i < size; ++i) {
  616. (*data)[i] = ring->ring[ptr++];
  617. ptr &= ring->ptr_mask;
  618. }
  619. mutex_unlock(&rdev->ring_lock);
  620. return size;
  621. }
  622. /**
  623. * radeon_ring_restore - append saved commands to the ring again
  624. *
  625. * @rdev: radeon_device pointer
  626. * @ring: ring to append commands to
  627. * @size: number of dwords we want to write
  628. * @data: saved commands
  629. *
  630. * Allocates space on the ring and restore the previously saved commands.
  631. */
  632. int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  633. unsigned size, uint32_t *data)
  634. {
  635. int i, r;
  636. if (!size || !data)
  637. return 0;
  638. /* restore the saved ring content */
  639. r = radeon_ring_lock(rdev, ring, size);
  640. if (r)
  641. return r;
  642. for (i = 0; i < size; ++i) {
  643. radeon_ring_write(ring, data[i]);
  644. }
  645. radeon_ring_unlock_commit(rdev, ring);
  646. kfree(data);
  647. return 0;
  648. }
  649. /**
  650. * radeon_ring_init - init driver ring struct.
  651. *
  652. * @rdev: radeon_device pointer
  653. * @ring: radeon_ring structure holding ring information
  654. * @ring_size: size of the ring
  655. * @rptr_offs: offset of the rptr writeback location in the WB buffer
  656. * @rptr_reg: MMIO offset of the rptr register
  657. * @wptr_reg: MMIO offset of the wptr register
  658. * @nop: nop packet for this ring
  659. *
  660. * Initialize the driver information for the selected ring (all asics).
  661. * Returns 0 on success, error on failure.
  662. */
  663. int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
  664. unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop)
  665. {
  666. int r;
  667. ring->ring_size = ring_size;
  668. ring->rptr_offs = rptr_offs;
  669. ring->rptr_reg = rptr_reg;
  670. ring->wptr_reg = wptr_reg;
  671. ring->nop = nop;
  672. /* Allocate ring buffer */
  673. if (ring->ring_obj == NULL) {
  674. r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
  675. RADEON_GEM_DOMAIN_GTT,
  676. NULL, &ring->ring_obj);
  677. if (r) {
  678. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  679. return r;
  680. }
  681. r = radeon_bo_reserve(ring->ring_obj, false);
  682. if (unlikely(r != 0))
  683. return r;
  684. r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
  685. &ring->gpu_addr);
  686. if (r) {
  687. radeon_bo_unreserve(ring->ring_obj);
  688. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  689. return r;
  690. }
  691. r = radeon_bo_kmap(ring->ring_obj,
  692. (void **)&ring->ring);
  693. radeon_bo_unreserve(ring->ring_obj);
  694. if (r) {
  695. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  696. return r;
  697. }
  698. }
  699. ring->ptr_mask = (ring->ring_size / 4) - 1;
  700. ring->ring_free_dw = ring->ring_size / 4;
  701. if (rdev->wb.enabled) {
  702. u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
  703. ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
  704. ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
  705. }
  706. if (radeon_debugfs_ring_init(rdev, ring)) {
  707. DRM_ERROR("Failed to register debugfs file for rings !\n");
  708. }
  709. radeon_ring_lockup_update(ring);
  710. return 0;
  711. }
  712. /**
  713. * radeon_ring_fini - tear down the driver ring struct.
  714. *
  715. * @rdev: radeon_device pointer
  716. * @ring: radeon_ring structure holding ring information
  717. *
  718. * Tear down the driver information for the selected ring (all asics).
  719. */
  720. void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
  721. {
  722. int r;
  723. struct radeon_bo *ring_obj;
  724. mutex_lock(&rdev->ring_lock);
  725. ring_obj = ring->ring_obj;
  726. ring->ready = false;
  727. ring->ring = NULL;
  728. ring->ring_obj = NULL;
  729. mutex_unlock(&rdev->ring_lock);
  730. if (ring_obj) {
  731. r = radeon_bo_reserve(ring_obj, false);
  732. if (likely(r == 0)) {
  733. radeon_bo_kunmap(ring_obj);
  734. radeon_bo_unpin(ring_obj);
  735. radeon_bo_unreserve(ring_obj);
  736. }
  737. radeon_bo_unref(&ring_obj);
  738. }
  739. }
  740. /*
  741. * Debugfs info
  742. */
  743. #if defined(CONFIG_DEBUG_FS)
  744. static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
  745. {
  746. struct drm_info_node *node = (struct drm_info_node *) m->private;
  747. struct drm_device *dev = node->minor->dev;
  748. struct radeon_device *rdev = dev->dev_private;
  749. int ridx = *(int*)node->info_ent->data;
  750. struct radeon_ring *ring = &rdev->ring[ridx];
  751. unsigned count, i, j;
  752. u32 tmp;
  753. radeon_ring_free_size(rdev, ring);
  754. count = (ring->ring_size / 4) - ring->ring_free_dw;
  755. tmp = radeon_ring_get_wptr(rdev, ring);
  756. seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
  757. tmp = radeon_ring_get_rptr(rdev, ring);
  758. seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
  759. if (ring->rptr_save_reg) {
  760. seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
  761. RREG32(ring->rptr_save_reg));
  762. }
  763. seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
  764. seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
  765. seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
  766. seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr);
  767. seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
  768. seq_printf(m, "%u dwords in ring\n", count);
  769. /* print 8 dw before current rptr as often it's the last executed
  770. * packet that is the root issue
  771. */
  772. i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
  773. if (ring->ready) {
  774. for (j = 0; j <= (count + 32); j++) {
  775. seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
  776. i = (i + 1) & ring->ptr_mask;
  777. }
  778. }
  779. return 0;
  780. }
  781. static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
  782. static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
  783. static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
  784. static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
  785. static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
  786. static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
  787. static struct drm_info_list radeon_debugfs_ring_info_list[] = {
  788. {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
  789. {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
  790. {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
  791. {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
  792. {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
  793. {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
  794. };
  795. static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
  796. {
  797. struct drm_info_node *node = (struct drm_info_node *) m->private;
  798. struct drm_device *dev = node->minor->dev;
  799. struct radeon_device *rdev = dev->dev_private;
  800. radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
  801. return 0;
  802. }
  803. static struct drm_info_list radeon_debugfs_sa_list[] = {
  804. {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
  805. };
  806. #endif
  807. static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
  808. {
  809. #if defined(CONFIG_DEBUG_FS)
  810. unsigned i;
  811. for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
  812. struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
  813. int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
  814. unsigned r;
  815. if (&rdev->ring[ridx] != ring)
  816. continue;
  817. r = radeon_debugfs_add_files(rdev, info, 1);
  818. if (r)
  819. return r;
  820. }
  821. #endif
  822. return 0;
  823. }
  824. static int radeon_debugfs_sa_init(struct radeon_device *rdev)
  825. {
  826. #if defined(CONFIG_DEBUG_FS)
  827. return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
  828. #else
  829. return 0;
  830. #endif
  831. }