radeon_object.c 15 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <linux/slab.h>
  34. #include <drm/drmP.h>
  35. #include <drm/radeon_drm.h>
  36. #include "radeon.h"
  37. #include "radeon_trace.h"
  38. int radeon_ttm_init(struct radeon_device *rdev);
  39. void radeon_ttm_fini(struct radeon_device *rdev);
  40. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  41. /*
  42. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  43. * function are calling it.
  44. */
  45. void radeon_bo_clear_va(struct radeon_bo *bo)
  46. {
  47. struct radeon_bo_va *bo_va, *tmp;
  48. list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  49. /* remove from all vm address space */
  50. radeon_vm_bo_rmv(bo->rdev, bo_va);
  51. }
  52. }
  53. static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54. {
  55. struct radeon_bo *bo;
  56. bo = container_of(tbo, struct radeon_bo, tbo);
  57. mutex_lock(&bo->rdev->gem.mutex);
  58. list_del_init(&bo->list);
  59. mutex_unlock(&bo->rdev->gem.mutex);
  60. radeon_bo_clear_surface_reg(bo);
  61. radeon_bo_clear_va(bo);
  62. drm_gem_object_release(&bo->gem_base);
  63. kfree(bo);
  64. }
  65. bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  66. {
  67. if (bo->destroy == &radeon_ttm_bo_destroy)
  68. return true;
  69. return false;
  70. }
  71. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  72. {
  73. u32 c = 0;
  74. rbo->placement.fpfn = 0;
  75. rbo->placement.lpfn = 0;
  76. rbo->placement.placement = rbo->placements;
  77. rbo->placement.busy_placement = rbo->placements;
  78. if (domain & RADEON_GEM_DOMAIN_VRAM)
  79. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  80. TTM_PL_FLAG_VRAM;
  81. if (domain & RADEON_GEM_DOMAIN_GTT) {
  82. if (rbo->rdev->flags & RADEON_IS_AGP) {
  83. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
  84. } else {
  85. rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
  86. }
  87. }
  88. if (domain & RADEON_GEM_DOMAIN_CPU) {
  89. if (rbo->rdev->flags & RADEON_IS_AGP) {
  90. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
  91. } else {
  92. rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
  93. }
  94. }
  95. if (!c)
  96. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  97. rbo->placement.num_placement = c;
  98. rbo->placement.num_busy_placement = c;
  99. }
  100. int radeon_bo_create(struct radeon_device *rdev,
  101. unsigned long size, int byte_align, bool kernel, u32 domain,
  102. struct sg_table *sg, struct radeon_bo **bo_ptr)
  103. {
  104. struct radeon_bo *bo;
  105. enum ttm_bo_type type;
  106. unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
  107. size_t acc_size;
  108. int r;
  109. size = ALIGN(size, PAGE_SIZE);
  110. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  111. if (kernel) {
  112. type = ttm_bo_type_kernel;
  113. } else if (sg) {
  114. type = ttm_bo_type_sg;
  115. } else {
  116. type = ttm_bo_type_device;
  117. }
  118. *bo_ptr = NULL;
  119. acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
  120. sizeof(struct radeon_bo));
  121. bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  122. if (bo == NULL)
  123. return -ENOMEM;
  124. r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
  125. if (unlikely(r)) {
  126. kfree(bo);
  127. return r;
  128. }
  129. bo->rdev = rdev;
  130. bo->surface_reg = -1;
  131. INIT_LIST_HEAD(&bo->list);
  132. INIT_LIST_HEAD(&bo->va);
  133. radeon_ttm_placement_from_domain(bo, domain);
  134. /* Kernel allocation are uninterruptible */
  135. down_read(&rdev->pm.mclk_lock);
  136. r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
  137. &bo->placement, page_align, !kernel, NULL,
  138. acc_size, sg, &radeon_ttm_bo_destroy);
  139. up_read(&rdev->pm.mclk_lock);
  140. if (unlikely(r != 0)) {
  141. return r;
  142. }
  143. *bo_ptr = bo;
  144. trace_radeon_bo_create(bo);
  145. return 0;
  146. }
  147. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  148. {
  149. bool is_iomem;
  150. int r;
  151. if (bo->kptr) {
  152. if (ptr) {
  153. *ptr = bo->kptr;
  154. }
  155. return 0;
  156. }
  157. r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
  158. if (r) {
  159. return r;
  160. }
  161. bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
  162. if (ptr) {
  163. *ptr = bo->kptr;
  164. }
  165. radeon_bo_check_tiling(bo, 0, 0);
  166. return 0;
  167. }
  168. void radeon_bo_kunmap(struct radeon_bo *bo)
  169. {
  170. if (bo->kptr == NULL)
  171. return;
  172. bo->kptr = NULL;
  173. radeon_bo_check_tiling(bo, 0, 0);
  174. ttm_bo_kunmap(&bo->kmap);
  175. }
  176. void radeon_bo_unref(struct radeon_bo **bo)
  177. {
  178. struct ttm_buffer_object *tbo;
  179. struct radeon_device *rdev;
  180. if ((*bo) == NULL)
  181. return;
  182. rdev = (*bo)->rdev;
  183. tbo = &((*bo)->tbo);
  184. down_read(&rdev->pm.mclk_lock);
  185. ttm_bo_unref(&tbo);
  186. up_read(&rdev->pm.mclk_lock);
  187. if (tbo == NULL)
  188. *bo = NULL;
  189. }
  190. int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
  191. u64 *gpu_addr)
  192. {
  193. int r, i;
  194. if (bo->pin_count) {
  195. bo->pin_count++;
  196. if (gpu_addr)
  197. *gpu_addr = radeon_bo_gpu_offset(bo);
  198. if (max_offset != 0) {
  199. u64 domain_start;
  200. if (domain == RADEON_GEM_DOMAIN_VRAM)
  201. domain_start = bo->rdev->mc.vram_start;
  202. else
  203. domain_start = bo->rdev->mc.gtt_start;
  204. WARN_ON_ONCE(max_offset <
  205. (radeon_bo_gpu_offset(bo) - domain_start));
  206. }
  207. return 0;
  208. }
  209. radeon_ttm_placement_from_domain(bo, domain);
  210. if (domain == RADEON_GEM_DOMAIN_VRAM) {
  211. /* force to pin into visible video ram */
  212. bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
  213. }
  214. if (max_offset) {
  215. u64 lpfn = max_offset >> PAGE_SHIFT;
  216. if (!bo->placement.lpfn)
  217. bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
  218. if (lpfn < bo->placement.lpfn)
  219. bo->placement.lpfn = lpfn;
  220. }
  221. for (i = 0; i < bo->placement.num_placement; i++)
  222. bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
  223. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  224. if (likely(r == 0)) {
  225. bo->pin_count = 1;
  226. if (gpu_addr != NULL)
  227. *gpu_addr = radeon_bo_gpu_offset(bo);
  228. }
  229. if (unlikely(r != 0))
  230. dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  231. return r;
  232. }
  233. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  234. {
  235. return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
  236. }
  237. int radeon_bo_unpin(struct radeon_bo *bo)
  238. {
  239. int r, i;
  240. if (!bo->pin_count) {
  241. dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  242. return 0;
  243. }
  244. bo->pin_count--;
  245. if (bo->pin_count)
  246. return 0;
  247. for (i = 0; i < bo->placement.num_placement; i++)
  248. bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
  249. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  250. if (unlikely(r != 0))
  251. dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
  252. return r;
  253. }
  254. int radeon_bo_evict_vram(struct radeon_device *rdev)
  255. {
  256. /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
  257. if (0 && (rdev->flags & RADEON_IS_IGP)) {
  258. if (rdev->mc.igp_sideport_enabled == false)
  259. /* Useless to evict on IGP chips */
  260. return 0;
  261. }
  262. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  263. }
  264. void radeon_bo_force_delete(struct radeon_device *rdev)
  265. {
  266. struct radeon_bo *bo, *n;
  267. if (list_empty(&rdev->gem.objects)) {
  268. return;
  269. }
  270. dev_err(rdev->dev, "Userspace still has active objects !\n");
  271. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  272. mutex_lock(&rdev->ddev->struct_mutex);
  273. dev_err(rdev->dev, "%p %p %lu %lu force free\n",
  274. &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
  275. *((unsigned long *)&bo->gem_base.refcount));
  276. mutex_lock(&bo->rdev->gem.mutex);
  277. list_del_init(&bo->list);
  278. mutex_unlock(&bo->rdev->gem.mutex);
  279. /* this should unref the ttm bo */
  280. drm_gem_object_unreference(&bo->gem_base);
  281. mutex_unlock(&rdev->ddev->struct_mutex);
  282. }
  283. }
  284. int radeon_bo_init(struct radeon_device *rdev)
  285. {
  286. /* Add an MTRR for the VRAM */
  287. if (!rdev->fastfb_working) {
  288. rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
  289. rdev->mc.aper_size);
  290. }
  291. DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  292. rdev->mc.mc_vram_size >> 20,
  293. (unsigned long long)rdev->mc.aper_size >> 20);
  294. DRM_INFO("RAM width %dbits %cDR\n",
  295. rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  296. return radeon_ttm_init(rdev);
  297. }
  298. void radeon_bo_fini(struct radeon_device *rdev)
  299. {
  300. radeon_ttm_fini(rdev);
  301. arch_phys_wc_del(rdev->mc.vram_mtrr);
  302. }
  303. void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
  304. struct list_head *head)
  305. {
  306. if (lobj->written) {
  307. list_add(&lobj->tv.head, head);
  308. } else {
  309. list_add_tail(&lobj->tv.head, head);
  310. }
  311. }
  312. int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
  313. struct list_head *head, int ring)
  314. {
  315. struct radeon_bo_list *lobj;
  316. struct radeon_bo *bo;
  317. u32 domain;
  318. int r;
  319. r = ttm_eu_reserve_buffers(ticket, head);
  320. if (unlikely(r != 0)) {
  321. return r;
  322. }
  323. list_for_each_entry(lobj, head, tv.head) {
  324. bo = lobj->bo;
  325. if (!bo->pin_count) {
  326. domain = lobj->domain;
  327. retry:
  328. radeon_ttm_placement_from_domain(bo, domain);
  329. if (ring == R600_RING_TYPE_UVD_INDEX)
  330. radeon_uvd_force_into_uvd_segment(bo);
  331. r = ttm_bo_validate(&bo->tbo, &bo->placement,
  332. true, false);
  333. if (unlikely(r)) {
  334. if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
  335. domain = lobj->alt_domain;
  336. goto retry;
  337. }
  338. ttm_eu_backoff_reservation(ticket, head);
  339. return r;
  340. }
  341. }
  342. lobj->gpu_offset = radeon_bo_gpu_offset(bo);
  343. lobj->tiling_flags = bo->tiling_flags;
  344. }
  345. return 0;
  346. }
  347. int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
  348. struct vm_area_struct *vma)
  349. {
  350. return ttm_fbdev_mmap(vma, &bo->tbo);
  351. }
  352. int radeon_bo_get_surface_reg(struct radeon_bo *bo)
  353. {
  354. struct radeon_device *rdev = bo->rdev;
  355. struct radeon_surface_reg *reg;
  356. struct radeon_bo *old_object;
  357. int steal;
  358. int i;
  359. lockdep_assert_held(&bo->tbo.resv->lock.base);
  360. if (!bo->tiling_flags)
  361. return 0;
  362. if (bo->surface_reg >= 0) {
  363. reg = &rdev->surface_regs[bo->surface_reg];
  364. i = bo->surface_reg;
  365. goto out;
  366. }
  367. steal = -1;
  368. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  369. reg = &rdev->surface_regs[i];
  370. if (!reg->bo)
  371. break;
  372. old_object = reg->bo;
  373. if (old_object->pin_count == 0)
  374. steal = i;
  375. }
  376. /* if we are all out */
  377. if (i == RADEON_GEM_MAX_SURFACES) {
  378. if (steal == -1)
  379. return -ENOMEM;
  380. /* find someone with a surface reg and nuke their BO */
  381. reg = &rdev->surface_regs[steal];
  382. old_object = reg->bo;
  383. /* blow away the mapping */
  384. DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
  385. ttm_bo_unmap_virtual(&old_object->tbo);
  386. old_object->surface_reg = -1;
  387. i = steal;
  388. }
  389. bo->surface_reg = i;
  390. reg->bo = bo;
  391. out:
  392. radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
  393. bo->tbo.mem.start << PAGE_SHIFT,
  394. bo->tbo.num_pages << PAGE_SHIFT);
  395. return 0;
  396. }
  397. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
  398. {
  399. struct radeon_device *rdev = bo->rdev;
  400. struct radeon_surface_reg *reg;
  401. if (bo->surface_reg == -1)
  402. return;
  403. reg = &rdev->surface_regs[bo->surface_reg];
  404. radeon_clear_surface_reg(rdev, bo->surface_reg);
  405. reg->bo = NULL;
  406. bo->surface_reg = -1;
  407. }
  408. int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
  409. uint32_t tiling_flags, uint32_t pitch)
  410. {
  411. struct radeon_device *rdev = bo->rdev;
  412. int r;
  413. if (rdev->family >= CHIP_CEDAR) {
  414. unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
  415. bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  416. bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  417. mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  418. tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  419. stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
  420. switch (bankw) {
  421. case 0:
  422. case 1:
  423. case 2:
  424. case 4:
  425. case 8:
  426. break;
  427. default:
  428. return -EINVAL;
  429. }
  430. switch (bankh) {
  431. case 0:
  432. case 1:
  433. case 2:
  434. case 4:
  435. case 8:
  436. break;
  437. default:
  438. return -EINVAL;
  439. }
  440. switch (mtaspect) {
  441. case 0:
  442. case 1:
  443. case 2:
  444. case 4:
  445. case 8:
  446. break;
  447. default:
  448. return -EINVAL;
  449. }
  450. if (tilesplit > 6) {
  451. return -EINVAL;
  452. }
  453. if (stilesplit > 6) {
  454. return -EINVAL;
  455. }
  456. }
  457. r = radeon_bo_reserve(bo, false);
  458. if (unlikely(r != 0))
  459. return r;
  460. bo->tiling_flags = tiling_flags;
  461. bo->pitch = pitch;
  462. radeon_bo_unreserve(bo);
  463. return 0;
  464. }
  465. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  466. uint32_t *tiling_flags,
  467. uint32_t *pitch)
  468. {
  469. lockdep_assert_held(&bo->tbo.resv->lock.base);
  470. if (tiling_flags)
  471. *tiling_flags = bo->tiling_flags;
  472. if (pitch)
  473. *pitch = bo->pitch;
  474. }
  475. int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
  476. bool force_drop)
  477. {
  478. if (!force_drop)
  479. lockdep_assert_held(&bo->tbo.resv->lock.base);
  480. if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
  481. return 0;
  482. if (force_drop) {
  483. radeon_bo_clear_surface_reg(bo);
  484. return 0;
  485. }
  486. if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
  487. if (!has_moved)
  488. return 0;
  489. if (bo->surface_reg >= 0)
  490. radeon_bo_clear_surface_reg(bo);
  491. return 0;
  492. }
  493. if ((bo->surface_reg >= 0) && !has_moved)
  494. return 0;
  495. return radeon_bo_get_surface_reg(bo);
  496. }
  497. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  498. struct ttm_mem_reg *mem)
  499. {
  500. struct radeon_bo *rbo;
  501. if (!radeon_ttm_bo_is_radeon_bo(bo))
  502. return;
  503. rbo = container_of(bo, struct radeon_bo, tbo);
  504. radeon_bo_check_tiling(rbo, 0, 1);
  505. radeon_vm_bo_invalidate(rbo->rdev, rbo);
  506. }
  507. int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
  508. {
  509. struct radeon_device *rdev;
  510. struct radeon_bo *rbo;
  511. unsigned long offset, size;
  512. int r;
  513. if (!radeon_ttm_bo_is_radeon_bo(bo))
  514. return 0;
  515. rbo = container_of(bo, struct radeon_bo, tbo);
  516. radeon_bo_check_tiling(rbo, 0, 0);
  517. rdev = rbo->rdev;
  518. if (bo->mem.mem_type == TTM_PL_VRAM) {
  519. size = bo->mem.num_pages << PAGE_SHIFT;
  520. offset = bo->mem.start << PAGE_SHIFT;
  521. if ((offset + size) > rdev->mc.visible_vram_size) {
  522. /* hurrah the memory is not visible ! */
  523. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
  524. rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
  525. r = ttm_bo_validate(bo, &rbo->placement, false, false);
  526. if (unlikely(r != 0))
  527. return r;
  528. offset = bo->mem.start << PAGE_SHIFT;
  529. /* this should not happen */
  530. if ((offset + size) > rdev->mc.visible_vram_size)
  531. return -EINVAL;
  532. }
  533. }
  534. return 0;
  535. }
  536. int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
  537. {
  538. int r;
  539. r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
  540. if (unlikely(r != 0))
  541. return r;
  542. spin_lock(&bo->tbo.bdev->fence_lock);
  543. if (mem_type)
  544. *mem_type = bo->tbo.mem.mem_type;
  545. if (bo->tbo.sync_obj)
  546. r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
  547. spin_unlock(&bo->tbo.bdev->fence_lock);
  548. ttm_bo_unreserve(&bo->tbo);
  549. return r;
  550. }