ni.c 67 KB

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  1. /*
  2. * Copyright 2010 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <linux/slab.h>
  26. #include <linux/module.h>
  27. #include <drm/drmP.h>
  28. #include "radeon.h"
  29. #include "radeon_asic.h"
  30. #include <drm/radeon_drm.h>
  31. #include "nid.h"
  32. #include "atom.h"
  33. #include "ni_reg.h"
  34. #include "cayman_blit_shaders.h"
  35. #include "radeon_ucode.h"
  36. #include "clearstate_cayman.h"
  37. static const u32 tn_rlc_save_restore_register_list[] =
  38. {
  39. 0x98fc,
  40. 0x98f0,
  41. 0x9834,
  42. 0x9838,
  43. 0x9870,
  44. 0x9874,
  45. 0x8a14,
  46. 0x8b24,
  47. 0x8bcc,
  48. 0x8b10,
  49. 0x8c30,
  50. 0x8d00,
  51. 0x8d04,
  52. 0x8c00,
  53. 0x8c04,
  54. 0x8c10,
  55. 0x8c14,
  56. 0x8d8c,
  57. 0x8cf0,
  58. 0x8e38,
  59. 0x9508,
  60. 0x9688,
  61. 0x9608,
  62. 0x960c,
  63. 0x9610,
  64. 0x9614,
  65. 0x88c4,
  66. 0x8978,
  67. 0x88d4,
  68. 0x900c,
  69. 0x9100,
  70. 0x913c,
  71. 0x90e8,
  72. 0x9354,
  73. 0xa008,
  74. 0x98f8,
  75. 0x9148,
  76. 0x914c,
  77. 0x3f94,
  78. 0x98f4,
  79. 0x9b7c,
  80. 0x3f8c,
  81. 0x8950,
  82. 0x8954,
  83. 0x8a18,
  84. 0x8b28,
  85. 0x9144,
  86. 0x3f90,
  87. 0x915c,
  88. 0x9160,
  89. 0x9178,
  90. 0x917c,
  91. 0x9180,
  92. 0x918c,
  93. 0x9190,
  94. 0x9194,
  95. 0x9198,
  96. 0x919c,
  97. 0x91a8,
  98. 0x91ac,
  99. 0x91b0,
  100. 0x91b4,
  101. 0x91b8,
  102. 0x91c4,
  103. 0x91c8,
  104. 0x91cc,
  105. 0x91d0,
  106. 0x91d4,
  107. 0x91e0,
  108. 0x91e4,
  109. 0x91ec,
  110. 0x91f0,
  111. 0x91f4,
  112. 0x9200,
  113. 0x9204,
  114. 0x929c,
  115. 0x8030,
  116. 0x9150,
  117. 0x9a60,
  118. 0x920c,
  119. 0x9210,
  120. 0x9228,
  121. 0x922c,
  122. 0x9244,
  123. 0x9248,
  124. 0x91e8,
  125. 0x9294,
  126. 0x9208,
  127. 0x9224,
  128. 0x9240,
  129. 0x9220,
  130. 0x923c,
  131. 0x9258,
  132. 0x9744,
  133. 0xa200,
  134. 0xa204,
  135. 0xa208,
  136. 0xa20c,
  137. 0x8d58,
  138. 0x9030,
  139. 0x9034,
  140. 0x9038,
  141. 0x903c,
  142. 0x9040,
  143. 0x9654,
  144. 0x897c,
  145. 0xa210,
  146. 0xa214,
  147. 0x9868,
  148. 0xa02c,
  149. 0x9664,
  150. 0x9698,
  151. 0x949c,
  152. 0x8e10,
  153. 0x8e18,
  154. 0x8c50,
  155. 0x8c58,
  156. 0x8c60,
  157. 0x8c68,
  158. 0x89b4,
  159. 0x9830,
  160. 0x802c,
  161. };
  162. extern bool evergreen_is_display_hung(struct radeon_device *rdev);
  163. extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
  164. extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  165. extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  166. extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  167. extern void evergreen_mc_program(struct radeon_device *rdev);
  168. extern void evergreen_irq_suspend(struct radeon_device *rdev);
  169. extern int evergreen_mc_init(struct radeon_device *rdev);
  170. extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  171. extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  172. extern void evergreen_program_aspm(struct radeon_device *rdev);
  173. extern void sumo_rlc_fini(struct radeon_device *rdev);
  174. extern int sumo_rlc_init(struct radeon_device *rdev);
  175. extern void cayman_dma_vm_set_page(struct radeon_device *rdev,
  176. struct radeon_ib *ib,
  177. uint64_t pe,
  178. uint64_t addr, unsigned count,
  179. uint32_t incr, uint32_t flags);
  180. /* Firmware Names */
  181. MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  182. MODULE_FIRMWARE("radeon/BARTS_me.bin");
  183. MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  184. MODULE_FIRMWARE("radeon/BARTS_smc.bin");
  185. MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  186. MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  187. MODULE_FIRMWARE("radeon/TURKS_me.bin");
  188. MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  189. MODULE_FIRMWARE("radeon/TURKS_smc.bin");
  190. MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  191. MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  192. MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  193. MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
  194. MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  195. MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  196. MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  197. MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  198. MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
  199. MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
  200. MODULE_FIRMWARE("radeon/ARUBA_me.bin");
  201. MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
  202. static const u32 cayman_golden_registers2[] =
  203. {
  204. 0x3e5c, 0xffffffff, 0x00000000,
  205. 0x3e48, 0xffffffff, 0x00000000,
  206. 0x3e4c, 0xffffffff, 0x00000000,
  207. 0x3e64, 0xffffffff, 0x00000000,
  208. 0x3e50, 0xffffffff, 0x00000000,
  209. 0x3e60, 0xffffffff, 0x00000000
  210. };
  211. static const u32 cayman_golden_registers[] =
  212. {
  213. 0x5eb4, 0xffffffff, 0x00000002,
  214. 0x5e78, 0x8f311ff1, 0x001000f0,
  215. 0x3f90, 0xffff0000, 0xff000000,
  216. 0x9148, 0xffff0000, 0xff000000,
  217. 0x3f94, 0xffff0000, 0xff000000,
  218. 0x914c, 0xffff0000, 0xff000000,
  219. 0xc78, 0x00000080, 0x00000080,
  220. 0xbd4, 0x70073777, 0x00011003,
  221. 0xd02c, 0xbfffff1f, 0x08421000,
  222. 0xd0b8, 0x73773777, 0x02011003,
  223. 0x5bc0, 0x00200000, 0x50100000,
  224. 0x98f8, 0x33773777, 0x02011003,
  225. 0x98fc, 0xffffffff, 0x76541032,
  226. 0x7030, 0x31000311, 0x00000011,
  227. 0x2f48, 0x33773777, 0x42010001,
  228. 0x6b28, 0x00000010, 0x00000012,
  229. 0x7728, 0x00000010, 0x00000012,
  230. 0x10328, 0x00000010, 0x00000012,
  231. 0x10f28, 0x00000010, 0x00000012,
  232. 0x11b28, 0x00000010, 0x00000012,
  233. 0x12728, 0x00000010, 0x00000012,
  234. 0x240c, 0x000007ff, 0x00000000,
  235. 0x8a14, 0xf000001f, 0x00000007,
  236. 0x8b24, 0x3fff3fff, 0x00ff0fff,
  237. 0x8b10, 0x0000ff0f, 0x00000000,
  238. 0x28a4c, 0x07ffffff, 0x06000000,
  239. 0x10c, 0x00000001, 0x00010003,
  240. 0xa02c, 0xffffffff, 0x0000009b,
  241. 0x913c, 0x0000010f, 0x01000100,
  242. 0x8c04, 0xf8ff00ff, 0x40600060,
  243. 0x28350, 0x00000f01, 0x00000000,
  244. 0x9508, 0x3700001f, 0x00000002,
  245. 0x960c, 0xffffffff, 0x54763210,
  246. 0x88c4, 0x001f3ae3, 0x00000082,
  247. 0x88d0, 0xffffffff, 0x0f40df40,
  248. 0x88d4, 0x0000001f, 0x00000010,
  249. 0x8974, 0xffffffff, 0x00000000
  250. };
  251. static const u32 dvst_golden_registers2[] =
  252. {
  253. 0x8f8, 0xffffffff, 0,
  254. 0x8fc, 0x00380000, 0,
  255. 0x8f8, 0xffffffff, 1,
  256. 0x8fc, 0x0e000000, 0
  257. };
  258. static const u32 dvst_golden_registers[] =
  259. {
  260. 0x690, 0x3fff3fff, 0x20c00033,
  261. 0x918c, 0x0fff0fff, 0x00010006,
  262. 0x91a8, 0x0fff0fff, 0x00010006,
  263. 0x9150, 0xffffdfff, 0x6e944040,
  264. 0x917c, 0x0fff0fff, 0x00030002,
  265. 0x9198, 0x0fff0fff, 0x00030002,
  266. 0x915c, 0x0fff0fff, 0x00010000,
  267. 0x3f90, 0xffff0001, 0xff000000,
  268. 0x9178, 0x0fff0fff, 0x00070000,
  269. 0x9194, 0x0fff0fff, 0x00070000,
  270. 0x9148, 0xffff0001, 0xff000000,
  271. 0x9190, 0x0fff0fff, 0x00090008,
  272. 0x91ac, 0x0fff0fff, 0x00090008,
  273. 0x3f94, 0xffff0000, 0xff000000,
  274. 0x914c, 0xffff0000, 0xff000000,
  275. 0x929c, 0x00000fff, 0x00000001,
  276. 0x55e4, 0xff607fff, 0xfc000100,
  277. 0x8a18, 0xff000fff, 0x00000100,
  278. 0x8b28, 0xff000fff, 0x00000100,
  279. 0x9144, 0xfffc0fff, 0x00000100,
  280. 0x6ed8, 0x00010101, 0x00010000,
  281. 0x9830, 0xffffffff, 0x00000000,
  282. 0x9834, 0xf00fffff, 0x00000400,
  283. 0x9838, 0xfffffffe, 0x00000000,
  284. 0xd0c0, 0xff000fff, 0x00000100,
  285. 0xd02c, 0xbfffff1f, 0x08421000,
  286. 0xd0b8, 0x73773777, 0x12010001,
  287. 0x5bb0, 0x000000f0, 0x00000070,
  288. 0x98f8, 0x73773777, 0x12010001,
  289. 0x98fc, 0xffffffff, 0x00000010,
  290. 0x9b7c, 0x00ff0000, 0x00fc0000,
  291. 0x8030, 0x00001f0f, 0x0000100a,
  292. 0x2f48, 0x73773777, 0x12010001,
  293. 0x2408, 0x00030000, 0x000c007f,
  294. 0x8a14, 0xf000003f, 0x00000007,
  295. 0x8b24, 0x3fff3fff, 0x00ff0fff,
  296. 0x8b10, 0x0000ff0f, 0x00000000,
  297. 0x28a4c, 0x07ffffff, 0x06000000,
  298. 0x4d8, 0x00000fff, 0x00000100,
  299. 0xa008, 0xffffffff, 0x00010000,
  300. 0x913c, 0xffff03ff, 0x01000100,
  301. 0x8c00, 0x000000ff, 0x00000003,
  302. 0x8c04, 0xf8ff00ff, 0x40600060,
  303. 0x8cf0, 0x1fff1fff, 0x08e00410,
  304. 0x28350, 0x00000f01, 0x00000000,
  305. 0x9508, 0xf700071f, 0x00000002,
  306. 0x960c, 0xffffffff, 0x54763210,
  307. 0x20ef8, 0x01ff01ff, 0x00000002,
  308. 0x20e98, 0xfffffbff, 0x00200000,
  309. 0x2015c, 0xffffffff, 0x00000f40,
  310. 0x88c4, 0x001f3ae3, 0x00000082,
  311. 0x8978, 0x3fffffff, 0x04050140,
  312. 0x88d4, 0x0000001f, 0x00000010,
  313. 0x8974, 0xffffffff, 0x00000000
  314. };
  315. static const u32 scrapper_golden_registers[] =
  316. {
  317. 0x690, 0x3fff3fff, 0x20c00033,
  318. 0x918c, 0x0fff0fff, 0x00010006,
  319. 0x918c, 0x0fff0fff, 0x00010006,
  320. 0x91a8, 0x0fff0fff, 0x00010006,
  321. 0x91a8, 0x0fff0fff, 0x00010006,
  322. 0x9150, 0xffffdfff, 0x6e944040,
  323. 0x9150, 0xffffdfff, 0x6e944040,
  324. 0x917c, 0x0fff0fff, 0x00030002,
  325. 0x917c, 0x0fff0fff, 0x00030002,
  326. 0x9198, 0x0fff0fff, 0x00030002,
  327. 0x9198, 0x0fff0fff, 0x00030002,
  328. 0x915c, 0x0fff0fff, 0x00010000,
  329. 0x915c, 0x0fff0fff, 0x00010000,
  330. 0x3f90, 0xffff0001, 0xff000000,
  331. 0x3f90, 0xffff0001, 0xff000000,
  332. 0x9178, 0x0fff0fff, 0x00070000,
  333. 0x9178, 0x0fff0fff, 0x00070000,
  334. 0x9194, 0x0fff0fff, 0x00070000,
  335. 0x9194, 0x0fff0fff, 0x00070000,
  336. 0x9148, 0xffff0001, 0xff000000,
  337. 0x9148, 0xffff0001, 0xff000000,
  338. 0x9190, 0x0fff0fff, 0x00090008,
  339. 0x9190, 0x0fff0fff, 0x00090008,
  340. 0x91ac, 0x0fff0fff, 0x00090008,
  341. 0x91ac, 0x0fff0fff, 0x00090008,
  342. 0x3f94, 0xffff0000, 0xff000000,
  343. 0x3f94, 0xffff0000, 0xff000000,
  344. 0x914c, 0xffff0000, 0xff000000,
  345. 0x914c, 0xffff0000, 0xff000000,
  346. 0x929c, 0x00000fff, 0x00000001,
  347. 0x929c, 0x00000fff, 0x00000001,
  348. 0x55e4, 0xff607fff, 0xfc000100,
  349. 0x8a18, 0xff000fff, 0x00000100,
  350. 0x8a18, 0xff000fff, 0x00000100,
  351. 0x8b28, 0xff000fff, 0x00000100,
  352. 0x8b28, 0xff000fff, 0x00000100,
  353. 0x9144, 0xfffc0fff, 0x00000100,
  354. 0x9144, 0xfffc0fff, 0x00000100,
  355. 0x6ed8, 0x00010101, 0x00010000,
  356. 0x9830, 0xffffffff, 0x00000000,
  357. 0x9830, 0xffffffff, 0x00000000,
  358. 0x9834, 0xf00fffff, 0x00000400,
  359. 0x9834, 0xf00fffff, 0x00000400,
  360. 0x9838, 0xfffffffe, 0x00000000,
  361. 0x9838, 0xfffffffe, 0x00000000,
  362. 0xd0c0, 0xff000fff, 0x00000100,
  363. 0xd02c, 0xbfffff1f, 0x08421000,
  364. 0xd02c, 0xbfffff1f, 0x08421000,
  365. 0xd0b8, 0x73773777, 0x12010001,
  366. 0xd0b8, 0x73773777, 0x12010001,
  367. 0x5bb0, 0x000000f0, 0x00000070,
  368. 0x98f8, 0x73773777, 0x12010001,
  369. 0x98f8, 0x73773777, 0x12010001,
  370. 0x98fc, 0xffffffff, 0x00000010,
  371. 0x98fc, 0xffffffff, 0x00000010,
  372. 0x9b7c, 0x00ff0000, 0x00fc0000,
  373. 0x9b7c, 0x00ff0000, 0x00fc0000,
  374. 0x8030, 0x00001f0f, 0x0000100a,
  375. 0x8030, 0x00001f0f, 0x0000100a,
  376. 0x2f48, 0x73773777, 0x12010001,
  377. 0x2f48, 0x73773777, 0x12010001,
  378. 0x2408, 0x00030000, 0x000c007f,
  379. 0x8a14, 0xf000003f, 0x00000007,
  380. 0x8a14, 0xf000003f, 0x00000007,
  381. 0x8b24, 0x3fff3fff, 0x00ff0fff,
  382. 0x8b24, 0x3fff3fff, 0x00ff0fff,
  383. 0x8b10, 0x0000ff0f, 0x00000000,
  384. 0x8b10, 0x0000ff0f, 0x00000000,
  385. 0x28a4c, 0x07ffffff, 0x06000000,
  386. 0x28a4c, 0x07ffffff, 0x06000000,
  387. 0x4d8, 0x00000fff, 0x00000100,
  388. 0x4d8, 0x00000fff, 0x00000100,
  389. 0xa008, 0xffffffff, 0x00010000,
  390. 0xa008, 0xffffffff, 0x00010000,
  391. 0x913c, 0xffff03ff, 0x01000100,
  392. 0x913c, 0xffff03ff, 0x01000100,
  393. 0x90e8, 0x001fffff, 0x010400c0,
  394. 0x8c00, 0x000000ff, 0x00000003,
  395. 0x8c00, 0x000000ff, 0x00000003,
  396. 0x8c04, 0xf8ff00ff, 0x40600060,
  397. 0x8c04, 0xf8ff00ff, 0x40600060,
  398. 0x8c30, 0x0000000f, 0x00040005,
  399. 0x8cf0, 0x1fff1fff, 0x08e00410,
  400. 0x8cf0, 0x1fff1fff, 0x08e00410,
  401. 0x900c, 0x00ffffff, 0x0017071f,
  402. 0x28350, 0x00000f01, 0x00000000,
  403. 0x28350, 0x00000f01, 0x00000000,
  404. 0x9508, 0xf700071f, 0x00000002,
  405. 0x9508, 0xf700071f, 0x00000002,
  406. 0x9688, 0x00300000, 0x0017000f,
  407. 0x960c, 0xffffffff, 0x54763210,
  408. 0x960c, 0xffffffff, 0x54763210,
  409. 0x20ef8, 0x01ff01ff, 0x00000002,
  410. 0x20e98, 0xfffffbff, 0x00200000,
  411. 0x2015c, 0xffffffff, 0x00000f40,
  412. 0x88c4, 0x001f3ae3, 0x00000082,
  413. 0x88c4, 0x001f3ae3, 0x00000082,
  414. 0x8978, 0x3fffffff, 0x04050140,
  415. 0x8978, 0x3fffffff, 0x04050140,
  416. 0x88d4, 0x0000001f, 0x00000010,
  417. 0x88d4, 0x0000001f, 0x00000010,
  418. 0x8974, 0xffffffff, 0x00000000,
  419. 0x8974, 0xffffffff, 0x00000000
  420. };
  421. static void ni_init_golden_registers(struct radeon_device *rdev)
  422. {
  423. switch (rdev->family) {
  424. case CHIP_CAYMAN:
  425. radeon_program_register_sequence(rdev,
  426. cayman_golden_registers,
  427. (const u32)ARRAY_SIZE(cayman_golden_registers));
  428. radeon_program_register_sequence(rdev,
  429. cayman_golden_registers2,
  430. (const u32)ARRAY_SIZE(cayman_golden_registers2));
  431. break;
  432. case CHIP_ARUBA:
  433. if ((rdev->pdev->device == 0x9900) ||
  434. (rdev->pdev->device == 0x9901) ||
  435. (rdev->pdev->device == 0x9903) ||
  436. (rdev->pdev->device == 0x9904) ||
  437. (rdev->pdev->device == 0x9905) ||
  438. (rdev->pdev->device == 0x9906) ||
  439. (rdev->pdev->device == 0x9907) ||
  440. (rdev->pdev->device == 0x9908) ||
  441. (rdev->pdev->device == 0x9909) ||
  442. (rdev->pdev->device == 0x990A) ||
  443. (rdev->pdev->device == 0x990B) ||
  444. (rdev->pdev->device == 0x990C) ||
  445. (rdev->pdev->device == 0x990D) ||
  446. (rdev->pdev->device == 0x990E) ||
  447. (rdev->pdev->device == 0x990F) ||
  448. (rdev->pdev->device == 0x9910) ||
  449. (rdev->pdev->device == 0x9913) ||
  450. (rdev->pdev->device == 0x9917) ||
  451. (rdev->pdev->device == 0x9918)) {
  452. radeon_program_register_sequence(rdev,
  453. dvst_golden_registers,
  454. (const u32)ARRAY_SIZE(dvst_golden_registers));
  455. radeon_program_register_sequence(rdev,
  456. dvst_golden_registers2,
  457. (const u32)ARRAY_SIZE(dvst_golden_registers2));
  458. } else {
  459. radeon_program_register_sequence(rdev,
  460. scrapper_golden_registers,
  461. (const u32)ARRAY_SIZE(scrapper_golden_registers));
  462. radeon_program_register_sequence(rdev,
  463. dvst_golden_registers2,
  464. (const u32)ARRAY_SIZE(dvst_golden_registers2));
  465. }
  466. break;
  467. default:
  468. break;
  469. }
  470. }
  471. #define BTC_IO_MC_REGS_SIZE 29
  472. static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  473. {0x00000077, 0xff010100},
  474. {0x00000078, 0x00000000},
  475. {0x00000079, 0x00001434},
  476. {0x0000007a, 0xcc08ec08},
  477. {0x0000007b, 0x00040000},
  478. {0x0000007c, 0x000080c0},
  479. {0x0000007d, 0x09000000},
  480. {0x0000007e, 0x00210404},
  481. {0x00000081, 0x08a8e800},
  482. {0x00000082, 0x00030444},
  483. {0x00000083, 0x00000000},
  484. {0x00000085, 0x00000001},
  485. {0x00000086, 0x00000002},
  486. {0x00000087, 0x48490000},
  487. {0x00000088, 0x20244647},
  488. {0x00000089, 0x00000005},
  489. {0x0000008b, 0x66030000},
  490. {0x0000008c, 0x00006603},
  491. {0x0000008d, 0x00000100},
  492. {0x0000008f, 0x00001c0a},
  493. {0x00000090, 0xff000001},
  494. {0x00000094, 0x00101101},
  495. {0x00000095, 0x00000fff},
  496. {0x00000096, 0x00116fff},
  497. {0x00000097, 0x60010000},
  498. {0x00000098, 0x10010000},
  499. {0x00000099, 0x00006000},
  500. {0x0000009a, 0x00001000},
  501. {0x0000009f, 0x00946a00}
  502. };
  503. static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  504. {0x00000077, 0xff010100},
  505. {0x00000078, 0x00000000},
  506. {0x00000079, 0x00001434},
  507. {0x0000007a, 0xcc08ec08},
  508. {0x0000007b, 0x00040000},
  509. {0x0000007c, 0x000080c0},
  510. {0x0000007d, 0x09000000},
  511. {0x0000007e, 0x00210404},
  512. {0x00000081, 0x08a8e800},
  513. {0x00000082, 0x00030444},
  514. {0x00000083, 0x00000000},
  515. {0x00000085, 0x00000001},
  516. {0x00000086, 0x00000002},
  517. {0x00000087, 0x48490000},
  518. {0x00000088, 0x20244647},
  519. {0x00000089, 0x00000005},
  520. {0x0000008b, 0x66030000},
  521. {0x0000008c, 0x00006603},
  522. {0x0000008d, 0x00000100},
  523. {0x0000008f, 0x00001c0a},
  524. {0x00000090, 0xff000001},
  525. {0x00000094, 0x00101101},
  526. {0x00000095, 0x00000fff},
  527. {0x00000096, 0x00116fff},
  528. {0x00000097, 0x60010000},
  529. {0x00000098, 0x10010000},
  530. {0x00000099, 0x00006000},
  531. {0x0000009a, 0x00001000},
  532. {0x0000009f, 0x00936a00}
  533. };
  534. static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  535. {0x00000077, 0xff010100},
  536. {0x00000078, 0x00000000},
  537. {0x00000079, 0x00001434},
  538. {0x0000007a, 0xcc08ec08},
  539. {0x0000007b, 0x00040000},
  540. {0x0000007c, 0x000080c0},
  541. {0x0000007d, 0x09000000},
  542. {0x0000007e, 0x00210404},
  543. {0x00000081, 0x08a8e800},
  544. {0x00000082, 0x00030444},
  545. {0x00000083, 0x00000000},
  546. {0x00000085, 0x00000001},
  547. {0x00000086, 0x00000002},
  548. {0x00000087, 0x48490000},
  549. {0x00000088, 0x20244647},
  550. {0x00000089, 0x00000005},
  551. {0x0000008b, 0x66030000},
  552. {0x0000008c, 0x00006603},
  553. {0x0000008d, 0x00000100},
  554. {0x0000008f, 0x00001c0a},
  555. {0x00000090, 0xff000001},
  556. {0x00000094, 0x00101101},
  557. {0x00000095, 0x00000fff},
  558. {0x00000096, 0x00116fff},
  559. {0x00000097, 0x60010000},
  560. {0x00000098, 0x10010000},
  561. {0x00000099, 0x00006000},
  562. {0x0000009a, 0x00001000},
  563. {0x0000009f, 0x00916a00}
  564. };
  565. static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  566. {0x00000077, 0xff010100},
  567. {0x00000078, 0x00000000},
  568. {0x00000079, 0x00001434},
  569. {0x0000007a, 0xcc08ec08},
  570. {0x0000007b, 0x00040000},
  571. {0x0000007c, 0x000080c0},
  572. {0x0000007d, 0x09000000},
  573. {0x0000007e, 0x00210404},
  574. {0x00000081, 0x08a8e800},
  575. {0x00000082, 0x00030444},
  576. {0x00000083, 0x00000000},
  577. {0x00000085, 0x00000001},
  578. {0x00000086, 0x00000002},
  579. {0x00000087, 0x48490000},
  580. {0x00000088, 0x20244647},
  581. {0x00000089, 0x00000005},
  582. {0x0000008b, 0x66030000},
  583. {0x0000008c, 0x00006603},
  584. {0x0000008d, 0x00000100},
  585. {0x0000008f, 0x00001c0a},
  586. {0x00000090, 0xff000001},
  587. {0x00000094, 0x00101101},
  588. {0x00000095, 0x00000fff},
  589. {0x00000096, 0x00116fff},
  590. {0x00000097, 0x60010000},
  591. {0x00000098, 0x10010000},
  592. {0x00000099, 0x00006000},
  593. {0x0000009a, 0x00001000},
  594. {0x0000009f, 0x00976b00}
  595. };
  596. int ni_mc_load_microcode(struct radeon_device *rdev)
  597. {
  598. const __be32 *fw_data;
  599. u32 mem_type, running, blackout = 0;
  600. u32 *io_mc_regs;
  601. int i, ucode_size, regs_size;
  602. if (!rdev->mc_fw)
  603. return -EINVAL;
  604. switch (rdev->family) {
  605. case CHIP_BARTS:
  606. io_mc_regs = (u32 *)&barts_io_mc_regs;
  607. ucode_size = BTC_MC_UCODE_SIZE;
  608. regs_size = BTC_IO_MC_REGS_SIZE;
  609. break;
  610. case CHIP_TURKS:
  611. io_mc_regs = (u32 *)&turks_io_mc_regs;
  612. ucode_size = BTC_MC_UCODE_SIZE;
  613. regs_size = BTC_IO_MC_REGS_SIZE;
  614. break;
  615. case CHIP_CAICOS:
  616. default:
  617. io_mc_regs = (u32 *)&caicos_io_mc_regs;
  618. ucode_size = BTC_MC_UCODE_SIZE;
  619. regs_size = BTC_IO_MC_REGS_SIZE;
  620. break;
  621. case CHIP_CAYMAN:
  622. io_mc_regs = (u32 *)&cayman_io_mc_regs;
  623. ucode_size = CAYMAN_MC_UCODE_SIZE;
  624. regs_size = BTC_IO_MC_REGS_SIZE;
  625. break;
  626. }
  627. mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
  628. running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
  629. if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
  630. if (running) {
  631. blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
  632. WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
  633. }
  634. /* reset the engine and set to writable */
  635. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  636. WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
  637. /* load mc io regs */
  638. for (i = 0; i < regs_size; i++) {
  639. WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
  640. WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
  641. }
  642. /* load the MC ucode */
  643. fw_data = (const __be32 *)rdev->mc_fw->data;
  644. for (i = 0; i < ucode_size; i++)
  645. WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
  646. /* put the engine back into the active state */
  647. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  648. WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
  649. WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
  650. /* wait for training to complete */
  651. for (i = 0; i < rdev->usec_timeout; i++) {
  652. if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
  653. break;
  654. udelay(1);
  655. }
  656. if (running)
  657. WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
  658. }
  659. return 0;
  660. }
  661. int ni_init_microcode(struct radeon_device *rdev)
  662. {
  663. const char *chip_name;
  664. const char *rlc_chip_name;
  665. size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
  666. size_t smc_req_size = 0;
  667. char fw_name[30];
  668. int err;
  669. DRM_DEBUG("\n");
  670. switch (rdev->family) {
  671. case CHIP_BARTS:
  672. chip_name = "BARTS";
  673. rlc_chip_name = "BTC";
  674. pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
  675. me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
  676. rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
  677. mc_req_size = BTC_MC_UCODE_SIZE * 4;
  678. smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
  679. break;
  680. case CHIP_TURKS:
  681. chip_name = "TURKS";
  682. rlc_chip_name = "BTC";
  683. pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
  684. me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
  685. rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
  686. mc_req_size = BTC_MC_UCODE_SIZE * 4;
  687. smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
  688. break;
  689. case CHIP_CAICOS:
  690. chip_name = "CAICOS";
  691. rlc_chip_name = "BTC";
  692. pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
  693. me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
  694. rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
  695. mc_req_size = BTC_MC_UCODE_SIZE * 4;
  696. smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
  697. break;
  698. case CHIP_CAYMAN:
  699. chip_name = "CAYMAN";
  700. rlc_chip_name = "CAYMAN";
  701. pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
  702. me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
  703. rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
  704. mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
  705. smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
  706. break;
  707. case CHIP_ARUBA:
  708. chip_name = "ARUBA";
  709. rlc_chip_name = "ARUBA";
  710. /* pfp/me same size as CAYMAN */
  711. pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
  712. me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
  713. rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
  714. mc_req_size = 0;
  715. break;
  716. default: BUG();
  717. }
  718. DRM_INFO("Loading %s Microcode\n", chip_name);
  719. snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
  720. err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
  721. if (err)
  722. goto out;
  723. if (rdev->pfp_fw->size != pfp_req_size) {
  724. printk(KERN_ERR
  725. "ni_cp: Bogus length %zu in firmware \"%s\"\n",
  726. rdev->pfp_fw->size, fw_name);
  727. err = -EINVAL;
  728. goto out;
  729. }
  730. snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
  731. err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
  732. if (err)
  733. goto out;
  734. if (rdev->me_fw->size != me_req_size) {
  735. printk(KERN_ERR
  736. "ni_cp: Bogus length %zu in firmware \"%s\"\n",
  737. rdev->me_fw->size, fw_name);
  738. err = -EINVAL;
  739. }
  740. snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
  741. err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
  742. if (err)
  743. goto out;
  744. if (rdev->rlc_fw->size != rlc_req_size) {
  745. printk(KERN_ERR
  746. "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
  747. rdev->rlc_fw->size, fw_name);
  748. err = -EINVAL;
  749. }
  750. /* no MC ucode on TN */
  751. if (!(rdev->flags & RADEON_IS_IGP)) {
  752. snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
  753. err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
  754. if (err)
  755. goto out;
  756. if (rdev->mc_fw->size != mc_req_size) {
  757. printk(KERN_ERR
  758. "ni_mc: Bogus length %zu in firmware \"%s\"\n",
  759. rdev->mc_fw->size, fw_name);
  760. err = -EINVAL;
  761. }
  762. }
  763. if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
  764. snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
  765. err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
  766. if (err) {
  767. printk(KERN_ERR
  768. "smc: error loading firmware \"%s\"\n",
  769. fw_name);
  770. release_firmware(rdev->smc_fw);
  771. rdev->smc_fw = NULL;
  772. } else if (rdev->smc_fw->size != smc_req_size) {
  773. printk(KERN_ERR
  774. "ni_mc: Bogus length %zu in firmware \"%s\"\n",
  775. rdev->mc_fw->size, fw_name);
  776. err = -EINVAL;
  777. }
  778. }
  779. out:
  780. if (err) {
  781. if (err != -EINVAL)
  782. printk(KERN_ERR
  783. "ni_cp: Failed to load firmware \"%s\"\n",
  784. fw_name);
  785. release_firmware(rdev->pfp_fw);
  786. rdev->pfp_fw = NULL;
  787. release_firmware(rdev->me_fw);
  788. rdev->me_fw = NULL;
  789. release_firmware(rdev->rlc_fw);
  790. rdev->rlc_fw = NULL;
  791. release_firmware(rdev->mc_fw);
  792. rdev->mc_fw = NULL;
  793. }
  794. return err;
  795. }
  796. int tn_get_temp(struct radeon_device *rdev)
  797. {
  798. u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
  799. int actual_temp = (temp / 8) - 49;
  800. return actual_temp * 1000;
  801. }
  802. /*
  803. * Core functions
  804. */
  805. static void cayman_gpu_init(struct radeon_device *rdev)
  806. {
  807. u32 gb_addr_config = 0;
  808. u32 mc_shared_chmap, mc_arb_ramcfg;
  809. u32 cgts_tcc_disable;
  810. u32 sx_debug_1;
  811. u32 smx_dc_ctl0;
  812. u32 cgts_sm_ctrl_reg;
  813. u32 hdp_host_path_cntl;
  814. u32 tmp;
  815. u32 disabled_rb_mask;
  816. int i, j;
  817. switch (rdev->family) {
  818. case CHIP_CAYMAN:
  819. rdev->config.cayman.max_shader_engines = 2;
  820. rdev->config.cayman.max_pipes_per_simd = 4;
  821. rdev->config.cayman.max_tile_pipes = 8;
  822. rdev->config.cayman.max_simds_per_se = 12;
  823. rdev->config.cayman.max_backends_per_se = 4;
  824. rdev->config.cayman.max_texture_channel_caches = 8;
  825. rdev->config.cayman.max_gprs = 256;
  826. rdev->config.cayman.max_threads = 256;
  827. rdev->config.cayman.max_gs_threads = 32;
  828. rdev->config.cayman.max_stack_entries = 512;
  829. rdev->config.cayman.sx_num_of_sets = 8;
  830. rdev->config.cayman.sx_max_export_size = 256;
  831. rdev->config.cayman.sx_max_export_pos_size = 64;
  832. rdev->config.cayman.sx_max_export_smx_size = 192;
  833. rdev->config.cayman.max_hw_contexts = 8;
  834. rdev->config.cayman.sq_num_cf_insts = 2;
  835. rdev->config.cayman.sc_prim_fifo_size = 0x100;
  836. rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
  837. rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
  838. gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
  839. break;
  840. case CHIP_ARUBA:
  841. default:
  842. rdev->config.cayman.max_shader_engines = 1;
  843. rdev->config.cayman.max_pipes_per_simd = 4;
  844. rdev->config.cayman.max_tile_pipes = 2;
  845. if ((rdev->pdev->device == 0x9900) ||
  846. (rdev->pdev->device == 0x9901) ||
  847. (rdev->pdev->device == 0x9905) ||
  848. (rdev->pdev->device == 0x9906) ||
  849. (rdev->pdev->device == 0x9907) ||
  850. (rdev->pdev->device == 0x9908) ||
  851. (rdev->pdev->device == 0x9909) ||
  852. (rdev->pdev->device == 0x990B) ||
  853. (rdev->pdev->device == 0x990C) ||
  854. (rdev->pdev->device == 0x990F) ||
  855. (rdev->pdev->device == 0x9910) ||
  856. (rdev->pdev->device == 0x9917) ||
  857. (rdev->pdev->device == 0x9999) ||
  858. (rdev->pdev->device == 0x999C)) {
  859. rdev->config.cayman.max_simds_per_se = 6;
  860. rdev->config.cayman.max_backends_per_se = 2;
  861. } else if ((rdev->pdev->device == 0x9903) ||
  862. (rdev->pdev->device == 0x9904) ||
  863. (rdev->pdev->device == 0x990A) ||
  864. (rdev->pdev->device == 0x990D) ||
  865. (rdev->pdev->device == 0x990E) ||
  866. (rdev->pdev->device == 0x9913) ||
  867. (rdev->pdev->device == 0x9918) ||
  868. (rdev->pdev->device == 0x999D)) {
  869. rdev->config.cayman.max_simds_per_se = 4;
  870. rdev->config.cayman.max_backends_per_se = 2;
  871. } else if ((rdev->pdev->device == 0x9919) ||
  872. (rdev->pdev->device == 0x9990) ||
  873. (rdev->pdev->device == 0x9991) ||
  874. (rdev->pdev->device == 0x9994) ||
  875. (rdev->pdev->device == 0x9995) ||
  876. (rdev->pdev->device == 0x9996) ||
  877. (rdev->pdev->device == 0x999A) ||
  878. (rdev->pdev->device == 0x99A0)) {
  879. rdev->config.cayman.max_simds_per_se = 3;
  880. rdev->config.cayman.max_backends_per_se = 1;
  881. } else {
  882. rdev->config.cayman.max_simds_per_se = 2;
  883. rdev->config.cayman.max_backends_per_se = 1;
  884. }
  885. rdev->config.cayman.max_texture_channel_caches = 2;
  886. rdev->config.cayman.max_gprs = 256;
  887. rdev->config.cayman.max_threads = 256;
  888. rdev->config.cayman.max_gs_threads = 32;
  889. rdev->config.cayman.max_stack_entries = 512;
  890. rdev->config.cayman.sx_num_of_sets = 8;
  891. rdev->config.cayman.sx_max_export_size = 256;
  892. rdev->config.cayman.sx_max_export_pos_size = 64;
  893. rdev->config.cayman.sx_max_export_smx_size = 192;
  894. rdev->config.cayman.max_hw_contexts = 8;
  895. rdev->config.cayman.sq_num_cf_insts = 2;
  896. rdev->config.cayman.sc_prim_fifo_size = 0x40;
  897. rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
  898. rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
  899. gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
  900. break;
  901. }
  902. /* Initialize HDP */
  903. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  904. WREG32((0x2c14 + j), 0x00000000);
  905. WREG32((0x2c18 + j), 0x00000000);
  906. WREG32((0x2c1c + j), 0x00000000);
  907. WREG32((0x2c20 + j), 0x00000000);
  908. WREG32((0x2c24 + j), 0x00000000);
  909. }
  910. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  911. evergreen_fix_pci_max_read_req_size(rdev);
  912. mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
  913. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  914. tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
  915. rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
  916. if (rdev->config.cayman.mem_row_size_in_kb > 4)
  917. rdev->config.cayman.mem_row_size_in_kb = 4;
  918. /* XXX use MC settings? */
  919. rdev->config.cayman.shader_engine_tile_size = 32;
  920. rdev->config.cayman.num_gpus = 1;
  921. rdev->config.cayman.multi_gpu_tile_size = 64;
  922. tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
  923. rdev->config.cayman.num_tile_pipes = (1 << tmp);
  924. tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
  925. rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
  926. tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
  927. rdev->config.cayman.num_shader_engines = tmp + 1;
  928. tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
  929. rdev->config.cayman.num_gpus = tmp + 1;
  930. tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
  931. rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
  932. tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
  933. rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
  934. /* setup tiling info dword. gb_addr_config is not adequate since it does
  935. * not have bank info, so create a custom tiling dword.
  936. * bits 3:0 num_pipes
  937. * bits 7:4 num_banks
  938. * bits 11:8 group_size
  939. * bits 15:12 row_size
  940. */
  941. rdev->config.cayman.tile_config = 0;
  942. switch (rdev->config.cayman.num_tile_pipes) {
  943. case 1:
  944. default:
  945. rdev->config.cayman.tile_config |= (0 << 0);
  946. break;
  947. case 2:
  948. rdev->config.cayman.tile_config |= (1 << 0);
  949. break;
  950. case 4:
  951. rdev->config.cayman.tile_config |= (2 << 0);
  952. break;
  953. case 8:
  954. rdev->config.cayman.tile_config |= (3 << 0);
  955. break;
  956. }
  957. /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
  958. if (rdev->flags & RADEON_IS_IGP)
  959. rdev->config.cayman.tile_config |= 1 << 4;
  960. else {
  961. switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
  962. case 0: /* four banks */
  963. rdev->config.cayman.tile_config |= 0 << 4;
  964. break;
  965. case 1: /* eight banks */
  966. rdev->config.cayman.tile_config |= 1 << 4;
  967. break;
  968. case 2: /* sixteen banks */
  969. default:
  970. rdev->config.cayman.tile_config |= 2 << 4;
  971. break;
  972. }
  973. }
  974. rdev->config.cayman.tile_config |=
  975. ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
  976. rdev->config.cayman.tile_config |=
  977. ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
  978. tmp = 0;
  979. for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
  980. u32 rb_disable_bitmap;
  981. WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
  982. WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
  983. rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
  984. tmp <<= 4;
  985. tmp |= rb_disable_bitmap;
  986. }
  987. /* enabled rb are just the one not disabled :) */
  988. disabled_rb_mask = tmp;
  989. tmp = 0;
  990. for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
  991. tmp |= (1 << i);
  992. /* if all the backends are disabled, fix it up here */
  993. if ((disabled_rb_mask & tmp) == tmp) {
  994. for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
  995. disabled_rb_mask &= ~(1 << i);
  996. }
  997. WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
  998. WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
  999. WREG32(GB_ADDR_CONFIG, gb_addr_config);
  1000. WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
  1001. if (ASIC_IS_DCE6(rdev))
  1002. WREG32(DMIF_ADDR_CALC, gb_addr_config);
  1003. WREG32(HDP_ADDR_CONFIG, gb_addr_config);
  1004. WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
  1005. WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
  1006. WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
  1007. WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
  1008. WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
  1009. if ((rdev->config.cayman.max_backends_per_se == 1) &&
  1010. (rdev->flags & RADEON_IS_IGP)) {
  1011. if ((disabled_rb_mask & 3) == 1) {
  1012. /* RB0 disabled, RB1 enabled */
  1013. tmp = 0x11111111;
  1014. } else {
  1015. /* RB1 disabled, RB0 enabled */
  1016. tmp = 0x00000000;
  1017. }
  1018. } else {
  1019. tmp = gb_addr_config & NUM_PIPES_MASK;
  1020. tmp = r6xx_remap_render_backend(rdev, tmp,
  1021. rdev->config.cayman.max_backends_per_se *
  1022. rdev->config.cayman.max_shader_engines,
  1023. CAYMAN_MAX_BACKENDS, disabled_rb_mask);
  1024. }
  1025. WREG32(GB_BACKEND_MAP, tmp);
  1026. cgts_tcc_disable = 0xffff0000;
  1027. for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
  1028. cgts_tcc_disable &= ~(1 << (16 + i));
  1029. WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
  1030. WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
  1031. WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
  1032. WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
  1033. /* reprogram the shader complex */
  1034. cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
  1035. for (i = 0; i < 16; i++)
  1036. WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
  1037. WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
  1038. /* set HW defaults for 3D engine */
  1039. WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
  1040. sx_debug_1 = RREG32(SX_DEBUG_1);
  1041. sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
  1042. WREG32(SX_DEBUG_1, sx_debug_1);
  1043. smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
  1044. smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
  1045. smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
  1046. WREG32(SMX_DC_CTL0, smx_dc_ctl0);
  1047. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
  1048. /* need to be explicitly zero-ed */
  1049. WREG32(VGT_OFFCHIP_LDS_BASE, 0);
  1050. WREG32(SQ_LSTMP_RING_BASE, 0);
  1051. WREG32(SQ_HSTMP_RING_BASE, 0);
  1052. WREG32(SQ_ESTMP_RING_BASE, 0);
  1053. WREG32(SQ_GSTMP_RING_BASE, 0);
  1054. WREG32(SQ_VSTMP_RING_BASE, 0);
  1055. WREG32(SQ_PSTMP_RING_BASE, 0);
  1056. WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
  1057. WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
  1058. POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
  1059. SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
  1060. WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
  1061. SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
  1062. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
  1063. WREG32(VGT_NUM_INSTANCES, 1);
  1064. WREG32(CP_PERFMON_CNTL, 0);
  1065. WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
  1066. FETCH_FIFO_HIWATER(0x4) |
  1067. DONE_FIFO_HIWATER(0xe0) |
  1068. ALU_UPDATE_FIFO_HIWATER(0x8)));
  1069. WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
  1070. WREG32(SQ_CONFIG, (VC_ENABLE |
  1071. EXPORT_SRC_C |
  1072. GFX_PRIO(0) |
  1073. CS1_PRIO(0) |
  1074. CS2_PRIO(1)));
  1075. WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
  1076. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  1077. FORCE_EOV_MAX_REZ_CNT(255)));
  1078. WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
  1079. AUTO_INVLD_EN(ES_AND_GS_AUTO));
  1080. WREG32(VGT_GS_VERTEX_REUSE, 16);
  1081. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  1082. WREG32(CB_PERF_CTR0_SEL_0, 0);
  1083. WREG32(CB_PERF_CTR0_SEL_1, 0);
  1084. WREG32(CB_PERF_CTR1_SEL_0, 0);
  1085. WREG32(CB_PERF_CTR1_SEL_1, 0);
  1086. WREG32(CB_PERF_CTR2_SEL_0, 0);
  1087. WREG32(CB_PERF_CTR2_SEL_1, 0);
  1088. WREG32(CB_PERF_CTR3_SEL_0, 0);
  1089. WREG32(CB_PERF_CTR3_SEL_1, 0);
  1090. tmp = RREG32(HDP_MISC_CNTL);
  1091. tmp |= HDP_FLUSH_INVALIDATE_CACHE;
  1092. WREG32(HDP_MISC_CNTL, tmp);
  1093. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  1094. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  1095. WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
  1096. udelay(50);
  1097. /* set clockgating golden values on TN */
  1098. if (rdev->family == CHIP_ARUBA) {
  1099. tmp = RREG32_CG(CG_CGTT_LOCAL_0);
  1100. tmp &= ~0x00380000;
  1101. WREG32_CG(CG_CGTT_LOCAL_0, tmp);
  1102. tmp = RREG32_CG(CG_CGTT_LOCAL_1);
  1103. tmp &= ~0x0e000000;
  1104. WREG32_CG(CG_CGTT_LOCAL_1, tmp);
  1105. }
  1106. }
  1107. /*
  1108. * GART
  1109. */
  1110. void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
  1111. {
  1112. /* flush hdp cache */
  1113. WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  1114. /* bits 0-7 are the VM contexts0-7 */
  1115. WREG32(VM_INVALIDATE_REQUEST, 1);
  1116. }
  1117. static int cayman_pcie_gart_enable(struct radeon_device *rdev)
  1118. {
  1119. int i, r;
  1120. if (rdev->gart.robj == NULL) {
  1121. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  1122. return -EINVAL;
  1123. }
  1124. r = radeon_gart_table_vram_pin(rdev);
  1125. if (r)
  1126. return r;
  1127. radeon_gart_restore(rdev);
  1128. /* Setup TLB control */
  1129. WREG32(MC_VM_MX_L1_TLB_CNTL,
  1130. (0xA << 7) |
  1131. ENABLE_L1_TLB |
  1132. ENABLE_L1_FRAGMENT_PROCESSING |
  1133. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  1134. ENABLE_ADVANCED_DRIVER_MODEL |
  1135. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  1136. /* Setup L2 cache */
  1137. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
  1138. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  1139. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  1140. EFFECTIVE_L2_QUEUE_SIZE(7) |
  1141. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  1142. WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
  1143. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  1144. L2_CACHE_BIGK_FRAGMENT_SIZE(6));
  1145. /* setup context0 */
  1146. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  1147. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  1148. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  1149. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  1150. (u32)(rdev->dummy_page.addr >> 12));
  1151. WREG32(VM_CONTEXT0_CNTL2, 0);
  1152. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  1153. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  1154. WREG32(0x15D4, 0);
  1155. WREG32(0x15D8, 0);
  1156. WREG32(0x15DC, 0);
  1157. /* empty context1-7 */
  1158. /* Assign the pt base to something valid for now; the pts used for
  1159. * the VMs are determined by the application and setup and assigned
  1160. * on the fly in the vm part of radeon_gart.c
  1161. */
  1162. for (i = 1; i < 8; i++) {
  1163. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
  1164. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
  1165. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
  1166. rdev->gart.table_addr >> 12);
  1167. }
  1168. /* enable context1-7 */
  1169. WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
  1170. (u32)(rdev->dummy_page.addr >> 12));
  1171. WREG32(VM_CONTEXT1_CNTL2, 4);
  1172. WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
  1173. RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1174. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  1175. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1176. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  1177. PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1178. PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
  1179. VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1180. VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
  1181. READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1182. READ_PROTECTION_FAULT_ENABLE_DEFAULT |
  1183. WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  1184. WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
  1185. cayman_pcie_gart_tlb_flush(rdev);
  1186. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  1187. (unsigned)(rdev->mc.gtt_size >> 20),
  1188. (unsigned long long)rdev->gart.table_addr);
  1189. rdev->gart.ready = true;
  1190. return 0;
  1191. }
  1192. static void cayman_pcie_gart_disable(struct radeon_device *rdev)
  1193. {
  1194. /* Disable all tables */
  1195. WREG32(VM_CONTEXT0_CNTL, 0);
  1196. WREG32(VM_CONTEXT1_CNTL, 0);
  1197. /* Setup TLB control */
  1198. WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
  1199. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  1200. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  1201. /* Setup L2 cache */
  1202. WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  1203. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  1204. EFFECTIVE_L2_QUEUE_SIZE(7) |
  1205. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  1206. WREG32(VM_L2_CNTL2, 0);
  1207. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  1208. L2_CACHE_BIGK_FRAGMENT_SIZE(6));
  1209. radeon_gart_table_vram_unpin(rdev);
  1210. }
  1211. static void cayman_pcie_gart_fini(struct radeon_device *rdev)
  1212. {
  1213. cayman_pcie_gart_disable(rdev);
  1214. radeon_gart_table_vram_free(rdev);
  1215. radeon_gart_fini(rdev);
  1216. }
  1217. void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  1218. int ring, u32 cp_int_cntl)
  1219. {
  1220. u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
  1221. WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
  1222. WREG32(CP_INT_CNTL, cp_int_cntl);
  1223. }
  1224. /*
  1225. * CP.
  1226. */
  1227. void cayman_fence_ring_emit(struct radeon_device *rdev,
  1228. struct radeon_fence *fence)
  1229. {
  1230. struct radeon_ring *ring = &rdev->ring[fence->ring];
  1231. u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
  1232. /* flush read cache over gart for this vmid */
  1233. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  1234. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  1235. radeon_ring_write(ring, 0);
  1236. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  1237. radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
  1238. radeon_ring_write(ring, 0xFFFFFFFF);
  1239. radeon_ring_write(ring, 0);
  1240. radeon_ring_write(ring, 10); /* poll interval */
  1241. /* EVENT_WRITE_EOP - flush caches, send int */
  1242. radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
  1243. radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
  1244. radeon_ring_write(ring, addr & 0xffffffff);
  1245. radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
  1246. radeon_ring_write(ring, fence->seq);
  1247. radeon_ring_write(ring, 0);
  1248. }
  1249. void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  1250. {
  1251. struct radeon_ring *ring = &rdev->ring[ib->ring];
  1252. /* set to DX10/11 mode */
  1253. radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
  1254. radeon_ring_write(ring, 1);
  1255. if (ring->rptr_save_reg) {
  1256. uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
  1257. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  1258. radeon_ring_write(ring, ((ring->rptr_save_reg -
  1259. PACKET3_SET_CONFIG_REG_START) >> 2));
  1260. radeon_ring_write(ring, next_rptr);
  1261. }
  1262. radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
  1263. radeon_ring_write(ring,
  1264. #ifdef __BIG_ENDIAN
  1265. (2 << 0) |
  1266. #endif
  1267. (ib->gpu_addr & 0xFFFFFFFC));
  1268. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
  1269. radeon_ring_write(ring, ib->length_dw |
  1270. (ib->vm ? (ib->vm->id << 24) : 0));
  1271. /* flush read cache over gart for this vmid */
  1272. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  1273. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  1274. radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
  1275. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  1276. radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
  1277. radeon_ring_write(ring, 0xFFFFFFFF);
  1278. radeon_ring_write(ring, 0);
  1279. radeon_ring_write(ring, 10); /* poll interval */
  1280. }
  1281. static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
  1282. {
  1283. if (enable)
  1284. WREG32(CP_ME_CNTL, 0);
  1285. else {
  1286. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  1287. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
  1288. WREG32(SCRATCH_UMSK, 0);
  1289. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  1290. }
  1291. }
  1292. static int cayman_cp_load_microcode(struct radeon_device *rdev)
  1293. {
  1294. const __be32 *fw_data;
  1295. int i;
  1296. if (!rdev->me_fw || !rdev->pfp_fw)
  1297. return -EINVAL;
  1298. cayman_cp_enable(rdev, false);
  1299. fw_data = (const __be32 *)rdev->pfp_fw->data;
  1300. WREG32(CP_PFP_UCODE_ADDR, 0);
  1301. for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
  1302. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  1303. WREG32(CP_PFP_UCODE_ADDR, 0);
  1304. fw_data = (const __be32 *)rdev->me_fw->data;
  1305. WREG32(CP_ME_RAM_WADDR, 0);
  1306. for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
  1307. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  1308. WREG32(CP_PFP_UCODE_ADDR, 0);
  1309. WREG32(CP_ME_RAM_WADDR, 0);
  1310. WREG32(CP_ME_RAM_RADDR, 0);
  1311. return 0;
  1312. }
  1313. static int cayman_cp_start(struct radeon_device *rdev)
  1314. {
  1315. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1316. int r, i;
  1317. r = radeon_ring_lock(rdev, ring, 7);
  1318. if (r) {
  1319. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  1320. return r;
  1321. }
  1322. radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
  1323. radeon_ring_write(ring, 0x1);
  1324. radeon_ring_write(ring, 0x0);
  1325. radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
  1326. radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
  1327. radeon_ring_write(ring, 0);
  1328. radeon_ring_write(ring, 0);
  1329. radeon_ring_unlock_commit(rdev, ring);
  1330. cayman_cp_enable(rdev, true);
  1331. r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
  1332. if (r) {
  1333. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  1334. return r;
  1335. }
  1336. /* setup clear context state */
  1337. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1338. radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  1339. for (i = 0; i < cayman_default_size; i++)
  1340. radeon_ring_write(ring, cayman_default_state[i]);
  1341. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1342. radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  1343. /* set clear context state */
  1344. radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  1345. radeon_ring_write(ring, 0);
  1346. /* SQ_VTX_BASE_VTX_LOC */
  1347. radeon_ring_write(ring, 0xc0026f00);
  1348. radeon_ring_write(ring, 0x00000000);
  1349. radeon_ring_write(ring, 0x00000000);
  1350. radeon_ring_write(ring, 0x00000000);
  1351. /* Clear consts */
  1352. radeon_ring_write(ring, 0xc0036f00);
  1353. radeon_ring_write(ring, 0x00000bc4);
  1354. radeon_ring_write(ring, 0xffffffff);
  1355. radeon_ring_write(ring, 0xffffffff);
  1356. radeon_ring_write(ring, 0xffffffff);
  1357. radeon_ring_write(ring, 0xc0026900);
  1358. radeon_ring_write(ring, 0x00000316);
  1359. radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  1360. radeon_ring_write(ring, 0x00000010); /* */
  1361. radeon_ring_unlock_commit(rdev, ring);
  1362. /* XXX init other rings */
  1363. return 0;
  1364. }
  1365. static void cayman_cp_fini(struct radeon_device *rdev)
  1366. {
  1367. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1368. cayman_cp_enable(rdev, false);
  1369. radeon_ring_fini(rdev, ring);
  1370. radeon_scratch_free(rdev, ring->rptr_save_reg);
  1371. }
  1372. static int cayman_cp_resume(struct radeon_device *rdev)
  1373. {
  1374. static const int ridx[] = {
  1375. RADEON_RING_TYPE_GFX_INDEX,
  1376. CAYMAN_RING_TYPE_CP1_INDEX,
  1377. CAYMAN_RING_TYPE_CP2_INDEX
  1378. };
  1379. static const unsigned cp_rb_cntl[] = {
  1380. CP_RB0_CNTL,
  1381. CP_RB1_CNTL,
  1382. CP_RB2_CNTL,
  1383. };
  1384. static const unsigned cp_rb_rptr_addr[] = {
  1385. CP_RB0_RPTR_ADDR,
  1386. CP_RB1_RPTR_ADDR,
  1387. CP_RB2_RPTR_ADDR
  1388. };
  1389. static const unsigned cp_rb_rptr_addr_hi[] = {
  1390. CP_RB0_RPTR_ADDR_HI,
  1391. CP_RB1_RPTR_ADDR_HI,
  1392. CP_RB2_RPTR_ADDR_HI
  1393. };
  1394. static const unsigned cp_rb_base[] = {
  1395. CP_RB0_BASE,
  1396. CP_RB1_BASE,
  1397. CP_RB2_BASE
  1398. };
  1399. struct radeon_ring *ring;
  1400. int i, r;
  1401. /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
  1402. WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
  1403. SOFT_RESET_PA |
  1404. SOFT_RESET_SH |
  1405. SOFT_RESET_VGT |
  1406. SOFT_RESET_SPI |
  1407. SOFT_RESET_SX));
  1408. RREG32(GRBM_SOFT_RESET);
  1409. mdelay(15);
  1410. WREG32(GRBM_SOFT_RESET, 0);
  1411. RREG32(GRBM_SOFT_RESET);
  1412. WREG32(CP_SEM_WAIT_TIMER, 0x0);
  1413. WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
  1414. /* Set the write pointer delay */
  1415. WREG32(CP_RB_WPTR_DELAY, 0);
  1416. WREG32(CP_DEBUG, (1 << 27));
  1417. /* set the wb address whether it's enabled or not */
  1418. WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
  1419. WREG32(SCRATCH_UMSK, 0xff);
  1420. for (i = 0; i < 3; ++i) {
  1421. uint32_t rb_cntl;
  1422. uint64_t addr;
  1423. /* Set ring buffer size */
  1424. ring = &rdev->ring[ridx[i]];
  1425. rb_cntl = order_base_2(ring->ring_size / 8);
  1426. rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
  1427. #ifdef __BIG_ENDIAN
  1428. rb_cntl |= BUF_SWAP_32BIT;
  1429. #endif
  1430. WREG32(cp_rb_cntl[i], rb_cntl);
  1431. /* set the wb address whether it's enabled or not */
  1432. addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
  1433. WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
  1434. WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
  1435. }
  1436. /* set the rb base addr, this causes an internal reset of ALL rings */
  1437. for (i = 0; i < 3; ++i) {
  1438. ring = &rdev->ring[ridx[i]];
  1439. WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
  1440. }
  1441. for (i = 0; i < 3; ++i) {
  1442. /* Initialize the ring buffer's read and write pointers */
  1443. ring = &rdev->ring[ridx[i]];
  1444. WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
  1445. ring->rptr = ring->wptr = 0;
  1446. WREG32(ring->rptr_reg, ring->rptr);
  1447. WREG32(ring->wptr_reg, ring->wptr);
  1448. mdelay(1);
  1449. WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
  1450. }
  1451. /* start the rings */
  1452. cayman_cp_start(rdev);
  1453. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
  1454. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  1455. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  1456. /* this only test cp0 */
  1457. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  1458. if (r) {
  1459. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  1460. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  1461. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  1462. return r;
  1463. }
  1464. return 0;
  1465. }
  1466. u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
  1467. {
  1468. u32 reset_mask = 0;
  1469. u32 tmp;
  1470. /* GRBM_STATUS */
  1471. tmp = RREG32(GRBM_STATUS);
  1472. if (tmp & (PA_BUSY | SC_BUSY |
  1473. SH_BUSY | SX_BUSY |
  1474. TA_BUSY | VGT_BUSY |
  1475. DB_BUSY | CB_BUSY |
  1476. GDS_BUSY | SPI_BUSY |
  1477. IA_BUSY | IA_BUSY_NO_DMA))
  1478. reset_mask |= RADEON_RESET_GFX;
  1479. if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
  1480. CP_BUSY | CP_COHERENCY_BUSY))
  1481. reset_mask |= RADEON_RESET_CP;
  1482. if (tmp & GRBM_EE_BUSY)
  1483. reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
  1484. /* DMA_STATUS_REG 0 */
  1485. tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
  1486. if (!(tmp & DMA_IDLE))
  1487. reset_mask |= RADEON_RESET_DMA;
  1488. /* DMA_STATUS_REG 1 */
  1489. tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
  1490. if (!(tmp & DMA_IDLE))
  1491. reset_mask |= RADEON_RESET_DMA1;
  1492. /* SRBM_STATUS2 */
  1493. tmp = RREG32(SRBM_STATUS2);
  1494. if (tmp & DMA_BUSY)
  1495. reset_mask |= RADEON_RESET_DMA;
  1496. if (tmp & DMA1_BUSY)
  1497. reset_mask |= RADEON_RESET_DMA1;
  1498. /* SRBM_STATUS */
  1499. tmp = RREG32(SRBM_STATUS);
  1500. if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
  1501. reset_mask |= RADEON_RESET_RLC;
  1502. if (tmp & IH_BUSY)
  1503. reset_mask |= RADEON_RESET_IH;
  1504. if (tmp & SEM_BUSY)
  1505. reset_mask |= RADEON_RESET_SEM;
  1506. if (tmp & GRBM_RQ_PENDING)
  1507. reset_mask |= RADEON_RESET_GRBM;
  1508. if (tmp & VMC_BUSY)
  1509. reset_mask |= RADEON_RESET_VMC;
  1510. if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
  1511. MCC_BUSY | MCD_BUSY))
  1512. reset_mask |= RADEON_RESET_MC;
  1513. if (evergreen_is_display_hung(rdev))
  1514. reset_mask |= RADEON_RESET_DISPLAY;
  1515. /* VM_L2_STATUS */
  1516. tmp = RREG32(VM_L2_STATUS);
  1517. if (tmp & L2_BUSY)
  1518. reset_mask |= RADEON_RESET_VMC;
  1519. /* Skip MC reset as it's mostly likely not hung, just busy */
  1520. if (reset_mask & RADEON_RESET_MC) {
  1521. DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
  1522. reset_mask &= ~RADEON_RESET_MC;
  1523. }
  1524. return reset_mask;
  1525. }
  1526. static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
  1527. {
  1528. struct evergreen_mc_save save;
  1529. u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
  1530. u32 tmp;
  1531. if (reset_mask == 0)
  1532. return;
  1533. dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
  1534. evergreen_print_gpu_status_regs(rdev);
  1535. dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
  1536. RREG32(0x14F8));
  1537. dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
  1538. RREG32(0x14D8));
  1539. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
  1540. RREG32(0x14FC));
  1541. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
  1542. RREG32(0x14DC));
  1543. /* Disable CP parsing/prefetching */
  1544. WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
  1545. if (reset_mask & RADEON_RESET_DMA) {
  1546. /* dma0 */
  1547. tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
  1548. tmp &= ~DMA_RB_ENABLE;
  1549. WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
  1550. }
  1551. if (reset_mask & RADEON_RESET_DMA1) {
  1552. /* dma1 */
  1553. tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
  1554. tmp &= ~DMA_RB_ENABLE;
  1555. WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
  1556. }
  1557. udelay(50);
  1558. evergreen_mc_stop(rdev, &save);
  1559. if (evergreen_mc_wait_for_idle(rdev)) {
  1560. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1561. }
  1562. if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
  1563. grbm_soft_reset = SOFT_RESET_CB |
  1564. SOFT_RESET_DB |
  1565. SOFT_RESET_GDS |
  1566. SOFT_RESET_PA |
  1567. SOFT_RESET_SC |
  1568. SOFT_RESET_SPI |
  1569. SOFT_RESET_SH |
  1570. SOFT_RESET_SX |
  1571. SOFT_RESET_TC |
  1572. SOFT_RESET_TA |
  1573. SOFT_RESET_VGT |
  1574. SOFT_RESET_IA;
  1575. }
  1576. if (reset_mask & RADEON_RESET_CP) {
  1577. grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
  1578. srbm_soft_reset |= SOFT_RESET_GRBM;
  1579. }
  1580. if (reset_mask & RADEON_RESET_DMA)
  1581. srbm_soft_reset |= SOFT_RESET_DMA;
  1582. if (reset_mask & RADEON_RESET_DMA1)
  1583. srbm_soft_reset |= SOFT_RESET_DMA1;
  1584. if (reset_mask & RADEON_RESET_DISPLAY)
  1585. srbm_soft_reset |= SOFT_RESET_DC;
  1586. if (reset_mask & RADEON_RESET_RLC)
  1587. srbm_soft_reset |= SOFT_RESET_RLC;
  1588. if (reset_mask & RADEON_RESET_SEM)
  1589. srbm_soft_reset |= SOFT_RESET_SEM;
  1590. if (reset_mask & RADEON_RESET_IH)
  1591. srbm_soft_reset |= SOFT_RESET_IH;
  1592. if (reset_mask & RADEON_RESET_GRBM)
  1593. srbm_soft_reset |= SOFT_RESET_GRBM;
  1594. if (reset_mask & RADEON_RESET_VMC)
  1595. srbm_soft_reset |= SOFT_RESET_VMC;
  1596. if (!(rdev->flags & RADEON_IS_IGP)) {
  1597. if (reset_mask & RADEON_RESET_MC)
  1598. srbm_soft_reset |= SOFT_RESET_MC;
  1599. }
  1600. if (grbm_soft_reset) {
  1601. tmp = RREG32(GRBM_SOFT_RESET);
  1602. tmp |= grbm_soft_reset;
  1603. dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
  1604. WREG32(GRBM_SOFT_RESET, tmp);
  1605. tmp = RREG32(GRBM_SOFT_RESET);
  1606. udelay(50);
  1607. tmp &= ~grbm_soft_reset;
  1608. WREG32(GRBM_SOFT_RESET, tmp);
  1609. tmp = RREG32(GRBM_SOFT_RESET);
  1610. }
  1611. if (srbm_soft_reset) {
  1612. tmp = RREG32(SRBM_SOFT_RESET);
  1613. tmp |= srbm_soft_reset;
  1614. dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  1615. WREG32(SRBM_SOFT_RESET, tmp);
  1616. tmp = RREG32(SRBM_SOFT_RESET);
  1617. udelay(50);
  1618. tmp &= ~srbm_soft_reset;
  1619. WREG32(SRBM_SOFT_RESET, tmp);
  1620. tmp = RREG32(SRBM_SOFT_RESET);
  1621. }
  1622. /* Wait a little for things to settle down */
  1623. udelay(50);
  1624. evergreen_mc_resume(rdev, &save);
  1625. udelay(50);
  1626. evergreen_print_gpu_status_regs(rdev);
  1627. }
  1628. int cayman_asic_reset(struct radeon_device *rdev)
  1629. {
  1630. u32 reset_mask;
  1631. reset_mask = cayman_gpu_check_soft_reset(rdev);
  1632. if (reset_mask)
  1633. r600_set_bios_scratch_engine_hung(rdev, true);
  1634. cayman_gpu_soft_reset(rdev, reset_mask);
  1635. reset_mask = cayman_gpu_check_soft_reset(rdev);
  1636. if (!reset_mask)
  1637. r600_set_bios_scratch_engine_hung(rdev, false);
  1638. return 0;
  1639. }
  1640. /**
  1641. * cayman_gfx_is_lockup - Check if the GFX engine is locked up
  1642. *
  1643. * @rdev: radeon_device pointer
  1644. * @ring: radeon_ring structure holding ring information
  1645. *
  1646. * Check if the GFX engine is locked up.
  1647. * Returns true if the engine appears to be locked up, false if not.
  1648. */
  1649. bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  1650. {
  1651. u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
  1652. if (!(reset_mask & (RADEON_RESET_GFX |
  1653. RADEON_RESET_COMPUTE |
  1654. RADEON_RESET_CP))) {
  1655. radeon_ring_lockup_update(ring);
  1656. return false;
  1657. }
  1658. /* force CP activities */
  1659. radeon_ring_force_activity(rdev, ring);
  1660. return radeon_ring_test_lockup(rdev, ring);
  1661. }
  1662. static int cayman_startup(struct radeon_device *rdev)
  1663. {
  1664. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1665. int r;
  1666. /* enable pcie gen2 link */
  1667. evergreen_pcie_gen2_enable(rdev);
  1668. /* enable aspm */
  1669. evergreen_program_aspm(rdev);
  1670. /* scratch needs to be initialized before MC */
  1671. r = r600_vram_scratch_init(rdev);
  1672. if (r)
  1673. return r;
  1674. evergreen_mc_program(rdev);
  1675. if (rdev->flags & RADEON_IS_IGP) {
  1676. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  1677. r = ni_init_microcode(rdev);
  1678. if (r) {
  1679. DRM_ERROR("Failed to load firmware!\n");
  1680. return r;
  1681. }
  1682. }
  1683. } else {
  1684. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
  1685. r = ni_init_microcode(rdev);
  1686. if (r) {
  1687. DRM_ERROR("Failed to load firmware!\n");
  1688. return r;
  1689. }
  1690. }
  1691. r = ni_mc_load_microcode(rdev);
  1692. if (r) {
  1693. DRM_ERROR("Failed to load MC firmware!\n");
  1694. return r;
  1695. }
  1696. }
  1697. r = cayman_pcie_gart_enable(rdev);
  1698. if (r)
  1699. return r;
  1700. cayman_gpu_init(rdev);
  1701. /* allocate rlc buffers */
  1702. if (rdev->flags & RADEON_IS_IGP) {
  1703. rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
  1704. rdev->rlc.reg_list_size =
  1705. (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
  1706. rdev->rlc.cs_data = cayman_cs_data;
  1707. r = sumo_rlc_init(rdev);
  1708. if (r) {
  1709. DRM_ERROR("Failed to init rlc BOs!\n");
  1710. return r;
  1711. }
  1712. }
  1713. /* allocate wb buffer */
  1714. r = radeon_wb_init(rdev);
  1715. if (r)
  1716. return r;
  1717. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  1718. if (r) {
  1719. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  1720. return r;
  1721. }
  1722. r = uvd_v2_2_resume(rdev);
  1723. if (!r) {
  1724. r = radeon_fence_driver_start_ring(rdev,
  1725. R600_RING_TYPE_UVD_INDEX);
  1726. if (r)
  1727. dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
  1728. }
  1729. if (r)
  1730. rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
  1731. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  1732. if (r) {
  1733. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  1734. return r;
  1735. }
  1736. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  1737. if (r) {
  1738. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  1739. return r;
  1740. }
  1741. r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
  1742. if (r) {
  1743. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  1744. return r;
  1745. }
  1746. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
  1747. if (r) {
  1748. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  1749. return r;
  1750. }
  1751. /* Enable IRQ */
  1752. if (!rdev->irq.installed) {
  1753. r = radeon_irq_kms_init(rdev);
  1754. if (r)
  1755. return r;
  1756. }
  1757. r = r600_irq_init(rdev);
  1758. if (r) {
  1759. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  1760. radeon_irq_kms_fini(rdev);
  1761. return r;
  1762. }
  1763. evergreen_irq_set(rdev);
  1764. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  1765. CP_RB0_RPTR, CP_RB0_WPTR,
  1766. RADEON_CP_PACKET2);
  1767. if (r)
  1768. return r;
  1769. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  1770. r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
  1771. DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
  1772. DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
  1773. DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
  1774. if (r)
  1775. return r;
  1776. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  1777. r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
  1778. DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
  1779. DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
  1780. DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
  1781. if (r)
  1782. return r;
  1783. r = cayman_cp_load_microcode(rdev);
  1784. if (r)
  1785. return r;
  1786. r = cayman_cp_resume(rdev);
  1787. if (r)
  1788. return r;
  1789. r = cayman_dma_resume(rdev);
  1790. if (r)
  1791. return r;
  1792. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  1793. if (ring->ring_size) {
  1794. r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
  1795. UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
  1796. RADEON_CP_PACKET2);
  1797. if (!r)
  1798. r = uvd_v1_0_init(rdev);
  1799. if (r)
  1800. DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
  1801. }
  1802. r = radeon_ib_pool_init(rdev);
  1803. if (r) {
  1804. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  1805. return r;
  1806. }
  1807. r = radeon_vm_manager_init(rdev);
  1808. if (r) {
  1809. dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
  1810. return r;
  1811. }
  1812. if (ASIC_IS_DCE6(rdev)) {
  1813. r = dce6_audio_init(rdev);
  1814. if (r)
  1815. return r;
  1816. } else {
  1817. r = r600_audio_init(rdev);
  1818. if (r)
  1819. return r;
  1820. }
  1821. return 0;
  1822. }
  1823. int cayman_resume(struct radeon_device *rdev)
  1824. {
  1825. int r;
  1826. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  1827. * posting will perform necessary task to bring back GPU into good
  1828. * shape.
  1829. */
  1830. /* post card */
  1831. atom_asic_init(rdev->mode_info.atom_context);
  1832. /* init golden registers */
  1833. ni_init_golden_registers(rdev);
  1834. rdev->accel_working = true;
  1835. r = cayman_startup(rdev);
  1836. if (r) {
  1837. DRM_ERROR("cayman startup failed on resume\n");
  1838. rdev->accel_working = false;
  1839. return r;
  1840. }
  1841. return r;
  1842. }
  1843. int cayman_suspend(struct radeon_device *rdev)
  1844. {
  1845. if (ASIC_IS_DCE6(rdev))
  1846. dce6_audio_fini(rdev);
  1847. else
  1848. r600_audio_fini(rdev);
  1849. radeon_vm_manager_fini(rdev);
  1850. cayman_cp_enable(rdev, false);
  1851. cayman_dma_stop(rdev);
  1852. uvd_v1_0_fini(rdev);
  1853. radeon_uvd_suspend(rdev);
  1854. evergreen_irq_suspend(rdev);
  1855. radeon_wb_disable(rdev);
  1856. cayman_pcie_gart_disable(rdev);
  1857. return 0;
  1858. }
  1859. /* Plan is to move initialization in that function and use
  1860. * helper function so that radeon_device_init pretty much
  1861. * do nothing more than calling asic specific function. This
  1862. * should also allow to remove a bunch of callback function
  1863. * like vram_info.
  1864. */
  1865. int cayman_init(struct radeon_device *rdev)
  1866. {
  1867. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1868. int r;
  1869. /* Read BIOS */
  1870. if (!radeon_get_bios(rdev)) {
  1871. if (ASIC_IS_AVIVO(rdev))
  1872. return -EINVAL;
  1873. }
  1874. /* Must be an ATOMBIOS */
  1875. if (!rdev->is_atom_bios) {
  1876. dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
  1877. return -EINVAL;
  1878. }
  1879. r = radeon_atombios_init(rdev);
  1880. if (r)
  1881. return r;
  1882. /* Post card if necessary */
  1883. if (!radeon_card_posted(rdev)) {
  1884. if (!rdev->bios) {
  1885. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  1886. return -EINVAL;
  1887. }
  1888. DRM_INFO("GPU not posted. posting now...\n");
  1889. atom_asic_init(rdev->mode_info.atom_context);
  1890. }
  1891. /* init golden registers */
  1892. ni_init_golden_registers(rdev);
  1893. /* Initialize scratch registers */
  1894. r600_scratch_init(rdev);
  1895. /* Initialize surface registers */
  1896. radeon_surface_init(rdev);
  1897. /* Initialize clocks */
  1898. radeon_get_clock_info(rdev->ddev);
  1899. /* Fence driver */
  1900. r = radeon_fence_driver_init(rdev);
  1901. if (r)
  1902. return r;
  1903. /* initialize memory controller */
  1904. r = evergreen_mc_init(rdev);
  1905. if (r)
  1906. return r;
  1907. /* Memory manager */
  1908. r = radeon_bo_init(rdev);
  1909. if (r)
  1910. return r;
  1911. ring->ring_obj = NULL;
  1912. r600_ring_init(rdev, ring, 1024 * 1024);
  1913. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  1914. ring->ring_obj = NULL;
  1915. r600_ring_init(rdev, ring, 64 * 1024);
  1916. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  1917. ring->ring_obj = NULL;
  1918. r600_ring_init(rdev, ring, 64 * 1024);
  1919. r = radeon_uvd_init(rdev);
  1920. if (!r) {
  1921. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  1922. ring->ring_obj = NULL;
  1923. r600_ring_init(rdev, ring, 4096);
  1924. }
  1925. rdev->ih.ring_obj = NULL;
  1926. r600_ih_ring_init(rdev, 64 * 1024);
  1927. r = r600_pcie_gart_init(rdev);
  1928. if (r)
  1929. return r;
  1930. rdev->accel_working = true;
  1931. r = cayman_startup(rdev);
  1932. if (r) {
  1933. dev_err(rdev->dev, "disabling GPU acceleration\n");
  1934. cayman_cp_fini(rdev);
  1935. cayman_dma_fini(rdev);
  1936. r600_irq_fini(rdev);
  1937. if (rdev->flags & RADEON_IS_IGP)
  1938. sumo_rlc_fini(rdev);
  1939. radeon_wb_fini(rdev);
  1940. radeon_ib_pool_fini(rdev);
  1941. radeon_vm_manager_fini(rdev);
  1942. radeon_irq_kms_fini(rdev);
  1943. cayman_pcie_gart_fini(rdev);
  1944. rdev->accel_working = false;
  1945. }
  1946. /* Don't start up if the MC ucode is missing.
  1947. * The default clocks and voltages before the MC ucode
  1948. * is loaded are not suffient for advanced operations.
  1949. *
  1950. * We can skip this check for TN, because there is no MC
  1951. * ucode.
  1952. */
  1953. if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
  1954. DRM_ERROR("radeon: MC ucode required for NI+.\n");
  1955. return -EINVAL;
  1956. }
  1957. return 0;
  1958. }
  1959. void cayman_fini(struct radeon_device *rdev)
  1960. {
  1961. cayman_cp_fini(rdev);
  1962. cayman_dma_fini(rdev);
  1963. r600_irq_fini(rdev);
  1964. if (rdev->flags & RADEON_IS_IGP)
  1965. sumo_rlc_fini(rdev);
  1966. radeon_wb_fini(rdev);
  1967. radeon_vm_manager_fini(rdev);
  1968. radeon_ib_pool_fini(rdev);
  1969. radeon_irq_kms_fini(rdev);
  1970. uvd_v1_0_fini(rdev);
  1971. radeon_uvd_fini(rdev);
  1972. cayman_pcie_gart_fini(rdev);
  1973. r600_vram_scratch_fini(rdev);
  1974. radeon_gem_fini(rdev);
  1975. radeon_fence_driver_fini(rdev);
  1976. radeon_bo_fini(rdev);
  1977. radeon_atombios_fini(rdev);
  1978. kfree(rdev->bios);
  1979. rdev->bios = NULL;
  1980. }
  1981. /*
  1982. * vm
  1983. */
  1984. int cayman_vm_init(struct radeon_device *rdev)
  1985. {
  1986. /* number of VMs */
  1987. rdev->vm_manager.nvm = 8;
  1988. /* base offset of vram pages */
  1989. if (rdev->flags & RADEON_IS_IGP) {
  1990. u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
  1991. tmp <<= 22;
  1992. rdev->vm_manager.vram_base_offset = tmp;
  1993. } else
  1994. rdev->vm_manager.vram_base_offset = 0;
  1995. return 0;
  1996. }
  1997. void cayman_vm_fini(struct radeon_device *rdev)
  1998. {
  1999. }
  2000. /**
  2001. * cayman_vm_decode_fault - print human readable fault info
  2002. *
  2003. * @rdev: radeon_device pointer
  2004. * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
  2005. * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
  2006. *
  2007. * Print human readable fault information (cayman/TN).
  2008. */
  2009. void cayman_vm_decode_fault(struct radeon_device *rdev,
  2010. u32 status, u32 addr)
  2011. {
  2012. u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
  2013. u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
  2014. u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
  2015. char *block;
  2016. switch (mc_id) {
  2017. case 32:
  2018. case 16:
  2019. case 96:
  2020. case 80:
  2021. case 160:
  2022. case 144:
  2023. case 224:
  2024. case 208:
  2025. block = "CB";
  2026. break;
  2027. case 33:
  2028. case 17:
  2029. case 97:
  2030. case 81:
  2031. case 161:
  2032. case 145:
  2033. case 225:
  2034. case 209:
  2035. block = "CB_FMASK";
  2036. break;
  2037. case 34:
  2038. case 18:
  2039. case 98:
  2040. case 82:
  2041. case 162:
  2042. case 146:
  2043. case 226:
  2044. case 210:
  2045. block = "CB_CMASK";
  2046. break;
  2047. case 35:
  2048. case 19:
  2049. case 99:
  2050. case 83:
  2051. case 163:
  2052. case 147:
  2053. case 227:
  2054. case 211:
  2055. block = "CB_IMMED";
  2056. break;
  2057. case 36:
  2058. case 20:
  2059. case 100:
  2060. case 84:
  2061. case 164:
  2062. case 148:
  2063. case 228:
  2064. case 212:
  2065. block = "DB";
  2066. break;
  2067. case 37:
  2068. case 21:
  2069. case 101:
  2070. case 85:
  2071. case 165:
  2072. case 149:
  2073. case 229:
  2074. case 213:
  2075. block = "DB_HTILE";
  2076. break;
  2077. case 38:
  2078. case 22:
  2079. case 102:
  2080. case 86:
  2081. case 166:
  2082. case 150:
  2083. case 230:
  2084. case 214:
  2085. block = "SX";
  2086. break;
  2087. case 39:
  2088. case 23:
  2089. case 103:
  2090. case 87:
  2091. case 167:
  2092. case 151:
  2093. case 231:
  2094. case 215:
  2095. block = "DB_STEN";
  2096. break;
  2097. case 40:
  2098. case 24:
  2099. case 104:
  2100. case 88:
  2101. case 232:
  2102. case 216:
  2103. case 168:
  2104. case 152:
  2105. block = "TC_TFETCH";
  2106. break;
  2107. case 41:
  2108. case 25:
  2109. case 105:
  2110. case 89:
  2111. case 233:
  2112. case 217:
  2113. case 169:
  2114. case 153:
  2115. block = "TC_VFETCH";
  2116. break;
  2117. case 42:
  2118. case 26:
  2119. case 106:
  2120. case 90:
  2121. case 234:
  2122. case 218:
  2123. case 170:
  2124. case 154:
  2125. block = "VC";
  2126. break;
  2127. case 112:
  2128. block = "CP";
  2129. break;
  2130. case 113:
  2131. case 114:
  2132. block = "SH";
  2133. break;
  2134. case 115:
  2135. block = "VGT";
  2136. break;
  2137. case 178:
  2138. block = "IH";
  2139. break;
  2140. case 51:
  2141. block = "RLC";
  2142. break;
  2143. case 55:
  2144. block = "DMA";
  2145. break;
  2146. case 56:
  2147. block = "HDP";
  2148. break;
  2149. default:
  2150. block = "unknown";
  2151. break;
  2152. }
  2153. printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
  2154. protections, vmid, addr,
  2155. (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
  2156. block, mc_id);
  2157. }
  2158. #define R600_ENTRY_VALID (1 << 0)
  2159. #define R600_PTE_SYSTEM (1 << 1)
  2160. #define R600_PTE_SNOOPED (1 << 2)
  2161. #define R600_PTE_READABLE (1 << 5)
  2162. #define R600_PTE_WRITEABLE (1 << 6)
  2163. uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
  2164. {
  2165. uint32_t r600_flags = 0;
  2166. r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
  2167. r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
  2168. r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
  2169. if (flags & RADEON_VM_PAGE_SYSTEM) {
  2170. r600_flags |= R600_PTE_SYSTEM;
  2171. r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
  2172. }
  2173. return r600_flags;
  2174. }
  2175. /**
  2176. * cayman_vm_set_page - update the page tables using the CP
  2177. *
  2178. * @rdev: radeon_device pointer
  2179. * @ib: indirect buffer to fill with commands
  2180. * @pe: addr of the page entry
  2181. * @addr: dst addr to write into pe
  2182. * @count: number of page entries to update
  2183. * @incr: increase next addr by incr bytes
  2184. * @flags: access flags
  2185. *
  2186. * Update the page tables using the CP (cayman/TN).
  2187. */
  2188. void cayman_vm_set_page(struct radeon_device *rdev,
  2189. struct radeon_ib *ib,
  2190. uint64_t pe,
  2191. uint64_t addr, unsigned count,
  2192. uint32_t incr, uint32_t flags)
  2193. {
  2194. uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
  2195. uint64_t value;
  2196. unsigned ndw;
  2197. if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
  2198. while (count) {
  2199. ndw = 1 + count * 2;
  2200. if (ndw > 0x3FFF)
  2201. ndw = 0x3FFF;
  2202. ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
  2203. ib->ptr[ib->length_dw++] = pe;
  2204. ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
  2205. for (; ndw > 1; ndw -= 2, --count, pe += 8) {
  2206. if (flags & RADEON_VM_PAGE_SYSTEM) {
  2207. value = radeon_vm_map_gart(rdev, addr);
  2208. value &= 0xFFFFFFFFFFFFF000ULL;
  2209. } else if (flags & RADEON_VM_PAGE_VALID) {
  2210. value = addr;
  2211. } else {
  2212. value = 0;
  2213. }
  2214. addr += incr;
  2215. value |= r600_flags;
  2216. ib->ptr[ib->length_dw++] = value;
  2217. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  2218. }
  2219. }
  2220. } else {
  2221. cayman_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
  2222. }
  2223. }
  2224. /**
  2225. * cayman_vm_flush - vm flush using the CP
  2226. *
  2227. * @rdev: radeon_device pointer
  2228. *
  2229. * Update the page table base and flush the VM TLB
  2230. * using the CP (cayman-si).
  2231. */
  2232. void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
  2233. {
  2234. struct radeon_ring *ring = &rdev->ring[ridx];
  2235. if (vm == NULL)
  2236. return;
  2237. radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
  2238. radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
  2239. /* flush hdp cache */
  2240. radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
  2241. radeon_ring_write(ring, 0x1);
  2242. /* bits 0-7 are the VM contexts0-7 */
  2243. radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
  2244. radeon_ring_write(ring, 1 << vm->id);
  2245. /* sync PFP to ME, otherwise we might get invalid PFP reads */
  2246. radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  2247. radeon_ring_write(ring, 0x0);
  2248. }