cikd.h 81 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901
  1. /*
  2. * Copyright 2012 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #ifndef CIK_H
  25. #define CIK_H
  26. #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
  27. #define CIK_RB_BITMAP_WIDTH_PER_SH 2
  28. /* DIDT IND registers */
  29. #define DIDT_SQ_CTRL0 0x0
  30. # define DIDT_CTRL_EN (1 << 0)
  31. #define DIDT_DB_CTRL0 0x20
  32. #define DIDT_TD_CTRL0 0x40
  33. #define DIDT_TCP_CTRL0 0x60
  34. /* SMC IND registers */
  35. #define DPM_TABLE_475 0x3F768
  36. # define SamuBootLevel(x) ((x) << 0)
  37. # define SamuBootLevel_MASK 0x000000ff
  38. # define SamuBootLevel_SHIFT 0
  39. # define AcpBootLevel(x) ((x) << 8)
  40. # define AcpBootLevel_MASK 0x0000ff00
  41. # define AcpBootLevel_SHIFT 8
  42. # define VceBootLevel(x) ((x) << 16)
  43. # define VceBootLevel_MASK 0x00ff0000
  44. # define VceBootLevel_SHIFT 16
  45. # define UvdBootLevel(x) ((x) << 24)
  46. # define UvdBootLevel_MASK 0xff000000
  47. # define UvdBootLevel_SHIFT 24
  48. #define FIRMWARE_FLAGS 0x3F800
  49. # define INTERRUPTS_ENABLED (1 << 0)
  50. #define NB_DPM_CONFIG_1 0x3F9E8
  51. # define Dpm0PgNbPsLo(x) ((x) << 0)
  52. # define Dpm0PgNbPsLo_MASK 0x000000ff
  53. # define Dpm0PgNbPsLo_SHIFT 0
  54. # define Dpm0PgNbPsHi(x) ((x) << 8)
  55. # define Dpm0PgNbPsHi_MASK 0x0000ff00
  56. # define Dpm0PgNbPsHi_SHIFT 8
  57. # define DpmXNbPsLo(x) ((x) << 16)
  58. # define DpmXNbPsLo_MASK 0x00ff0000
  59. # define DpmXNbPsLo_SHIFT 16
  60. # define DpmXNbPsHi(x) ((x) << 24)
  61. # define DpmXNbPsHi_MASK 0xff000000
  62. # define DpmXNbPsHi_SHIFT 24
  63. #define SMC_SYSCON_RESET_CNTL 0x80000000
  64. # define RST_REG (1 << 0)
  65. #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
  66. # define CK_DISABLE (1 << 0)
  67. # define CKEN (1 << 24)
  68. #define SMC_SYSCON_MISC_CNTL 0x80000010
  69. #define SMC_SYSCON_MSG_ARG_0 0x80000068
  70. #define SMC_PC_C 0x80000370
  71. #define SMC_SCRATCH9 0x80000424
  72. #define RCU_UC_EVENTS 0xC0000004
  73. # define BOOT_SEQ_DONE (1 << 7)
  74. #define GENERAL_PWRMGT 0xC0200000
  75. # define GLOBAL_PWRMGT_EN (1 << 0)
  76. # define STATIC_PM_EN (1 << 1)
  77. # define THERMAL_PROTECTION_DIS (1 << 2)
  78. # define THERMAL_PROTECTION_TYPE (1 << 3)
  79. # define SW_SMIO_INDEX(x) ((x) << 6)
  80. # define SW_SMIO_INDEX_MASK (1 << 6)
  81. # define SW_SMIO_INDEX_SHIFT 6
  82. # define VOLT_PWRMGT_EN (1 << 10)
  83. # define GPU_COUNTER_CLK (1 << 15)
  84. # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
  85. #define CNB_PWRMGT_CNTL 0xC0200004
  86. # define GNB_SLOW_MODE(x) ((x) << 0)
  87. # define GNB_SLOW_MODE_MASK (3 << 0)
  88. # define GNB_SLOW_MODE_SHIFT 0
  89. # define GNB_SLOW (1 << 2)
  90. # define FORCE_NB_PS1 (1 << 3)
  91. # define DPM_ENABLED (1 << 4)
  92. #define SCLK_PWRMGT_CNTL 0xC0200008
  93. # define SCLK_PWRMGT_OFF (1 << 0)
  94. # define RESET_BUSY_CNT (1 << 4)
  95. # define RESET_SCLK_CNT (1 << 5)
  96. # define DYNAMIC_PM_EN (1 << 21)
  97. #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
  98. # define CURRENT_STATE_MASK (0xf << 4)
  99. # define CURRENT_STATE_SHIFT 4
  100. # define CURR_MCLK_INDEX_MASK (0xf << 8)
  101. # define CURR_MCLK_INDEX_SHIFT 8
  102. # define CURR_SCLK_INDEX_MASK (0x1f << 16)
  103. # define CURR_SCLK_INDEX_SHIFT 16
  104. #define CG_SSP 0xC0200044
  105. # define SST(x) ((x) << 0)
  106. # define SST_MASK (0xffff << 0)
  107. # define SSTU(x) ((x) << 16)
  108. # define SSTU_MASK (0xf << 16)
  109. #define CG_DISPLAY_GAP_CNTL 0xC0200060
  110. # define DISP_GAP(x) ((x) << 0)
  111. # define DISP_GAP_MASK (3 << 0)
  112. # define VBI_TIMER_COUNT(x) ((x) << 4)
  113. # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
  114. # define VBI_TIMER_UNIT(x) ((x) << 20)
  115. # define VBI_TIMER_UNIT_MASK (7 << 20)
  116. # define DISP_GAP_MCHG(x) ((x) << 24)
  117. # define DISP_GAP_MCHG_MASK (3 << 24)
  118. #define SMU_VOLTAGE_STATUS 0xC0200094
  119. # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
  120. # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
  121. #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
  122. # define CURR_PCIE_INDEX_MASK (0xf << 24)
  123. # define CURR_PCIE_INDEX_SHIFT 24
  124. #define CG_ULV_PARAMETER 0xC0200158
  125. #define CG_FTV_0 0xC02001A8
  126. #define CG_FTV_1 0xC02001AC
  127. #define CG_FTV_2 0xC02001B0
  128. #define CG_FTV_3 0xC02001B4
  129. #define CG_FTV_4 0xC02001B8
  130. #define CG_FTV_5 0xC02001BC
  131. #define CG_FTV_6 0xC02001C0
  132. #define CG_FTV_7 0xC02001C4
  133. #define CG_DISPLAY_GAP_CNTL2 0xC0200230
  134. #define LCAC_SX0_OVR_SEL 0xC0400D04
  135. #define LCAC_SX0_OVR_VAL 0xC0400D08
  136. #define LCAC_MC0_CNTL 0xC0400D30
  137. #define LCAC_MC0_OVR_SEL 0xC0400D34
  138. #define LCAC_MC0_OVR_VAL 0xC0400D38
  139. #define LCAC_MC1_CNTL 0xC0400D3C
  140. #define LCAC_MC1_OVR_SEL 0xC0400D40
  141. #define LCAC_MC1_OVR_VAL 0xC0400D44
  142. #define LCAC_MC2_OVR_SEL 0xC0400D4C
  143. #define LCAC_MC2_OVR_VAL 0xC0400D50
  144. #define LCAC_MC3_OVR_SEL 0xC0400D58
  145. #define LCAC_MC3_OVR_VAL 0xC0400D5C
  146. #define LCAC_CPL_CNTL 0xC0400D80
  147. #define LCAC_CPL_OVR_SEL 0xC0400D84
  148. #define LCAC_CPL_OVR_VAL 0xC0400D88
  149. /* dGPU */
  150. #define CG_THERMAL_CTRL 0xC0300004
  151. #define DPM_EVENT_SRC(x) ((x) << 0)
  152. #define DPM_EVENT_SRC_MASK (7 << 0)
  153. #define DIG_THERM_DPM(x) ((x) << 14)
  154. #define DIG_THERM_DPM_MASK 0x003FC000
  155. #define DIG_THERM_DPM_SHIFT 14
  156. #define CG_THERMAL_INT 0xC030000C
  157. #define CI_DIG_THERM_INTH(x) ((x) << 8)
  158. #define CI_DIG_THERM_INTH_MASK 0x0000FF00
  159. #define CI_DIG_THERM_INTH_SHIFT 8
  160. #define CI_DIG_THERM_INTL(x) ((x) << 16)
  161. #define CI_DIG_THERM_INTL_MASK 0x00FF0000
  162. #define CI_DIG_THERM_INTL_SHIFT 16
  163. #define THERM_INT_MASK_HIGH (1 << 24)
  164. #define THERM_INT_MASK_LOW (1 << 25)
  165. #define CG_MULT_THERMAL_STATUS 0xC0300014
  166. #define ASIC_MAX_TEMP(x) ((x) << 0)
  167. #define ASIC_MAX_TEMP_MASK 0x000001ff
  168. #define ASIC_MAX_TEMP_SHIFT 0
  169. #define CTF_TEMP(x) ((x) << 9)
  170. #define CTF_TEMP_MASK 0x0003fe00
  171. #define CTF_TEMP_SHIFT 9
  172. #define CG_SPLL_FUNC_CNTL 0xC0500140
  173. #define SPLL_RESET (1 << 0)
  174. #define SPLL_PWRON (1 << 1)
  175. #define SPLL_BYPASS_EN (1 << 3)
  176. #define SPLL_REF_DIV(x) ((x) << 5)
  177. #define SPLL_REF_DIV_MASK (0x3f << 5)
  178. #define SPLL_PDIV_A(x) ((x) << 20)
  179. #define SPLL_PDIV_A_MASK (0x7f << 20)
  180. #define SPLL_PDIV_A_SHIFT 20
  181. #define CG_SPLL_FUNC_CNTL_2 0xC0500144
  182. #define SCLK_MUX_SEL(x) ((x) << 0)
  183. #define SCLK_MUX_SEL_MASK (0x1ff << 0)
  184. #define CG_SPLL_FUNC_CNTL_3 0xC0500148
  185. #define SPLL_FB_DIV(x) ((x) << 0)
  186. #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
  187. #define SPLL_FB_DIV_SHIFT 0
  188. #define SPLL_DITHEN (1 << 28)
  189. #define CG_SPLL_FUNC_CNTL_4 0xC050014C
  190. #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
  191. #define SSEN (1 << 0)
  192. #define CLK_S(x) ((x) << 4)
  193. #define CLK_S_MASK (0xfff << 4)
  194. #define CLK_S_SHIFT 4
  195. #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
  196. #define CLK_V(x) ((x) << 0)
  197. #define CLK_V_MASK (0x3ffffff << 0)
  198. #define CLK_V_SHIFT 0
  199. #define MPLL_BYPASSCLK_SEL 0xC050019C
  200. # define MPLL_CLKOUT_SEL(x) ((x) << 8)
  201. # define MPLL_CLKOUT_SEL_MASK 0xFF00
  202. #define CG_CLKPIN_CNTL 0xC05001A0
  203. # define XTALIN_DIVIDE (1 << 1)
  204. # define BCLK_AS_XCLK (1 << 2)
  205. #define CG_CLKPIN_CNTL_2 0xC05001A4
  206. # define FORCE_BIF_REFCLK_EN (1 << 3)
  207. # define MUX_TCLK_TO_XCLK (1 << 8)
  208. #define THM_CLK_CNTL 0xC05001A8
  209. # define CMON_CLK_SEL(x) ((x) << 0)
  210. # define CMON_CLK_SEL_MASK 0xFF
  211. # define TMON_CLK_SEL(x) ((x) << 8)
  212. # define TMON_CLK_SEL_MASK 0xFF00
  213. #define MISC_CLK_CTRL 0xC05001AC
  214. # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
  215. # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
  216. # define ZCLK_SEL(x) ((x) << 8)
  217. # define ZCLK_SEL_MASK 0xFF00
  218. /* KV/KB */
  219. #define CG_THERMAL_INT_CTRL 0xC2100028
  220. #define DIG_THERM_INTH(x) ((x) << 0)
  221. #define DIG_THERM_INTH_MASK 0x000000FF
  222. #define DIG_THERM_INTH_SHIFT 0
  223. #define DIG_THERM_INTL(x) ((x) << 8)
  224. #define DIG_THERM_INTL_MASK 0x0000FF00
  225. #define DIG_THERM_INTL_SHIFT 8
  226. #define THERM_INTH_MASK (1 << 24)
  227. #define THERM_INTL_MASK (1 << 25)
  228. /* PCIE registers idx/data 0x38/0x3c */
  229. #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
  230. # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
  231. # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
  232. # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
  233. # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
  234. # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
  235. # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
  236. # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
  237. # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
  238. # define PLL_RAMP_UP_TIME_0_SHIFT 24
  239. #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
  240. # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
  241. # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
  242. # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
  243. # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
  244. # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
  245. # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
  246. # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
  247. # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
  248. # define PLL_RAMP_UP_TIME_1_SHIFT 24
  249. #define PCIE_CNTL2 0x1001001c /* PCIE */
  250. # define SLV_MEM_LS_EN (1 << 16)
  251. # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
  252. # define MST_MEM_LS_EN (1 << 18)
  253. # define REPLAY_MEM_LS_EN (1 << 19)
  254. #define PCIE_LC_STATUS1 0x1400028 /* PCIE */
  255. # define LC_REVERSE_RCVR (1 << 0)
  256. # define LC_REVERSE_XMIT (1 << 1)
  257. # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
  258. # define LC_OPERATING_LINK_WIDTH_SHIFT 2
  259. # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
  260. # define LC_DETECTED_LINK_WIDTH_SHIFT 5
  261. #define PCIE_P_CNTL 0x1400040 /* PCIE */
  262. # define P_IGNORE_EDB_ERR (1 << 6)
  263. #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
  264. #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
  265. #define PCIE_LC_CNTL 0x100100A0 /* PCIE */
  266. # define LC_L0S_INACTIVITY(x) ((x) << 8)
  267. # define LC_L0S_INACTIVITY_MASK (0xf << 8)
  268. # define LC_L0S_INACTIVITY_SHIFT 8
  269. # define LC_L1_INACTIVITY(x) ((x) << 12)
  270. # define LC_L1_INACTIVITY_MASK (0xf << 12)
  271. # define LC_L1_INACTIVITY_SHIFT 12
  272. # define LC_PMI_TO_L1_DIS (1 << 16)
  273. # define LC_ASPM_TO_L1_DIS (1 << 24)
  274. #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
  275. # define LC_LINK_WIDTH_SHIFT 0
  276. # define LC_LINK_WIDTH_MASK 0x7
  277. # define LC_LINK_WIDTH_X0 0
  278. # define LC_LINK_WIDTH_X1 1
  279. # define LC_LINK_WIDTH_X2 2
  280. # define LC_LINK_WIDTH_X4 3
  281. # define LC_LINK_WIDTH_X8 4
  282. # define LC_LINK_WIDTH_X16 6
  283. # define LC_LINK_WIDTH_RD_SHIFT 4
  284. # define LC_LINK_WIDTH_RD_MASK 0x70
  285. # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
  286. # define LC_RECONFIG_NOW (1 << 8)
  287. # define LC_RENEGOTIATION_SUPPORT (1 << 9)
  288. # define LC_RENEGOTIATE_EN (1 << 10)
  289. # define LC_SHORT_RECONFIG_EN (1 << 11)
  290. # define LC_UPCONFIGURE_SUPPORT (1 << 12)
  291. # define LC_UPCONFIGURE_DIS (1 << 13)
  292. # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
  293. # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
  294. # define LC_DYN_LANES_PWR_STATE_SHIFT 21
  295. #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
  296. # define LC_XMIT_N_FTS(x) ((x) << 0)
  297. # define LC_XMIT_N_FTS_MASK (0xff << 0)
  298. # define LC_XMIT_N_FTS_SHIFT 0
  299. # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
  300. # define LC_N_FTS_MASK (0xff << 24)
  301. #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
  302. # define LC_GEN2_EN_STRAP (1 << 0)
  303. # define LC_GEN3_EN_STRAP (1 << 1)
  304. # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
  305. # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
  306. # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
  307. # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
  308. # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
  309. # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
  310. # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
  311. # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
  312. # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
  313. # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
  314. # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
  315. # define LC_CURRENT_DATA_RATE_SHIFT 13
  316. # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
  317. # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
  318. # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
  319. # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
  320. # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
  321. #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
  322. # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
  323. # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
  324. #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
  325. # define LC_GO_TO_RECOVERY (1 << 30)
  326. #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
  327. # define LC_REDO_EQ (1 << 5)
  328. # define LC_SET_QUIESCE (1 << 13)
  329. /* direct registers */
  330. #define PCIE_INDEX 0x38
  331. #define PCIE_DATA 0x3C
  332. #define SMC_IND_INDEX_0 0x200
  333. #define SMC_IND_DATA_0 0x204
  334. #define SMC_IND_ACCESS_CNTL 0x240
  335. #define AUTO_INCREMENT_IND_0 (1 << 0)
  336. #define SMC_MESSAGE_0 0x250
  337. #define SMC_MSG_MASK 0xffff
  338. #define SMC_RESP_0 0x254
  339. #define SMC_RESP_MASK 0xffff
  340. #define SMC_MSG_ARG_0 0x290
  341. #define VGA_HDP_CONTROL 0x328
  342. #define VGA_MEMORY_DISABLE (1 << 4)
  343. #define DMIF_ADDR_CALC 0xC00
  344. #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
  345. # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
  346. # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
  347. #define SRBM_GFX_CNTL 0xE44
  348. #define PIPEID(x) ((x) << 0)
  349. #define MEID(x) ((x) << 2)
  350. #define VMID(x) ((x) << 4)
  351. #define QUEUEID(x) ((x) << 8)
  352. #define SRBM_STATUS2 0xE4C
  353. #define SDMA_BUSY (1 << 5)
  354. #define SDMA1_BUSY (1 << 6)
  355. #define SRBM_STATUS 0xE50
  356. #define UVD_RQ_PENDING (1 << 1)
  357. #define GRBM_RQ_PENDING (1 << 5)
  358. #define VMC_BUSY (1 << 8)
  359. #define MCB_BUSY (1 << 9)
  360. #define MCB_NON_DISPLAY_BUSY (1 << 10)
  361. #define MCC_BUSY (1 << 11)
  362. #define MCD_BUSY (1 << 12)
  363. #define SEM_BUSY (1 << 14)
  364. #define IH_BUSY (1 << 17)
  365. #define UVD_BUSY (1 << 19)
  366. #define SRBM_SOFT_RESET 0xE60
  367. #define SOFT_RESET_BIF (1 << 1)
  368. #define SOFT_RESET_R0PLL (1 << 4)
  369. #define SOFT_RESET_DC (1 << 5)
  370. #define SOFT_RESET_SDMA1 (1 << 6)
  371. #define SOFT_RESET_GRBM (1 << 8)
  372. #define SOFT_RESET_HDP (1 << 9)
  373. #define SOFT_RESET_IH (1 << 10)
  374. #define SOFT_RESET_MC (1 << 11)
  375. #define SOFT_RESET_ROM (1 << 14)
  376. #define SOFT_RESET_SEM (1 << 15)
  377. #define SOFT_RESET_VMC (1 << 17)
  378. #define SOFT_RESET_SDMA (1 << 20)
  379. #define SOFT_RESET_TST (1 << 21)
  380. #define SOFT_RESET_REGBB (1 << 22)
  381. #define SOFT_RESET_ORB (1 << 23)
  382. #define SOFT_RESET_VCE (1 << 24)
  383. #define VM_L2_CNTL 0x1400
  384. #define ENABLE_L2_CACHE (1 << 0)
  385. #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
  386. #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
  387. #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
  388. #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
  389. #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
  390. #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
  391. #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
  392. #define VM_L2_CNTL2 0x1404
  393. #define INVALIDATE_ALL_L1_TLBS (1 << 0)
  394. #define INVALIDATE_L2_CACHE (1 << 1)
  395. #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
  396. #define INVALIDATE_PTE_AND_PDE_CACHES 0
  397. #define INVALIDATE_ONLY_PTE_CACHES 1
  398. #define INVALIDATE_ONLY_PDE_CACHES 2
  399. #define VM_L2_CNTL3 0x1408
  400. #define BANK_SELECT(x) ((x) << 0)
  401. #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
  402. #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
  403. #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
  404. #define VM_L2_STATUS 0x140C
  405. #define L2_BUSY (1 << 0)
  406. #define VM_CONTEXT0_CNTL 0x1410
  407. #define ENABLE_CONTEXT (1 << 0)
  408. #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
  409. #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
  410. #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
  411. #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
  412. #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
  413. #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
  414. #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
  415. #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
  416. #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
  417. #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
  418. #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
  419. #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
  420. #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
  421. #define VM_CONTEXT1_CNTL 0x1414
  422. #define VM_CONTEXT0_CNTL2 0x1430
  423. #define VM_CONTEXT1_CNTL2 0x1434
  424. #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
  425. #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
  426. #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
  427. #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
  428. #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
  429. #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
  430. #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
  431. #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
  432. #define VM_INVALIDATE_REQUEST 0x1478
  433. #define VM_INVALIDATE_RESPONSE 0x147c
  434. #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
  435. #define PROTECTIONS_MASK (0xf << 0)
  436. #define PROTECTIONS_SHIFT 0
  437. /* bit 0: range
  438. * bit 1: pde0
  439. * bit 2: valid
  440. * bit 3: read
  441. * bit 4: write
  442. */
  443. #define MEMORY_CLIENT_ID_MASK (0xff << 12)
  444. #define MEMORY_CLIENT_ID_SHIFT 12
  445. #define MEMORY_CLIENT_RW_MASK (1 << 24)
  446. #define MEMORY_CLIENT_RW_SHIFT 24
  447. #define FAULT_VMID_MASK (0xf << 25)
  448. #define FAULT_VMID_SHIFT 25
  449. #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
  450. #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
  451. #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
  452. #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
  453. #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
  454. #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
  455. #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
  456. #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
  457. #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
  458. #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
  459. #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
  460. #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
  461. #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
  462. #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
  463. #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
  464. #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
  465. #define VM_L2_CG 0x15c0
  466. #define MC_CG_ENABLE (1 << 18)
  467. #define MC_LS_ENABLE (1 << 19)
  468. #define MC_SHARED_CHMAP 0x2004
  469. #define NOOFCHAN_SHIFT 12
  470. #define NOOFCHAN_MASK 0x0000f000
  471. #define MC_SHARED_CHREMAP 0x2008
  472. #define CHUB_CONTROL 0x1864
  473. #define BYPASS_VM (1 << 0)
  474. #define MC_VM_FB_LOCATION 0x2024
  475. #define MC_VM_AGP_TOP 0x2028
  476. #define MC_VM_AGP_BOT 0x202C
  477. #define MC_VM_AGP_BASE 0x2030
  478. #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
  479. #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
  480. #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
  481. #define MC_VM_MX_L1_TLB_CNTL 0x2064
  482. #define ENABLE_L1_TLB (1 << 0)
  483. #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
  484. #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
  485. #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
  486. #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
  487. #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
  488. #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
  489. #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
  490. #define MC_VM_FB_OFFSET 0x2068
  491. #define MC_SHARED_BLACKOUT_CNTL 0x20ac
  492. #define MC_HUB_MISC_HUB_CG 0x20b8
  493. #define MC_HUB_MISC_VM_CG 0x20bc
  494. #define MC_HUB_MISC_SIP_CG 0x20c0
  495. #define MC_XPB_CLK_GAT 0x2478
  496. #define MC_CITF_MISC_RD_CG 0x2648
  497. #define MC_CITF_MISC_WR_CG 0x264c
  498. #define MC_CITF_MISC_VM_CG 0x2650
  499. #define MC_ARB_RAMCFG 0x2760
  500. #define NOOFBANK_SHIFT 0
  501. #define NOOFBANK_MASK 0x00000003
  502. #define NOOFRANK_SHIFT 2
  503. #define NOOFRANK_MASK 0x00000004
  504. #define NOOFROWS_SHIFT 3
  505. #define NOOFROWS_MASK 0x00000038
  506. #define NOOFCOLS_SHIFT 6
  507. #define NOOFCOLS_MASK 0x000000C0
  508. #define CHANSIZE_SHIFT 8
  509. #define CHANSIZE_MASK 0x00000100
  510. #define NOOFGROUPS_SHIFT 12
  511. #define NOOFGROUPS_MASK 0x00001000
  512. #define MC_ARB_DRAM_TIMING 0x2774
  513. #define MC_ARB_DRAM_TIMING2 0x2778
  514. #define MC_ARB_BURST_TIME 0x2808
  515. #define STATE0(x) ((x) << 0)
  516. #define STATE0_MASK (0x1f << 0)
  517. #define STATE0_SHIFT 0
  518. #define STATE1(x) ((x) << 5)
  519. #define STATE1_MASK (0x1f << 5)
  520. #define STATE1_SHIFT 5
  521. #define STATE2(x) ((x) << 10)
  522. #define STATE2_MASK (0x1f << 10)
  523. #define STATE2_SHIFT 10
  524. #define STATE3(x) ((x) << 15)
  525. #define STATE3_MASK (0x1f << 15)
  526. #define STATE3_SHIFT 15
  527. #define MC_SEQ_RAS_TIMING 0x28a0
  528. #define MC_SEQ_CAS_TIMING 0x28a4
  529. #define MC_SEQ_MISC_TIMING 0x28a8
  530. #define MC_SEQ_MISC_TIMING2 0x28ac
  531. #define MC_SEQ_PMG_TIMING 0x28b0
  532. #define MC_SEQ_RD_CTL_D0 0x28b4
  533. #define MC_SEQ_RD_CTL_D1 0x28b8
  534. #define MC_SEQ_WR_CTL_D0 0x28bc
  535. #define MC_SEQ_WR_CTL_D1 0x28c0
  536. #define MC_SEQ_SUP_CNTL 0x28c8
  537. #define RUN_MASK (1 << 0)
  538. #define MC_SEQ_SUP_PGM 0x28cc
  539. #define MC_PMG_AUTO_CMD 0x28d0
  540. #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
  541. #define TRAIN_DONE_D0 (1 << 30)
  542. #define TRAIN_DONE_D1 (1 << 31)
  543. #define MC_IO_PAD_CNTL_D0 0x29d0
  544. #define MEM_FALL_OUT_CMD (1 << 8)
  545. #define MC_SEQ_MISC0 0x2a00
  546. #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
  547. #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
  548. #define MC_SEQ_MISC0_VEN_ID_VALUE 3
  549. #define MC_SEQ_MISC0_REV_ID_SHIFT 12
  550. #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
  551. #define MC_SEQ_MISC0_REV_ID_VALUE 1
  552. #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  553. #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
  554. #define MC_SEQ_MISC0_GDDR5_VALUE 5
  555. #define MC_SEQ_MISC1 0x2a04
  556. #define MC_SEQ_RESERVE_M 0x2a08
  557. #define MC_PMG_CMD_EMRS 0x2a0c
  558. #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
  559. #define MC_SEQ_IO_DEBUG_DATA 0x2a48
  560. #define MC_SEQ_MISC5 0x2a54
  561. #define MC_SEQ_MISC6 0x2a58
  562. #define MC_SEQ_MISC7 0x2a64
  563. #define MC_SEQ_RAS_TIMING_LP 0x2a6c
  564. #define MC_SEQ_CAS_TIMING_LP 0x2a70
  565. #define MC_SEQ_MISC_TIMING_LP 0x2a74
  566. #define MC_SEQ_MISC_TIMING2_LP 0x2a78
  567. #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
  568. #define MC_SEQ_WR_CTL_D1_LP 0x2a80
  569. #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
  570. #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
  571. #define MC_PMG_CMD_MRS 0x2aac
  572. #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
  573. #define MC_SEQ_RD_CTL_D1_LP 0x2b20
  574. #define MC_PMG_CMD_MRS1 0x2b44
  575. #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
  576. #define MC_SEQ_PMG_TIMING_LP 0x2b4c
  577. #define MC_SEQ_WR_CTL_2 0x2b54
  578. #define MC_SEQ_WR_CTL_2_LP 0x2b58
  579. #define MC_PMG_CMD_MRS2 0x2b5c
  580. #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
  581. #define MCLK_PWRMGT_CNTL 0x2ba0
  582. # define DLL_SPEED(x) ((x) << 0)
  583. # define DLL_SPEED_MASK (0x1f << 0)
  584. # define DLL_READY (1 << 6)
  585. # define MC_INT_CNTL (1 << 7)
  586. # define MRDCK0_PDNB (1 << 8)
  587. # define MRDCK1_PDNB (1 << 9)
  588. # define MRDCK0_RESET (1 << 16)
  589. # define MRDCK1_RESET (1 << 17)
  590. # define DLL_READY_READ (1 << 24)
  591. #define DLL_CNTL 0x2ba4
  592. # define MRDCK0_BYPASS (1 << 24)
  593. # define MRDCK1_BYPASS (1 << 25)
  594. #define MPLL_FUNC_CNTL 0x2bb4
  595. #define BWCTRL(x) ((x) << 20)
  596. #define BWCTRL_MASK (0xff << 20)
  597. #define MPLL_FUNC_CNTL_1 0x2bb8
  598. #define VCO_MODE(x) ((x) << 0)
  599. #define VCO_MODE_MASK (3 << 0)
  600. #define CLKFRAC(x) ((x) << 4)
  601. #define CLKFRAC_MASK (0xfff << 4)
  602. #define CLKF(x) ((x) << 16)
  603. #define CLKF_MASK (0xfff << 16)
  604. #define MPLL_FUNC_CNTL_2 0x2bbc
  605. #define MPLL_AD_FUNC_CNTL 0x2bc0
  606. #define YCLK_POST_DIV(x) ((x) << 0)
  607. #define YCLK_POST_DIV_MASK (7 << 0)
  608. #define MPLL_DQ_FUNC_CNTL 0x2bc4
  609. #define YCLK_SEL(x) ((x) << 4)
  610. #define YCLK_SEL_MASK (1 << 4)
  611. #define MPLL_SS1 0x2bcc
  612. #define CLKV(x) ((x) << 0)
  613. #define CLKV_MASK (0x3ffffff << 0)
  614. #define MPLL_SS2 0x2bd0
  615. #define CLKS(x) ((x) << 0)
  616. #define CLKS_MASK (0xfff << 0)
  617. #define HDP_HOST_PATH_CNTL 0x2C00
  618. #define CLOCK_GATING_DIS (1 << 23)
  619. #define HDP_NONSURFACE_BASE 0x2C04
  620. #define HDP_NONSURFACE_INFO 0x2C08
  621. #define HDP_NONSURFACE_SIZE 0x2C0C
  622. #define HDP_ADDR_CONFIG 0x2F48
  623. #define HDP_MISC_CNTL 0x2F4C
  624. #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
  625. #define HDP_MEM_POWER_LS 0x2F50
  626. #define HDP_LS_ENABLE (1 << 0)
  627. #define ATC_MISC_CG 0x3350
  628. #define MC_SEQ_CNTL_3 0x3600
  629. # define CAC_EN (1 << 31)
  630. #define MC_SEQ_G5PDX_CTRL 0x3604
  631. #define MC_SEQ_G5PDX_CTRL_LP 0x3608
  632. #define MC_SEQ_G5PDX_CMD0 0x360c
  633. #define MC_SEQ_G5PDX_CMD0_LP 0x3610
  634. #define MC_SEQ_G5PDX_CMD1 0x3614
  635. #define MC_SEQ_G5PDX_CMD1_LP 0x3618
  636. #define MC_SEQ_PMG_DVS_CTL 0x3628
  637. #define MC_SEQ_PMG_DVS_CTL_LP 0x362c
  638. #define MC_SEQ_PMG_DVS_CMD 0x3630
  639. #define MC_SEQ_PMG_DVS_CMD_LP 0x3634
  640. #define MC_SEQ_DLL_STBY 0x3638
  641. #define MC_SEQ_DLL_STBY_LP 0x363c
  642. #define IH_RB_CNTL 0x3e00
  643. # define IH_RB_ENABLE (1 << 0)
  644. # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
  645. # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
  646. # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
  647. # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
  648. # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
  649. # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
  650. #define IH_RB_BASE 0x3e04
  651. #define IH_RB_RPTR 0x3e08
  652. #define IH_RB_WPTR 0x3e0c
  653. # define RB_OVERFLOW (1 << 0)
  654. # define WPTR_OFFSET_MASK 0x3fffc
  655. #define IH_RB_WPTR_ADDR_HI 0x3e10
  656. #define IH_RB_WPTR_ADDR_LO 0x3e14
  657. #define IH_CNTL 0x3e18
  658. # define ENABLE_INTR (1 << 0)
  659. # define IH_MC_SWAP(x) ((x) << 1)
  660. # define IH_MC_SWAP_NONE 0
  661. # define IH_MC_SWAP_16BIT 1
  662. # define IH_MC_SWAP_32BIT 2
  663. # define IH_MC_SWAP_64BIT 3
  664. # define RPTR_REARM (1 << 4)
  665. # define MC_WRREQ_CREDIT(x) ((x) << 15)
  666. # define MC_WR_CLEAN_CNT(x) ((x) << 20)
  667. # define MC_VMID(x) ((x) << 25)
  668. #define BIF_LNCNT_RESET 0x5220
  669. # define RESET_LNCNT_EN (1 << 0)
  670. #define CONFIG_MEMSIZE 0x5428
  671. #define INTERRUPT_CNTL 0x5468
  672. # define IH_DUMMY_RD_OVERRIDE (1 << 0)
  673. # define IH_DUMMY_RD_EN (1 << 1)
  674. # define IH_REQ_NONSNOOP_EN (1 << 3)
  675. # define GEN_IH_INT_EN (1 << 8)
  676. #define INTERRUPT_CNTL2 0x546c
  677. #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
  678. #define BIF_FB_EN 0x5490
  679. #define FB_READ_EN (1 << 0)
  680. #define FB_WRITE_EN (1 << 1)
  681. #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
  682. #define GPU_HDP_FLUSH_REQ 0x54DC
  683. #define GPU_HDP_FLUSH_DONE 0x54E0
  684. #define CP0 (1 << 0)
  685. #define CP1 (1 << 1)
  686. #define CP2 (1 << 2)
  687. #define CP3 (1 << 3)
  688. #define CP4 (1 << 4)
  689. #define CP5 (1 << 5)
  690. #define CP6 (1 << 6)
  691. #define CP7 (1 << 7)
  692. #define CP8 (1 << 8)
  693. #define CP9 (1 << 9)
  694. #define SDMA0 (1 << 10)
  695. #define SDMA1 (1 << 11)
  696. /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
  697. #define LB_MEMORY_CTRL 0x6b04
  698. #define LB_MEMORY_SIZE(x) ((x) << 0)
  699. #define LB_MEMORY_CONFIG(x) ((x) << 20)
  700. #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
  701. # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
  702. #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
  703. # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
  704. # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
  705. /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
  706. #define LB_VLINE_STATUS 0x6b24
  707. # define VLINE_OCCURRED (1 << 0)
  708. # define VLINE_ACK (1 << 4)
  709. # define VLINE_STAT (1 << 12)
  710. # define VLINE_INTERRUPT (1 << 16)
  711. # define VLINE_INTERRUPT_TYPE (1 << 17)
  712. /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
  713. #define LB_VBLANK_STATUS 0x6b2c
  714. # define VBLANK_OCCURRED (1 << 0)
  715. # define VBLANK_ACK (1 << 4)
  716. # define VBLANK_STAT (1 << 12)
  717. # define VBLANK_INTERRUPT (1 << 16)
  718. # define VBLANK_INTERRUPT_TYPE (1 << 17)
  719. /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
  720. #define LB_INTERRUPT_MASK 0x6b20
  721. # define VBLANK_INTERRUPT_MASK (1 << 0)
  722. # define VLINE_INTERRUPT_MASK (1 << 4)
  723. # define VLINE2_INTERRUPT_MASK (1 << 8)
  724. #define DISP_INTERRUPT_STATUS 0x60f4
  725. # define LB_D1_VLINE_INTERRUPT (1 << 2)
  726. # define LB_D1_VBLANK_INTERRUPT (1 << 3)
  727. # define DC_HPD1_INTERRUPT (1 << 17)
  728. # define DC_HPD1_RX_INTERRUPT (1 << 18)
  729. # define DACA_AUTODETECT_INTERRUPT (1 << 22)
  730. # define DACB_AUTODETECT_INTERRUPT (1 << 23)
  731. # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
  732. # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
  733. #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
  734. # define LB_D2_VLINE_INTERRUPT (1 << 2)
  735. # define LB_D2_VBLANK_INTERRUPT (1 << 3)
  736. # define DC_HPD2_INTERRUPT (1 << 17)
  737. # define DC_HPD2_RX_INTERRUPT (1 << 18)
  738. # define DISP_TIMER_INTERRUPT (1 << 24)
  739. #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
  740. # define LB_D3_VLINE_INTERRUPT (1 << 2)
  741. # define LB_D3_VBLANK_INTERRUPT (1 << 3)
  742. # define DC_HPD3_INTERRUPT (1 << 17)
  743. # define DC_HPD3_RX_INTERRUPT (1 << 18)
  744. #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
  745. # define LB_D4_VLINE_INTERRUPT (1 << 2)
  746. # define LB_D4_VBLANK_INTERRUPT (1 << 3)
  747. # define DC_HPD4_INTERRUPT (1 << 17)
  748. # define DC_HPD4_RX_INTERRUPT (1 << 18)
  749. #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
  750. # define LB_D5_VLINE_INTERRUPT (1 << 2)
  751. # define LB_D5_VBLANK_INTERRUPT (1 << 3)
  752. # define DC_HPD5_INTERRUPT (1 << 17)
  753. # define DC_HPD5_RX_INTERRUPT (1 << 18)
  754. #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
  755. # define LB_D6_VLINE_INTERRUPT (1 << 2)
  756. # define LB_D6_VBLANK_INTERRUPT (1 << 3)
  757. # define DC_HPD6_INTERRUPT (1 << 17)
  758. # define DC_HPD6_RX_INTERRUPT (1 << 18)
  759. #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
  760. #define DAC_AUTODETECT_INT_CONTROL 0x67c8
  761. #define DC_HPD1_INT_STATUS 0x601c
  762. #define DC_HPD2_INT_STATUS 0x6028
  763. #define DC_HPD3_INT_STATUS 0x6034
  764. #define DC_HPD4_INT_STATUS 0x6040
  765. #define DC_HPD5_INT_STATUS 0x604c
  766. #define DC_HPD6_INT_STATUS 0x6058
  767. # define DC_HPDx_INT_STATUS (1 << 0)
  768. # define DC_HPDx_SENSE (1 << 1)
  769. # define DC_HPDx_SENSE_DELAYED (1 << 4)
  770. # define DC_HPDx_RX_INT_STATUS (1 << 8)
  771. #define DC_HPD1_INT_CONTROL 0x6020
  772. #define DC_HPD2_INT_CONTROL 0x602c
  773. #define DC_HPD3_INT_CONTROL 0x6038
  774. #define DC_HPD4_INT_CONTROL 0x6044
  775. #define DC_HPD5_INT_CONTROL 0x6050
  776. #define DC_HPD6_INT_CONTROL 0x605c
  777. # define DC_HPDx_INT_ACK (1 << 0)
  778. # define DC_HPDx_INT_POLARITY (1 << 8)
  779. # define DC_HPDx_INT_EN (1 << 16)
  780. # define DC_HPDx_RX_INT_ACK (1 << 20)
  781. # define DC_HPDx_RX_INT_EN (1 << 24)
  782. #define DC_HPD1_CONTROL 0x6024
  783. #define DC_HPD2_CONTROL 0x6030
  784. #define DC_HPD3_CONTROL 0x603c
  785. #define DC_HPD4_CONTROL 0x6048
  786. #define DC_HPD5_CONTROL 0x6054
  787. #define DC_HPD6_CONTROL 0x6060
  788. # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
  789. # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
  790. # define DC_HPDx_EN (1 << 28)
  791. #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
  792. # define STUTTER_ENABLE (1 << 0)
  793. #define GRBM_CNTL 0x8000
  794. #define GRBM_READ_TIMEOUT(x) ((x) << 0)
  795. #define GRBM_STATUS2 0x8008
  796. #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
  797. #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
  798. #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
  799. #define ME1PIPE0_RQ_PENDING (1 << 6)
  800. #define ME1PIPE1_RQ_PENDING (1 << 7)
  801. #define ME1PIPE2_RQ_PENDING (1 << 8)
  802. #define ME1PIPE3_RQ_PENDING (1 << 9)
  803. #define ME2PIPE0_RQ_PENDING (1 << 10)
  804. #define ME2PIPE1_RQ_PENDING (1 << 11)
  805. #define ME2PIPE2_RQ_PENDING (1 << 12)
  806. #define ME2PIPE3_RQ_PENDING (1 << 13)
  807. #define RLC_RQ_PENDING (1 << 14)
  808. #define RLC_BUSY (1 << 24)
  809. #define TC_BUSY (1 << 25)
  810. #define CPF_BUSY (1 << 28)
  811. #define CPC_BUSY (1 << 29)
  812. #define CPG_BUSY (1 << 30)
  813. #define GRBM_STATUS 0x8010
  814. #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
  815. #define SRBM_RQ_PENDING (1 << 5)
  816. #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
  817. #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
  818. #define GDS_DMA_RQ_PENDING (1 << 9)
  819. #define DB_CLEAN (1 << 12)
  820. #define CB_CLEAN (1 << 13)
  821. #define TA_BUSY (1 << 14)
  822. #define GDS_BUSY (1 << 15)
  823. #define WD_BUSY_NO_DMA (1 << 16)
  824. #define VGT_BUSY (1 << 17)
  825. #define IA_BUSY_NO_DMA (1 << 18)
  826. #define IA_BUSY (1 << 19)
  827. #define SX_BUSY (1 << 20)
  828. #define WD_BUSY (1 << 21)
  829. #define SPI_BUSY (1 << 22)
  830. #define BCI_BUSY (1 << 23)
  831. #define SC_BUSY (1 << 24)
  832. #define PA_BUSY (1 << 25)
  833. #define DB_BUSY (1 << 26)
  834. #define CP_COHERENCY_BUSY (1 << 28)
  835. #define CP_BUSY (1 << 29)
  836. #define CB_BUSY (1 << 30)
  837. #define GUI_ACTIVE (1 << 31)
  838. #define GRBM_STATUS_SE0 0x8014
  839. #define GRBM_STATUS_SE1 0x8018
  840. #define GRBM_STATUS_SE2 0x8038
  841. #define GRBM_STATUS_SE3 0x803C
  842. #define SE_DB_CLEAN (1 << 1)
  843. #define SE_CB_CLEAN (1 << 2)
  844. #define SE_BCI_BUSY (1 << 22)
  845. #define SE_VGT_BUSY (1 << 23)
  846. #define SE_PA_BUSY (1 << 24)
  847. #define SE_TA_BUSY (1 << 25)
  848. #define SE_SX_BUSY (1 << 26)
  849. #define SE_SPI_BUSY (1 << 27)
  850. #define SE_SC_BUSY (1 << 29)
  851. #define SE_DB_BUSY (1 << 30)
  852. #define SE_CB_BUSY (1 << 31)
  853. #define GRBM_SOFT_RESET 0x8020
  854. #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
  855. #define SOFT_RESET_RLC (1 << 2) /* RLC */
  856. #define SOFT_RESET_GFX (1 << 16) /* GFX */
  857. #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
  858. #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
  859. #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
  860. #define GRBM_INT_CNTL 0x8060
  861. # define RDERR_INT_ENABLE (1 << 0)
  862. # define GUI_IDLE_INT_ENABLE (1 << 19)
  863. #define CP_CPC_STATUS 0x8210
  864. #define CP_CPC_BUSY_STAT 0x8214
  865. #define CP_CPC_STALLED_STAT1 0x8218
  866. #define CP_CPF_STATUS 0x821c
  867. #define CP_CPF_BUSY_STAT 0x8220
  868. #define CP_CPF_STALLED_STAT1 0x8224
  869. #define CP_MEC_CNTL 0x8234
  870. #define MEC_ME2_HALT (1 << 28)
  871. #define MEC_ME1_HALT (1 << 30)
  872. #define CP_MEC_CNTL 0x8234
  873. #define MEC_ME2_HALT (1 << 28)
  874. #define MEC_ME1_HALT (1 << 30)
  875. #define CP_STALLED_STAT3 0x8670
  876. #define CP_STALLED_STAT1 0x8674
  877. #define CP_STALLED_STAT2 0x8678
  878. #define CP_STAT 0x8680
  879. #define CP_ME_CNTL 0x86D8
  880. #define CP_CE_HALT (1 << 24)
  881. #define CP_PFP_HALT (1 << 26)
  882. #define CP_ME_HALT (1 << 28)
  883. #define CP_RB0_RPTR 0x8700
  884. #define CP_RB_WPTR_DELAY 0x8704
  885. #define CP_RB_WPTR_POLL_CNTL 0x8708
  886. #define IDLE_POLL_COUNT(x) ((x) << 16)
  887. #define IDLE_POLL_COUNT_MASK (0xffff << 16)
  888. #define CP_MEQ_THRESHOLDS 0x8764
  889. #define MEQ1_START(x) ((x) << 0)
  890. #define MEQ2_START(x) ((x) << 8)
  891. #define VGT_VTX_VECT_EJECT_REG 0x88B0
  892. #define VGT_CACHE_INVALIDATION 0x88C4
  893. #define CACHE_INVALIDATION(x) ((x) << 0)
  894. #define VC_ONLY 0
  895. #define TC_ONLY 1
  896. #define VC_AND_TC 2
  897. #define AUTO_INVLD_EN(x) ((x) << 6)
  898. #define NO_AUTO 0
  899. #define ES_AUTO 1
  900. #define GS_AUTO 2
  901. #define ES_AND_GS_AUTO 3
  902. #define VGT_GS_VERTEX_REUSE 0x88D4
  903. #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
  904. #define INACTIVE_CUS_MASK 0xFFFF0000
  905. #define INACTIVE_CUS_SHIFT 16
  906. #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
  907. #define PA_CL_ENHANCE 0x8A14
  908. #define CLIP_VTX_REORDER_ENA (1 << 0)
  909. #define NUM_CLIP_SEQ(x) ((x) << 1)
  910. #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
  911. #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
  912. #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
  913. #define PA_SC_FIFO_SIZE 0x8BCC
  914. #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
  915. #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
  916. #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
  917. #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
  918. #define PA_SC_ENHANCE 0x8BF0
  919. #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
  920. #define DISABLE_PA_SC_GUIDANCE (1 << 13)
  921. #define SQ_CONFIG 0x8C00
  922. #define SH_MEM_BASES 0x8C28
  923. /* if PTR32, these are the bases for scratch and lds */
  924. #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
  925. #define SHARED_BASE(x) ((x) << 16) /* LDS */
  926. #define SH_MEM_APE1_BASE 0x8C2C
  927. /* if PTR32, this is the base location of GPUVM */
  928. #define SH_MEM_APE1_LIMIT 0x8C30
  929. /* if PTR32, this is the upper limit of GPUVM */
  930. #define SH_MEM_CONFIG 0x8C34
  931. #define PTR32 (1 << 0)
  932. #define ALIGNMENT_MODE(x) ((x) << 2)
  933. #define SH_MEM_ALIGNMENT_MODE_DWORD 0
  934. #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
  935. #define SH_MEM_ALIGNMENT_MODE_STRICT 2
  936. #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
  937. #define DEFAULT_MTYPE(x) ((x) << 4)
  938. #define APE1_MTYPE(x) ((x) << 7)
  939. #define SX_DEBUG_1 0x9060
  940. #define SPI_CONFIG_CNTL 0x9100
  941. #define SPI_CONFIG_CNTL_1 0x913C
  942. #define VTX_DONE_DELAY(x) ((x) << 0)
  943. #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
  944. #define TA_CNTL_AUX 0x9508
  945. #define DB_DEBUG 0x9830
  946. #define DB_DEBUG2 0x9834
  947. #define DB_DEBUG3 0x9838
  948. #define CC_RB_BACKEND_DISABLE 0x98F4
  949. #define BACKEND_DISABLE(x) ((x) << 16)
  950. #define GB_ADDR_CONFIG 0x98F8
  951. #define NUM_PIPES(x) ((x) << 0)
  952. #define NUM_PIPES_MASK 0x00000007
  953. #define NUM_PIPES_SHIFT 0
  954. #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
  955. #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
  956. #define PIPE_INTERLEAVE_SIZE_SHIFT 4
  957. #define NUM_SHADER_ENGINES(x) ((x) << 12)
  958. #define NUM_SHADER_ENGINES_MASK 0x00003000
  959. #define NUM_SHADER_ENGINES_SHIFT 12
  960. #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
  961. #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
  962. #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
  963. #define ROW_SIZE(x) ((x) << 28)
  964. #define ROW_SIZE_MASK 0x30000000
  965. #define ROW_SIZE_SHIFT 28
  966. #define GB_TILE_MODE0 0x9910
  967. # define ARRAY_MODE(x) ((x) << 2)
  968. # define ARRAY_LINEAR_GENERAL 0
  969. # define ARRAY_LINEAR_ALIGNED 1
  970. # define ARRAY_1D_TILED_THIN1 2
  971. # define ARRAY_2D_TILED_THIN1 4
  972. # define ARRAY_PRT_TILED_THIN1 5
  973. # define ARRAY_PRT_2D_TILED_THIN1 6
  974. # define PIPE_CONFIG(x) ((x) << 6)
  975. # define ADDR_SURF_P2 0
  976. # define ADDR_SURF_P4_8x16 4
  977. # define ADDR_SURF_P4_16x16 5
  978. # define ADDR_SURF_P4_16x32 6
  979. # define ADDR_SURF_P4_32x32 7
  980. # define ADDR_SURF_P8_16x16_8x16 8
  981. # define ADDR_SURF_P8_16x32_8x16 9
  982. # define ADDR_SURF_P8_32x32_8x16 10
  983. # define ADDR_SURF_P8_16x32_16x16 11
  984. # define ADDR_SURF_P8_32x32_16x16 12
  985. # define ADDR_SURF_P8_32x32_16x32 13
  986. # define ADDR_SURF_P8_32x64_32x32 14
  987. # define TILE_SPLIT(x) ((x) << 11)
  988. # define ADDR_SURF_TILE_SPLIT_64B 0
  989. # define ADDR_SURF_TILE_SPLIT_128B 1
  990. # define ADDR_SURF_TILE_SPLIT_256B 2
  991. # define ADDR_SURF_TILE_SPLIT_512B 3
  992. # define ADDR_SURF_TILE_SPLIT_1KB 4
  993. # define ADDR_SURF_TILE_SPLIT_2KB 5
  994. # define ADDR_SURF_TILE_SPLIT_4KB 6
  995. # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
  996. # define ADDR_SURF_DISPLAY_MICRO_TILING 0
  997. # define ADDR_SURF_THIN_MICRO_TILING 1
  998. # define ADDR_SURF_DEPTH_MICRO_TILING 2
  999. # define ADDR_SURF_ROTATED_MICRO_TILING 3
  1000. # define SAMPLE_SPLIT(x) ((x) << 25)
  1001. # define ADDR_SURF_SAMPLE_SPLIT_1 0
  1002. # define ADDR_SURF_SAMPLE_SPLIT_2 1
  1003. # define ADDR_SURF_SAMPLE_SPLIT_4 2
  1004. # define ADDR_SURF_SAMPLE_SPLIT_8 3
  1005. #define GB_MACROTILE_MODE0 0x9990
  1006. # define BANK_WIDTH(x) ((x) << 0)
  1007. # define ADDR_SURF_BANK_WIDTH_1 0
  1008. # define ADDR_SURF_BANK_WIDTH_2 1
  1009. # define ADDR_SURF_BANK_WIDTH_4 2
  1010. # define ADDR_SURF_BANK_WIDTH_8 3
  1011. # define BANK_HEIGHT(x) ((x) << 2)
  1012. # define ADDR_SURF_BANK_HEIGHT_1 0
  1013. # define ADDR_SURF_BANK_HEIGHT_2 1
  1014. # define ADDR_SURF_BANK_HEIGHT_4 2
  1015. # define ADDR_SURF_BANK_HEIGHT_8 3
  1016. # define MACRO_TILE_ASPECT(x) ((x) << 4)
  1017. # define ADDR_SURF_MACRO_ASPECT_1 0
  1018. # define ADDR_SURF_MACRO_ASPECT_2 1
  1019. # define ADDR_SURF_MACRO_ASPECT_4 2
  1020. # define ADDR_SURF_MACRO_ASPECT_8 3
  1021. # define NUM_BANKS(x) ((x) << 6)
  1022. # define ADDR_SURF_2_BANK 0
  1023. # define ADDR_SURF_4_BANK 1
  1024. # define ADDR_SURF_8_BANK 2
  1025. # define ADDR_SURF_16_BANK 3
  1026. #define CB_HW_CONTROL 0x9A10
  1027. #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
  1028. #define BACKEND_DISABLE_MASK 0x00FF0000
  1029. #define BACKEND_DISABLE_SHIFT 16
  1030. #define TCP_CHAN_STEER_LO 0xac0c
  1031. #define TCP_CHAN_STEER_HI 0xac10
  1032. #define TC_CFG_L1_LOAD_POLICY0 0xAC68
  1033. #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
  1034. #define TC_CFG_L1_STORE_POLICY 0xAC70
  1035. #define TC_CFG_L2_LOAD_POLICY0 0xAC74
  1036. #define TC_CFG_L2_LOAD_POLICY1 0xAC78
  1037. #define TC_CFG_L2_STORE_POLICY0 0xAC7C
  1038. #define TC_CFG_L2_STORE_POLICY1 0xAC80
  1039. #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
  1040. #define TC_CFG_L1_VOLATILE 0xAC88
  1041. #define TC_CFG_L2_VOLATILE 0xAC8C
  1042. #define CP_RB0_BASE 0xC100
  1043. #define CP_RB0_CNTL 0xC104
  1044. #define RB_BUFSZ(x) ((x) << 0)
  1045. #define RB_BLKSZ(x) ((x) << 8)
  1046. #define BUF_SWAP_32BIT (2 << 16)
  1047. #define RB_NO_UPDATE (1 << 27)
  1048. #define RB_RPTR_WR_ENA (1 << 31)
  1049. #define CP_RB0_RPTR_ADDR 0xC10C
  1050. #define RB_RPTR_SWAP_32BIT (2 << 0)
  1051. #define CP_RB0_RPTR_ADDR_HI 0xC110
  1052. #define CP_RB0_WPTR 0xC114
  1053. #define CP_DEVICE_ID 0xC12C
  1054. #define CP_ENDIAN_SWAP 0xC140
  1055. #define CP_RB_VMID 0xC144
  1056. #define CP_PFP_UCODE_ADDR 0xC150
  1057. #define CP_PFP_UCODE_DATA 0xC154
  1058. #define CP_ME_RAM_RADDR 0xC158
  1059. #define CP_ME_RAM_WADDR 0xC15C
  1060. #define CP_ME_RAM_DATA 0xC160
  1061. #define CP_CE_UCODE_ADDR 0xC168
  1062. #define CP_CE_UCODE_DATA 0xC16C
  1063. #define CP_MEC_ME1_UCODE_ADDR 0xC170
  1064. #define CP_MEC_ME1_UCODE_DATA 0xC174
  1065. #define CP_MEC_ME2_UCODE_ADDR 0xC178
  1066. #define CP_MEC_ME2_UCODE_DATA 0xC17C
  1067. #define CP_INT_CNTL_RING0 0xC1A8
  1068. # define CNTX_BUSY_INT_ENABLE (1 << 19)
  1069. # define CNTX_EMPTY_INT_ENABLE (1 << 20)
  1070. # define PRIV_INSTR_INT_ENABLE (1 << 22)
  1071. # define PRIV_REG_INT_ENABLE (1 << 23)
  1072. # define TIME_STAMP_INT_ENABLE (1 << 26)
  1073. # define CP_RINGID2_INT_ENABLE (1 << 29)
  1074. # define CP_RINGID1_INT_ENABLE (1 << 30)
  1075. # define CP_RINGID0_INT_ENABLE (1 << 31)
  1076. #define CP_INT_STATUS_RING0 0xC1B4
  1077. # define PRIV_INSTR_INT_STAT (1 << 22)
  1078. # define PRIV_REG_INT_STAT (1 << 23)
  1079. # define TIME_STAMP_INT_STAT (1 << 26)
  1080. # define CP_RINGID2_INT_STAT (1 << 29)
  1081. # define CP_RINGID1_INT_STAT (1 << 30)
  1082. # define CP_RINGID0_INT_STAT (1 << 31)
  1083. #define CP_MEM_SLP_CNTL 0xC1E4
  1084. # define CP_MEM_LS_EN (1 << 0)
  1085. #define CP_CPF_DEBUG 0xC200
  1086. #define CP_PQ_WPTR_POLL_CNTL 0xC20C
  1087. #define WPTR_POLL_EN (1 << 31)
  1088. #define CP_ME1_PIPE0_INT_CNTL 0xC214
  1089. #define CP_ME1_PIPE1_INT_CNTL 0xC218
  1090. #define CP_ME1_PIPE2_INT_CNTL 0xC21C
  1091. #define CP_ME1_PIPE3_INT_CNTL 0xC220
  1092. #define CP_ME2_PIPE0_INT_CNTL 0xC224
  1093. #define CP_ME2_PIPE1_INT_CNTL 0xC228
  1094. #define CP_ME2_PIPE2_INT_CNTL 0xC22C
  1095. #define CP_ME2_PIPE3_INT_CNTL 0xC230
  1096. # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
  1097. # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
  1098. # define PRIV_REG_INT_ENABLE (1 << 23)
  1099. # define TIME_STAMP_INT_ENABLE (1 << 26)
  1100. # define GENERIC2_INT_ENABLE (1 << 29)
  1101. # define GENERIC1_INT_ENABLE (1 << 30)
  1102. # define GENERIC0_INT_ENABLE (1 << 31)
  1103. #define CP_ME1_PIPE0_INT_STATUS 0xC214
  1104. #define CP_ME1_PIPE1_INT_STATUS 0xC218
  1105. #define CP_ME1_PIPE2_INT_STATUS 0xC21C
  1106. #define CP_ME1_PIPE3_INT_STATUS 0xC220
  1107. #define CP_ME2_PIPE0_INT_STATUS 0xC224
  1108. #define CP_ME2_PIPE1_INT_STATUS 0xC228
  1109. #define CP_ME2_PIPE2_INT_STATUS 0xC22C
  1110. #define CP_ME2_PIPE3_INT_STATUS 0xC230
  1111. # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
  1112. # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
  1113. # define PRIV_REG_INT_STATUS (1 << 23)
  1114. # define TIME_STAMP_INT_STATUS (1 << 26)
  1115. # define GENERIC2_INT_STATUS (1 << 29)
  1116. # define GENERIC1_INT_STATUS (1 << 30)
  1117. # define GENERIC0_INT_STATUS (1 << 31)
  1118. #define CP_MAX_CONTEXT 0xC2B8
  1119. #define CP_RB0_BASE_HI 0xC2C4
  1120. #define RLC_CNTL 0xC300
  1121. # define RLC_ENABLE (1 << 0)
  1122. #define RLC_MC_CNTL 0xC30C
  1123. #define RLC_MEM_SLP_CNTL 0xC318
  1124. # define RLC_MEM_LS_EN (1 << 0)
  1125. #define RLC_LB_CNTR_MAX 0xC348
  1126. #define RLC_LB_CNTL 0xC364
  1127. # define LOAD_BALANCE_ENABLE (1 << 0)
  1128. #define RLC_LB_CNTR_INIT 0xC36C
  1129. #define RLC_SAVE_AND_RESTORE_BASE 0xC374
  1130. #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
  1131. #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
  1132. #define RLC_PG_DELAY_2 0xC37C
  1133. #define RLC_GPM_UCODE_ADDR 0xC388
  1134. #define RLC_GPM_UCODE_DATA 0xC38C
  1135. #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
  1136. #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
  1137. #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
  1138. #define RLC_UCODE_CNTL 0xC39C
  1139. #define RLC_GPM_STAT 0xC400
  1140. # define RLC_GPM_BUSY (1 << 0)
  1141. # define GFX_POWER_STATUS (1 << 1)
  1142. # define GFX_CLOCK_STATUS (1 << 2)
  1143. #define RLC_PG_CNTL 0xC40C
  1144. # define GFX_PG_ENABLE (1 << 0)
  1145. # define GFX_PG_SRC (1 << 1)
  1146. # define DYN_PER_CU_PG_ENABLE (1 << 2)
  1147. # define STATIC_PER_CU_PG_ENABLE (1 << 3)
  1148. # define DISABLE_GDS_PG (1 << 13)
  1149. # define DISABLE_CP_PG (1 << 15)
  1150. # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
  1151. # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
  1152. #define RLC_CGTT_MGCG_OVERRIDE 0xC420
  1153. #define RLC_CGCG_CGLS_CTRL 0xC424
  1154. # define CGCG_EN (1 << 0)
  1155. # define CGLS_EN (1 << 1)
  1156. #define RLC_PG_DELAY 0xC434
  1157. #define RLC_LB_INIT_CU_MASK 0xC43C
  1158. #define RLC_LB_PARAMS 0xC444
  1159. #define RLC_PG_AO_CU_MASK 0xC44C
  1160. #define RLC_MAX_PG_CU 0xC450
  1161. # define MAX_PU_CU(x) ((x) << 0)
  1162. # define MAX_PU_CU_MASK (0xff << 0)
  1163. #define RLC_AUTO_PG_CTRL 0xC454
  1164. # define AUTO_PG_EN (1 << 0)
  1165. # define GRBM_REG_SGIT(x) ((x) << 3)
  1166. # define GRBM_REG_SGIT_MASK (0xffff << 3)
  1167. #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
  1168. #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
  1169. #define RLC_SERDES_WR_CTRL 0xC47C
  1170. #define BPM_ADDR(x) ((x) << 0)
  1171. #define BPM_ADDR_MASK (0xff << 0)
  1172. #define CGLS_ENABLE (1 << 16)
  1173. #define CGCG_OVERRIDE_0 (1 << 20)
  1174. #define MGCG_OVERRIDE_0 (1 << 22)
  1175. #define MGCG_OVERRIDE_1 (1 << 23)
  1176. #define RLC_SERDES_CU_MASTER_BUSY 0xC484
  1177. #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
  1178. # define SE_MASTER_BUSY_MASK 0x0000ffff
  1179. # define GC_MASTER_BUSY (1 << 16)
  1180. # define TC0_MASTER_BUSY (1 << 17)
  1181. # define TC1_MASTER_BUSY (1 << 18)
  1182. #define RLC_GPM_SCRATCH_ADDR 0xC4B0
  1183. #define RLC_GPM_SCRATCH_DATA 0xC4B4
  1184. #define RLC_GPR_REG2 0xC4E8
  1185. #define REQ 0x00000001
  1186. #define MESSAGE(x) ((x) << 1)
  1187. #define MESSAGE_MASK 0x0000001e
  1188. #define MSG_ENTER_RLC_SAFE_MODE 1
  1189. #define MSG_EXIT_RLC_SAFE_MODE 0
  1190. #define CP_HPD_EOP_BASE_ADDR 0xC904
  1191. #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
  1192. #define CP_HPD_EOP_VMID 0xC90C
  1193. #define CP_HPD_EOP_CONTROL 0xC910
  1194. #define EOP_SIZE(x) ((x) << 0)
  1195. #define EOP_SIZE_MASK (0x3f << 0)
  1196. #define CP_MQD_BASE_ADDR 0xC914
  1197. #define CP_MQD_BASE_ADDR_HI 0xC918
  1198. #define CP_HQD_ACTIVE 0xC91C
  1199. #define CP_HQD_VMID 0xC920
  1200. #define CP_HQD_PQ_BASE 0xC934
  1201. #define CP_HQD_PQ_BASE_HI 0xC938
  1202. #define CP_HQD_PQ_RPTR 0xC93C
  1203. #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
  1204. #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
  1205. #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
  1206. #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
  1207. #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
  1208. #define DOORBELL_OFFSET(x) ((x) << 2)
  1209. #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
  1210. #define DOORBELL_SOURCE (1 << 28)
  1211. #define DOORBELL_SCHD_HIT (1 << 29)
  1212. #define DOORBELL_EN (1 << 30)
  1213. #define DOORBELL_HIT (1 << 31)
  1214. #define CP_HQD_PQ_WPTR 0xC954
  1215. #define CP_HQD_PQ_CONTROL 0xC958
  1216. #define QUEUE_SIZE(x) ((x) << 0)
  1217. #define QUEUE_SIZE_MASK (0x3f << 0)
  1218. #define RPTR_BLOCK_SIZE(x) ((x) << 8)
  1219. #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
  1220. #define PQ_VOLATILE (1 << 26)
  1221. #define NO_UPDATE_RPTR (1 << 27)
  1222. #define UNORD_DISPATCH (1 << 28)
  1223. #define ROQ_PQ_IB_FLIP (1 << 29)
  1224. #define PRIV_STATE (1 << 30)
  1225. #define KMD_QUEUE (1 << 31)
  1226. #define CP_HQD_DEQUEUE_REQUEST 0xC974
  1227. #define CP_MQD_CONTROL 0xC99C
  1228. #define MQD_VMID(x) ((x) << 0)
  1229. #define MQD_VMID_MASK (0xf << 0)
  1230. #define DB_RENDER_CONTROL 0x28000
  1231. #define PA_SC_RASTER_CONFIG 0x28350
  1232. # define RASTER_CONFIG_RB_MAP_0 0
  1233. # define RASTER_CONFIG_RB_MAP_1 1
  1234. # define RASTER_CONFIG_RB_MAP_2 2
  1235. # define RASTER_CONFIG_RB_MAP_3 3
  1236. #define VGT_EVENT_INITIATOR 0x28a90
  1237. # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
  1238. # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
  1239. # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
  1240. # define CACHE_FLUSH_TS (4 << 0)
  1241. # define CACHE_FLUSH (6 << 0)
  1242. # define CS_PARTIAL_FLUSH (7 << 0)
  1243. # define VGT_STREAMOUT_RESET (10 << 0)
  1244. # define END_OF_PIPE_INCR_DE (11 << 0)
  1245. # define END_OF_PIPE_IB_END (12 << 0)
  1246. # define RST_PIX_CNT (13 << 0)
  1247. # define VS_PARTIAL_FLUSH (15 << 0)
  1248. # define PS_PARTIAL_FLUSH (16 << 0)
  1249. # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
  1250. # define ZPASS_DONE (21 << 0)
  1251. # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
  1252. # define PERFCOUNTER_START (23 << 0)
  1253. # define PERFCOUNTER_STOP (24 << 0)
  1254. # define PIPELINESTAT_START (25 << 0)
  1255. # define PIPELINESTAT_STOP (26 << 0)
  1256. # define PERFCOUNTER_SAMPLE (27 << 0)
  1257. # define SAMPLE_PIPELINESTAT (30 << 0)
  1258. # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
  1259. # define SAMPLE_STREAMOUTSTATS (32 << 0)
  1260. # define RESET_VTX_CNT (33 << 0)
  1261. # define VGT_FLUSH (36 << 0)
  1262. # define BOTTOM_OF_PIPE_TS (40 << 0)
  1263. # define DB_CACHE_FLUSH_AND_INV (42 << 0)
  1264. # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
  1265. # define FLUSH_AND_INV_DB_META (44 << 0)
  1266. # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
  1267. # define FLUSH_AND_INV_CB_META (46 << 0)
  1268. # define CS_DONE (47 << 0)
  1269. # define PS_DONE (48 << 0)
  1270. # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
  1271. # define THREAD_TRACE_START (51 << 0)
  1272. # define THREAD_TRACE_STOP (52 << 0)
  1273. # define THREAD_TRACE_FLUSH (54 << 0)
  1274. # define THREAD_TRACE_FINISH (55 << 0)
  1275. # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
  1276. # define PIXEL_PIPE_STAT_DUMP (57 << 0)
  1277. # define PIXEL_PIPE_STAT_RESET (58 << 0)
  1278. #define SCRATCH_REG0 0x30100
  1279. #define SCRATCH_REG1 0x30104
  1280. #define SCRATCH_REG2 0x30108
  1281. #define SCRATCH_REG3 0x3010C
  1282. #define SCRATCH_REG4 0x30110
  1283. #define SCRATCH_REG5 0x30114
  1284. #define SCRATCH_REG6 0x30118
  1285. #define SCRATCH_REG7 0x3011C
  1286. #define SCRATCH_UMSK 0x30140
  1287. #define SCRATCH_ADDR 0x30144
  1288. #define CP_SEM_WAIT_TIMER 0x301BC
  1289. #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
  1290. #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
  1291. #define GRBM_GFX_INDEX 0x30800
  1292. #define INSTANCE_INDEX(x) ((x) << 0)
  1293. #define SH_INDEX(x) ((x) << 8)
  1294. #define SE_INDEX(x) ((x) << 16)
  1295. #define SH_BROADCAST_WRITES (1 << 29)
  1296. #define INSTANCE_BROADCAST_WRITES (1 << 30)
  1297. #define SE_BROADCAST_WRITES (1 << 31)
  1298. #define VGT_ESGS_RING_SIZE 0x30900
  1299. #define VGT_GSVS_RING_SIZE 0x30904
  1300. #define VGT_PRIMITIVE_TYPE 0x30908
  1301. #define VGT_INDEX_TYPE 0x3090C
  1302. #define VGT_NUM_INDICES 0x30930
  1303. #define VGT_NUM_INSTANCES 0x30934
  1304. #define VGT_TF_RING_SIZE 0x30938
  1305. #define VGT_HS_OFFCHIP_PARAM 0x3093C
  1306. #define VGT_TF_MEMORY_BASE 0x30940
  1307. #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
  1308. #define PA_SC_LINE_STIPPLE_STATE 0x30a04
  1309. #define SQC_CACHES 0x30d20
  1310. #define CP_PERFMON_CNTL 0x36020
  1311. #define CGTS_SM_CTRL_REG 0x3c000
  1312. #define SM_MODE(x) ((x) << 17)
  1313. #define SM_MODE_MASK (0x7 << 17)
  1314. #define SM_MODE_ENABLE (1 << 20)
  1315. #define CGTS_OVERRIDE (1 << 21)
  1316. #define CGTS_LS_OVERRIDE (1 << 22)
  1317. #define ON_MONITOR_ADD_EN (1 << 23)
  1318. #define ON_MONITOR_ADD(x) ((x) << 24)
  1319. #define ON_MONITOR_ADD_MASK (0xff << 24)
  1320. #define CGTS_TCC_DISABLE 0x3c00c
  1321. #define CGTS_USER_TCC_DISABLE 0x3c010
  1322. #define TCC_DISABLE_MASK 0xFFFF0000
  1323. #define TCC_DISABLE_SHIFT 16
  1324. #define CB_CGTT_SCLK_CTRL 0x3c2a0
  1325. /*
  1326. * PM4
  1327. */
  1328. #define PACKET_TYPE0 0
  1329. #define PACKET_TYPE1 1
  1330. #define PACKET_TYPE2 2
  1331. #define PACKET_TYPE3 3
  1332. #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
  1333. #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
  1334. #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
  1335. #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
  1336. #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
  1337. (((reg) >> 2) & 0xFFFF) | \
  1338. ((n) & 0x3FFF) << 16)
  1339. #define CP_PACKET2 0x80000000
  1340. #define PACKET2_PAD_SHIFT 0
  1341. #define PACKET2_PAD_MASK (0x3fffffff << 0)
  1342. #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  1343. #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
  1344. (((op) & 0xFF) << 8) | \
  1345. ((n) & 0x3FFF) << 16)
  1346. #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
  1347. /* Packet 3 types */
  1348. #define PACKET3_NOP 0x10
  1349. #define PACKET3_SET_BASE 0x11
  1350. #define PACKET3_BASE_INDEX(x) ((x) << 0)
  1351. #define CE_PARTITION_BASE 3
  1352. #define PACKET3_CLEAR_STATE 0x12
  1353. #define PACKET3_INDEX_BUFFER_SIZE 0x13
  1354. #define PACKET3_DISPATCH_DIRECT 0x15
  1355. #define PACKET3_DISPATCH_INDIRECT 0x16
  1356. #define PACKET3_ATOMIC_GDS 0x1D
  1357. #define PACKET3_ATOMIC_MEM 0x1E
  1358. #define PACKET3_OCCLUSION_QUERY 0x1F
  1359. #define PACKET3_SET_PREDICATION 0x20
  1360. #define PACKET3_REG_RMW 0x21
  1361. #define PACKET3_COND_EXEC 0x22
  1362. #define PACKET3_PRED_EXEC 0x23
  1363. #define PACKET3_DRAW_INDIRECT 0x24
  1364. #define PACKET3_DRAW_INDEX_INDIRECT 0x25
  1365. #define PACKET3_INDEX_BASE 0x26
  1366. #define PACKET3_DRAW_INDEX_2 0x27
  1367. #define PACKET3_CONTEXT_CONTROL 0x28
  1368. #define PACKET3_INDEX_TYPE 0x2A
  1369. #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
  1370. #define PACKET3_DRAW_INDEX_AUTO 0x2D
  1371. #define PACKET3_NUM_INSTANCES 0x2F
  1372. #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
  1373. #define PACKET3_INDIRECT_BUFFER_CONST 0x33
  1374. #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
  1375. #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
  1376. #define PACKET3_DRAW_PREAMBLE 0x36
  1377. #define PACKET3_WRITE_DATA 0x37
  1378. #define WRITE_DATA_DST_SEL(x) ((x) << 8)
  1379. /* 0 - register
  1380. * 1 - memory (sync - via GRBM)
  1381. * 2 - gl2
  1382. * 3 - gds
  1383. * 4 - reserved
  1384. * 5 - memory (async - direct)
  1385. */
  1386. #define WR_ONE_ADDR (1 << 16)
  1387. #define WR_CONFIRM (1 << 20)
  1388. #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
  1389. /* 0 - LRU
  1390. * 1 - Stream
  1391. */
  1392. #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
  1393. /* 0 - me
  1394. * 1 - pfp
  1395. * 2 - ce
  1396. */
  1397. #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
  1398. #define PACKET3_MEM_SEMAPHORE 0x39
  1399. # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
  1400. # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
  1401. # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
  1402. # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
  1403. # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
  1404. #define PACKET3_COPY_DW 0x3B
  1405. #define PACKET3_WAIT_REG_MEM 0x3C
  1406. #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
  1407. /* 0 - always
  1408. * 1 - <
  1409. * 2 - <=
  1410. * 3 - ==
  1411. * 4 - !=
  1412. * 5 - >=
  1413. * 6 - >
  1414. */
  1415. #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
  1416. /* 0 - reg
  1417. * 1 - mem
  1418. */
  1419. #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
  1420. /* 0 - wait_reg_mem
  1421. * 1 - wr_wait_wr_reg
  1422. */
  1423. #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
  1424. /* 0 - me
  1425. * 1 - pfp
  1426. */
  1427. #define PACKET3_INDIRECT_BUFFER 0x3F
  1428. #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
  1429. #define INDIRECT_BUFFER_VALID (1 << 23)
  1430. #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
  1431. /* 0 - LRU
  1432. * 1 - Stream
  1433. * 2 - Bypass
  1434. */
  1435. #define PACKET3_COPY_DATA 0x40
  1436. #define PACKET3_PFP_SYNC_ME 0x42
  1437. #define PACKET3_SURFACE_SYNC 0x43
  1438. # define PACKET3_DEST_BASE_0_ENA (1 << 0)
  1439. # define PACKET3_DEST_BASE_1_ENA (1 << 1)
  1440. # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
  1441. # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
  1442. # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
  1443. # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
  1444. # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
  1445. # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
  1446. # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
  1447. # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
  1448. # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
  1449. # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
  1450. # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
  1451. # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
  1452. # define PACKET3_DEST_BASE_2_ENA (1 << 19)
  1453. # define PACKET3_DEST_BASE_3_ENA (1 << 21)
  1454. # define PACKET3_TCL1_ACTION_ENA (1 << 22)
  1455. # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
  1456. # define PACKET3_CB_ACTION_ENA (1 << 25)
  1457. # define PACKET3_DB_ACTION_ENA (1 << 26)
  1458. # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
  1459. # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
  1460. # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
  1461. #define PACKET3_COND_WRITE 0x45
  1462. #define PACKET3_EVENT_WRITE 0x46
  1463. #define EVENT_TYPE(x) ((x) << 0)
  1464. #define EVENT_INDEX(x) ((x) << 8)
  1465. /* 0 - any non-TS event
  1466. * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
  1467. * 2 - SAMPLE_PIPELINESTAT
  1468. * 3 - SAMPLE_STREAMOUTSTAT*
  1469. * 4 - *S_PARTIAL_FLUSH
  1470. * 5 - EOP events
  1471. * 6 - EOS events
  1472. */
  1473. #define PACKET3_EVENT_WRITE_EOP 0x47
  1474. #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
  1475. #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
  1476. #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
  1477. #define EOP_TCL1_ACTION_EN (1 << 16)
  1478. #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
  1479. #define EOP_CACHE_POLICY(x) ((x) << 25)
  1480. /* 0 - LRU
  1481. * 1 - Stream
  1482. * 2 - Bypass
  1483. */
  1484. #define EOP_TCL2_VOLATILE (1 << 27)
  1485. #define DATA_SEL(x) ((x) << 29)
  1486. /* 0 - discard
  1487. * 1 - send low 32bit data
  1488. * 2 - send 64bit data
  1489. * 3 - send 64bit GPU counter value
  1490. * 4 - send 64bit sys counter value
  1491. */
  1492. #define INT_SEL(x) ((x) << 24)
  1493. /* 0 - none
  1494. * 1 - interrupt only (DATA_SEL = 0)
  1495. * 2 - interrupt when data write is confirmed
  1496. */
  1497. #define DST_SEL(x) ((x) << 16)
  1498. /* 0 - MC
  1499. * 1 - TC/L2
  1500. */
  1501. #define PACKET3_EVENT_WRITE_EOS 0x48
  1502. #define PACKET3_RELEASE_MEM 0x49
  1503. #define PACKET3_PREAMBLE_CNTL 0x4A
  1504. # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
  1505. # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
  1506. #define PACKET3_DMA_DATA 0x50
  1507. #define PACKET3_AQUIRE_MEM 0x58
  1508. #define PACKET3_REWIND 0x59
  1509. #define PACKET3_LOAD_UCONFIG_REG 0x5E
  1510. #define PACKET3_LOAD_SH_REG 0x5F
  1511. #define PACKET3_LOAD_CONFIG_REG 0x60
  1512. #define PACKET3_LOAD_CONTEXT_REG 0x61
  1513. #define PACKET3_SET_CONFIG_REG 0x68
  1514. #define PACKET3_SET_CONFIG_REG_START 0x00008000
  1515. #define PACKET3_SET_CONFIG_REG_END 0x0000b000
  1516. #define PACKET3_SET_CONTEXT_REG 0x69
  1517. #define PACKET3_SET_CONTEXT_REG_START 0x00028000
  1518. #define PACKET3_SET_CONTEXT_REG_END 0x00029000
  1519. #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
  1520. #define PACKET3_SET_SH_REG 0x76
  1521. #define PACKET3_SET_SH_REG_START 0x0000b000
  1522. #define PACKET3_SET_SH_REG_END 0x0000c000
  1523. #define PACKET3_SET_SH_REG_OFFSET 0x77
  1524. #define PACKET3_SET_QUEUE_REG 0x78
  1525. #define PACKET3_SET_UCONFIG_REG 0x79
  1526. #define PACKET3_SET_UCONFIG_REG_START 0x00030000
  1527. #define PACKET3_SET_UCONFIG_REG_END 0x00031000
  1528. #define PACKET3_SCRATCH_RAM_WRITE 0x7D
  1529. #define PACKET3_SCRATCH_RAM_READ 0x7E
  1530. #define PACKET3_LOAD_CONST_RAM 0x80
  1531. #define PACKET3_WRITE_CONST_RAM 0x81
  1532. #define PACKET3_DUMP_CONST_RAM 0x83
  1533. #define PACKET3_INCREMENT_CE_COUNTER 0x84
  1534. #define PACKET3_INCREMENT_DE_COUNTER 0x85
  1535. #define PACKET3_WAIT_ON_CE_COUNTER 0x86
  1536. #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
  1537. #define PACKET3_SWITCH_BUFFER 0x8B
  1538. /* SDMA - first instance at 0xd000, second at 0xd800 */
  1539. #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
  1540. #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
  1541. #define SDMA0_UCODE_ADDR 0xD000
  1542. #define SDMA0_UCODE_DATA 0xD004
  1543. #define SDMA0_POWER_CNTL 0xD008
  1544. #define SDMA0_CLK_CTRL 0xD00C
  1545. #define SDMA0_CNTL 0xD010
  1546. # define TRAP_ENABLE (1 << 0)
  1547. # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
  1548. # define SEM_WAIT_INT_ENABLE (1 << 2)
  1549. # define DATA_SWAP_ENABLE (1 << 3)
  1550. # define FENCE_SWAP_ENABLE (1 << 4)
  1551. # define AUTO_CTXSW_ENABLE (1 << 18)
  1552. # define CTXEMPTY_INT_ENABLE (1 << 28)
  1553. #define SDMA0_TILING_CONFIG 0xD018
  1554. #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
  1555. #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
  1556. #define SDMA0_STATUS_REG 0xd034
  1557. # define SDMA_IDLE (1 << 0)
  1558. #define SDMA0_ME_CNTL 0xD048
  1559. # define SDMA_HALT (1 << 0)
  1560. #define SDMA0_GFX_RB_CNTL 0xD200
  1561. # define SDMA_RB_ENABLE (1 << 0)
  1562. # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
  1563. # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
  1564. # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
  1565. # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
  1566. # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
  1567. #define SDMA0_GFX_RB_BASE 0xD204
  1568. #define SDMA0_GFX_RB_BASE_HI 0xD208
  1569. #define SDMA0_GFX_RB_RPTR 0xD20C
  1570. #define SDMA0_GFX_RB_WPTR 0xD210
  1571. #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
  1572. #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
  1573. #define SDMA0_GFX_IB_CNTL 0xD228
  1574. # define SDMA_IB_ENABLE (1 << 0)
  1575. # define SDMA_IB_SWAP_ENABLE (1 << 4)
  1576. # define SDMA_SWITCH_INSIDE_IB (1 << 8)
  1577. # define SDMA_CMD_VMID(x) ((x) << 16)
  1578. #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
  1579. #define SDMA0_GFX_APE1_CNTL 0xD2A0
  1580. #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
  1581. (((sub_op) & 0xFF) << 8) | \
  1582. (((op) & 0xFF) << 0))
  1583. /* sDMA opcodes */
  1584. #define SDMA_OPCODE_NOP 0
  1585. #define SDMA_OPCODE_COPY 1
  1586. # define SDMA_COPY_SUB_OPCODE_LINEAR 0
  1587. # define SDMA_COPY_SUB_OPCODE_TILED 1
  1588. # define SDMA_COPY_SUB_OPCODE_SOA 3
  1589. # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
  1590. # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
  1591. # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
  1592. #define SDMA_OPCODE_WRITE 2
  1593. # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
  1594. # define SDMA_WRTIE_SUB_OPCODE_TILED 1
  1595. #define SDMA_OPCODE_INDIRECT_BUFFER 4
  1596. #define SDMA_OPCODE_FENCE 5
  1597. #define SDMA_OPCODE_TRAP 6
  1598. #define SDMA_OPCODE_SEMAPHORE 7
  1599. # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
  1600. /* 0 - increment
  1601. * 1 - write 1
  1602. */
  1603. # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
  1604. /* 0 - wait
  1605. * 1 - signal
  1606. */
  1607. # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
  1608. /* mailbox */
  1609. #define SDMA_OPCODE_POLL_REG_MEM 8
  1610. # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
  1611. /* 0 - wait_reg_mem
  1612. * 1 - wr_wait_wr_reg
  1613. */
  1614. # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
  1615. /* 0 - always
  1616. * 1 - <
  1617. * 2 - <=
  1618. * 3 - ==
  1619. * 4 - !=
  1620. * 5 - >=
  1621. * 6 - >
  1622. */
  1623. # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
  1624. /* 0 = register
  1625. * 1 = memory
  1626. */
  1627. #define SDMA_OPCODE_COND_EXEC 9
  1628. #define SDMA_OPCODE_CONSTANT_FILL 11
  1629. # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
  1630. /* 0 = byte fill
  1631. * 2 = DW fill
  1632. */
  1633. #define SDMA_OPCODE_GENERATE_PTE_PDE 12
  1634. #define SDMA_OPCODE_TIMESTAMP 13
  1635. # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
  1636. # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
  1637. # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
  1638. #define SDMA_OPCODE_SRBM_WRITE 14
  1639. # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
  1640. /* byte mask */
  1641. /* UVD */
  1642. #define UVD_UDEC_ADDR_CONFIG 0xef4c
  1643. #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
  1644. #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
  1645. #define UVD_LMI_EXT40_ADDR 0xf498
  1646. #define UVD_LMI_ADDR_EXT 0xf594
  1647. #define UVD_VCPU_CACHE_OFFSET0 0xf608
  1648. #define UVD_VCPU_CACHE_SIZE0 0xf60c
  1649. #define UVD_VCPU_CACHE_OFFSET1 0xf610
  1650. #define UVD_VCPU_CACHE_SIZE1 0xf614
  1651. #define UVD_VCPU_CACHE_OFFSET2 0xf618
  1652. #define UVD_VCPU_CACHE_SIZE2 0xf61c
  1653. #define UVD_RBC_RB_RPTR 0xf690
  1654. #define UVD_RBC_RB_WPTR 0xf694
  1655. #define UVD_CGC_CTRL 0xF4B0
  1656. # define DCM (1 << 0)
  1657. # define CG_DT(x) ((x) << 2)
  1658. # define CG_DT_MASK (0xf << 2)
  1659. # define CLK_OD(x) ((x) << 6)
  1660. # define CLK_OD_MASK (0x1f << 6)
  1661. /* UVD clocks */
  1662. #define CG_DCLK_CNTL 0xC050009C
  1663. # define DCLK_DIVIDER_MASK 0x7f
  1664. # define DCLK_DIR_CNTL_EN (1 << 8)
  1665. #define CG_DCLK_STATUS 0xC05000A0
  1666. # define DCLK_STATUS (1 << 0)
  1667. #define CG_VCLK_CNTL 0xC05000A4
  1668. #define CG_VCLK_STATUS 0xC05000A8
  1669. /* UVD CTX indirect */
  1670. #define UVD_CGC_MEM_CTRL 0xC0
  1671. #endif