atombios_encoders.c 86 KB

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  1. /*
  2. * Copyright 2007-11 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors: Dave Airlie
  24. * Alex Deucher
  25. */
  26. #include <drm/drmP.h>
  27. #include <drm/drm_crtc_helper.h>
  28. #include <drm/radeon_drm.h>
  29. #include "radeon.h"
  30. #include "atom.h"
  31. #include <linux/backlight.h>
  32. extern int atom_debug;
  33. static u8
  34. radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  35. {
  36. u8 backlight_level;
  37. u32 bios_2_scratch;
  38. if (rdev->family >= CHIP_R600)
  39. bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  40. else
  41. bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  42. backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  43. ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  44. return backlight_level;
  45. }
  46. static void
  47. radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  48. u8 backlight_level)
  49. {
  50. u32 bios_2_scratch;
  51. if (rdev->family >= CHIP_R600)
  52. bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  53. else
  54. bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  55. bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  56. bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  57. ATOM_S2_CURRENT_BL_LEVEL_MASK);
  58. if (rdev->family >= CHIP_R600)
  59. WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  60. else
  61. WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  62. }
  63. u8
  64. atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  65. {
  66. struct drm_device *dev = radeon_encoder->base.dev;
  67. struct radeon_device *rdev = dev->dev_private;
  68. if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  69. return 0;
  70. return radeon_atom_get_backlight_level_from_reg(rdev);
  71. }
  72. void
  73. atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  74. {
  75. struct drm_encoder *encoder = &radeon_encoder->base;
  76. struct drm_device *dev = radeon_encoder->base.dev;
  77. struct radeon_device *rdev = dev->dev_private;
  78. struct radeon_encoder_atom_dig *dig;
  79. DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  80. int index;
  81. if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  82. return;
  83. if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  84. radeon_encoder->enc_priv) {
  85. dig = radeon_encoder->enc_priv;
  86. dig->backlight_level = level;
  87. radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
  88. switch (radeon_encoder->encoder_id) {
  89. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  90. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  91. index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
  92. if (dig->backlight_level == 0) {
  93. args.ucAction = ATOM_LCD_BLOFF;
  94. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  95. } else {
  96. args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
  97. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  98. args.ucAction = ATOM_LCD_BLON;
  99. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  100. }
  101. break;
  102. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  103. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  104. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  105. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  106. if (dig->backlight_level == 0)
  107. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
  108. else {
  109. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
  110. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
  111. }
  112. break;
  113. default:
  114. break;
  115. }
  116. }
  117. }
  118. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  119. static u8 radeon_atom_bl_level(struct backlight_device *bd)
  120. {
  121. u8 level;
  122. /* Convert brightness to hardware level */
  123. if (bd->props.brightness < 0)
  124. level = 0;
  125. else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
  126. level = RADEON_MAX_BL_LEVEL;
  127. else
  128. level = bd->props.brightness;
  129. return level;
  130. }
  131. static int radeon_atom_backlight_update_status(struct backlight_device *bd)
  132. {
  133. struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  134. struct radeon_encoder *radeon_encoder = pdata->encoder;
  135. atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
  136. return 0;
  137. }
  138. static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
  139. {
  140. struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  141. struct radeon_encoder *radeon_encoder = pdata->encoder;
  142. struct drm_device *dev = radeon_encoder->base.dev;
  143. struct radeon_device *rdev = dev->dev_private;
  144. return radeon_atom_get_backlight_level_from_reg(rdev);
  145. }
  146. static const struct backlight_ops radeon_atom_backlight_ops = {
  147. .get_brightness = radeon_atom_backlight_get_brightness,
  148. .update_status = radeon_atom_backlight_update_status,
  149. };
  150. void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
  151. struct drm_connector *drm_connector)
  152. {
  153. struct drm_device *dev = radeon_encoder->base.dev;
  154. struct radeon_device *rdev = dev->dev_private;
  155. struct backlight_device *bd;
  156. struct backlight_properties props;
  157. struct radeon_backlight_privdata *pdata;
  158. struct radeon_encoder_atom_dig *dig;
  159. u8 backlight_level;
  160. char bl_name[16];
  161. /* Mac laptops with multiple GPUs use the gmux driver for backlight
  162. * so don't register a backlight device
  163. */
  164. if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
  165. (rdev->pdev->device == 0x6741))
  166. return;
  167. if (!radeon_encoder->enc_priv)
  168. return;
  169. if (!rdev->is_atom_bios)
  170. return;
  171. if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  172. return;
  173. pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
  174. if (!pdata) {
  175. DRM_ERROR("Memory allocation failed\n");
  176. goto error;
  177. }
  178. memset(&props, 0, sizeof(props));
  179. props.max_brightness = RADEON_MAX_BL_LEVEL;
  180. props.type = BACKLIGHT_RAW;
  181. snprintf(bl_name, sizeof(bl_name),
  182. "radeon_bl%d", dev->primary->index);
  183. bd = backlight_device_register(bl_name, &drm_connector->kdev,
  184. pdata, &radeon_atom_backlight_ops, &props);
  185. if (IS_ERR(bd)) {
  186. DRM_ERROR("Backlight registration failed\n");
  187. goto error;
  188. }
  189. pdata->encoder = radeon_encoder;
  190. backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
  191. dig = radeon_encoder->enc_priv;
  192. dig->bl_dev = bd;
  193. bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
  194. bd->props.power = FB_BLANK_UNBLANK;
  195. backlight_update_status(bd);
  196. DRM_INFO("radeon atom DIG backlight initialized\n");
  197. return;
  198. error:
  199. kfree(pdata);
  200. return;
  201. }
  202. static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
  203. {
  204. struct drm_device *dev = radeon_encoder->base.dev;
  205. struct radeon_device *rdev = dev->dev_private;
  206. struct backlight_device *bd = NULL;
  207. struct radeon_encoder_atom_dig *dig;
  208. if (!radeon_encoder->enc_priv)
  209. return;
  210. if (!rdev->is_atom_bios)
  211. return;
  212. if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  213. return;
  214. dig = radeon_encoder->enc_priv;
  215. bd = dig->bl_dev;
  216. dig->bl_dev = NULL;
  217. if (bd) {
  218. struct radeon_legacy_backlight_privdata *pdata;
  219. pdata = bl_get_data(bd);
  220. backlight_device_unregister(bd);
  221. kfree(pdata);
  222. DRM_INFO("radeon atom LVDS backlight unloaded\n");
  223. }
  224. }
  225. #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
  226. void radeon_atom_backlight_init(struct radeon_encoder *encoder)
  227. {
  228. }
  229. static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
  230. {
  231. }
  232. #endif
  233. /* evil but including atombios.h is much worse */
  234. bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  235. struct drm_display_mode *mode);
  236. static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  237. {
  238. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  239. switch (radeon_encoder->encoder_id) {
  240. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  241. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  242. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  243. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  244. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  245. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  246. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  247. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  248. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  249. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  250. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  251. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  252. return true;
  253. default:
  254. return false;
  255. }
  256. }
  257. static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  258. const struct drm_display_mode *mode,
  259. struct drm_display_mode *adjusted_mode)
  260. {
  261. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  262. struct drm_device *dev = encoder->dev;
  263. struct radeon_device *rdev = dev->dev_private;
  264. /* set the active encoder to connector routing */
  265. radeon_encoder_set_active_device(encoder);
  266. drm_mode_set_crtcinfo(adjusted_mode, 0);
  267. /* hw bug */
  268. if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  269. && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  270. adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  271. /* get the native mode for LVDS */
  272. if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  273. radeon_panel_mode_fixup(encoder, adjusted_mode);
  274. /* get the native mode for TV */
  275. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  276. struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  277. if (tv_dac) {
  278. if (tv_dac->tv_std == TV_STD_NTSC ||
  279. tv_dac->tv_std == TV_STD_NTSC_J ||
  280. tv_dac->tv_std == TV_STD_PAL_M)
  281. radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
  282. else
  283. radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
  284. }
  285. }
  286. if (ASIC_IS_DCE3(rdev) &&
  287. ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
  288. (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
  289. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  290. radeon_dp_set_link_config(connector, adjusted_mode);
  291. }
  292. return true;
  293. }
  294. static void
  295. atombios_dac_setup(struct drm_encoder *encoder, int action)
  296. {
  297. struct drm_device *dev = encoder->dev;
  298. struct radeon_device *rdev = dev->dev_private;
  299. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  300. DAC_ENCODER_CONTROL_PS_ALLOCATION args;
  301. int index = 0;
  302. struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
  303. memset(&args, 0, sizeof(args));
  304. switch (radeon_encoder->encoder_id) {
  305. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  306. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  307. index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
  308. break;
  309. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  310. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  311. index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
  312. break;
  313. }
  314. args.ucAction = action;
  315. if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
  316. args.ucDacStandard = ATOM_DAC1_PS2;
  317. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  318. args.ucDacStandard = ATOM_DAC1_CV;
  319. else {
  320. switch (dac_info->tv_std) {
  321. case TV_STD_PAL:
  322. case TV_STD_PAL_M:
  323. case TV_STD_SCART_PAL:
  324. case TV_STD_SECAM:
  325. case TV_STD_PAL_CN:
  326. args.ucDacStandard = ATOM_DAC1_PAL;
  327. break;
  328. case TV_STD_NTSC:
  329. case TV_STD_NTSC_J:
  330. case TV_STD_PAL_60:
  331. default:
  332. args.ucDacStandard = ATOM_DAC1_NTSC;
  333. break;
  334. }
  335. }
  336. args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  337. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  338. }
  339. static void
  340. atombios_tv_setup(struct drm_encoder *encoder, int action)
  341. {
  342. struct drm_device *dev = encoder->dev;
  343. struct radeon_device *rdev = dev->dev_private;
  344. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  345. TV_ENCODER_CONTROL_PS_ALLOCATION args;
  346. int index = 0;
  347. struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
  348. memset(&args, 0, sizeof(args));
  349. index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
  350. args.sTVEncoder.ucAction = action;
  351. if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  352. args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
  353. else {
  354. switch (dac_info->tv_std) {
  355. case TV_STD_NTSC:
  356. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
  357. break;
  358. case TV_STD_PAL:
  359. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
  360. break;
  361. case TV_STD_PAL_M:
  362. args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
  363. break;
  364. case TV_STD_PAL_60:
  365. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
  366. break;
  367. case TV_STD_NTSC_J:
  368. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
  369. break;
  370. case TV_STD_SCART_PAL:
  371. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
  372. break;
  373. case TV_STD_SECAM:
  374. args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
  375. break;
  376. case TV_STD_PAL_CN:
  377. args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
  378. break;
  379. default:
  380. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
  381. break;
  382. }
  383. }
  384. args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  385. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  386. }
  387. static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
  388. {
  389. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  390. int bpc = 8;
  391. if (connector)
  392. bpc = radeon_get_monitor_bpc(connector);
  393. switch (bpc) {
  394. case 0:
  395. return PANEL_BPC_UNDEFINE;
  396. case 6:
  397. return PANEL_6BIT_PER_COLOR;
  398. case 8:
  399. default:
  400. return PANEL_8BIT_PER_COLOR;
  401. case 10:
  402. return PANEL_10BIT_PER_COLOR;
  403. case 12:
  404. return PANEL_12BIT_PER_COLOR;
  405. case 16:
  406. return PANEL_16BIT_PER_COLOR;
  407. }
  408. }
  409. union dvo_encoder_control {
  410. ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
  411. DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
  412. DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
  413. DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
  414. };
  415. void
  416. atombios_dvo_setup(struct drm_encoder *encoder, int action)
  417. {
  418. struct drm_device *dev = encoder->dev;
  419. struct radeon_device *rdev = dev->dev_private;
  420. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  421. union dvo_encoder_control args;
  422. int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
  423. uint8_t frev, crev;
  424. memset(&args, 0, sizeof(args));
  425. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  426. return;
  427. /* some R4xx chips have the wrong frev */
  428. if (rdev->family <= CHIP_RV410)
  429. frev = 1;
  430. switch (frev) {
  431. case 1:
  432. switch (crev) {
  433. case 1:
  434. /* R4xx, R5xx */
  435. args.ext_tmds.sXTmdsEncoder.ucEnable = action;
  436. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  437. args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  438. args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
  439. break;
  440. case 2:
  441. /* RS600/690/740 */
  442. args.dvo.sDVOEncoder.ucAction = action;
  443. args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  444. /* DFP1, CRT1, TV1 depending on the type of port */
  445. args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
  446. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  447. args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
  448. break;
  449. case 3:
  450. /* R6xx */
  451. args.dvo_v3.ucAction = action;
  452. args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  453. args.dvo_v3.ucDVOConfig = 0; /* XXX */
  454. break;
  455. case 4:
  456. /* DCE8 */
  457. args.dvo_v4.ucAction = action;
  458. args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  459. args.dvo_v4.ucDVOConfig = 0; /* XXX */
  460. args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
  461. break;
  462. default:
  463. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  464. break;
  465. }
  466. break;
  467. default:
  468. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  469. break;
  470. }
  471. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  472. }
  473. union lvds_encoder_control {
  474. LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
  475. LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
  476. };
  477. void
  478. atombios_digital_setup(struct drm_encoder *encoder, int action)
  479. {
  480. struct drm_device *dev = encoder->dev;
  481. struct radeon_device *rdev = dev->dev_private;
  482. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  483. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  484. union lvds_encoder_control args;
  485. int index = 0;
  486. int hdmi_detected = 0;
  487. uint8_t frev, crev;
  488. if (!dig)
  489. return;
  490. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
  491. hdmi_detected = 1;
  492. memset(&args, 0, sizeof(args));
  493. switch (radeon_encoder->encoder_id) {
  494. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  495. index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
  496. break;
  497. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  498. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  499. index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
  500. break;
  501. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  502. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  503. index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
  504. else
  505. index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
  506. break;
  507. }
  508. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  509. return;
  510. switch (frev) {
  511. case 1:
  512. case 2:
  513. switch (crev) {
  514. case 1:
  515. args.v1.ucMisc = 0;
  516. args.v1.ucAction = action;
  517. if (hdmi_detected)
  518. args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
  519. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  520. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  521. if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
  522. args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  523. if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
  524. args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
  525. } else {
  526. if (dig->linkb)
  527. args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
  528. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  529. args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  530. /*if (pScrn->rgbBits == 8) */
  531. args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
  532. }
  533. break;
  534. case 2:
  535. case 3:
  536. args.v2.ucMisc = 0;
  537. args.v2.ucAction = action;
  538. if (crev == 3) {
  539. if (dig->coherent_mode)
  540. args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
  541. }
  542. if (hdmi_detected)
  543. args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
  544. args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  545. args.v2.ucTruncate = 0;
  546. args.v2.ucSpatial = 0;
  547. args.v2.ucTemporal = 0;
  548. args.v2.ucFRC = 0;
  549. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  550. if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
  551. args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  552. if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
  553. args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
  554. if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
  555. args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
  556. }
  557. if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
  558. args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
  559. if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
  560. args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
  561. if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
  562. args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
  563. }
  564. } else {
  565. if (dig->linkb)
  566. args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
  567. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  568. args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  569. }
  570. break;
  571. default:
  572. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  573. break;
  574. }
  575. break;
  576. default:
  577. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  578. break;
  579. }
  580. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  581. }
  582. int
  583. atombios_get_encoder_mode(struct drm_encoder *encoder)
  584. {
  585. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  586. struct drm_connector *connector;
  587. struct radeon_connector *radeon_connector;
  588. struct radeon_connector_atom_dig *dig_connector;
  589. /* dp bridges are always DP */
  590. if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
  591. return ATOM_ENCODER_MODE_DP;
  592. /* DVO is always DVO */
  593. if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
  594. (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
  595. return ATOM_ENCODER_MODE_DVO;
  596. connector = radeon_get_connector_for_encoder(encoder);
  597. /* if we don't have an active device yet, just use one of
  598. * the connectors tied to the encoder.
  599. */
  600. if (!connector)
  601. connector = radeon_get_connector_for_encoder_init(encoder);
  602. radeon_connector = to_radeon_connector(connector);
  603. switch (connector->connector_type) {
  604. case DRM_MODE_CONNECTOR_DVII:
  605. case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
  606. if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
  607. (drm_detect_hdmi_monitor(radeon_connector->edid) &&
  608. (radeon_connector->audio == RADEON_AUDIO_AUTO)))
  609. return ATOM_ENCODER_MODE_HDMI;
  610. else if (radeon_connector->use_digital)
  611. return ATOM_ENCODER_MODE_DVI;
  612. else
  613. return ATOM_ENCODER_MODE_CRT;
  614. break;
  615. case DRM_MODE_CONNECTOR_DVID:
  616. case DRM_MODE_CONNECTOR_HDMIA:
  617. default:
  618. if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
  619. (drm_detect_hdmi_monitor(radeon_connector->edid) &&
  620. (radeon_connector->audio == RADEON_AUDIO_AUTO)))
  621. return ATOM_ENCODER_MODE_HDMI;
  622. else
  623. return ATOM_ENCODER_MODE_DVI;
  624. break;
  625. case DRM_MODE_CONNECTOR_LVDS:
  626. return ATOM_ENCODER_MODE_LVDS;
  627. break;
  628. case DRM_MODE_CONNECTOR_DisplayPort:
  629. dig_connector = radeon_connector->con_priv;
  630. if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
  631. (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
  632. return ATOM_ENCODER_MODE_DP;
  633. else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
  634. (drm_detect_hdmi_monitor(radeon_connector->edid) &&
  635. (radeon_connector->audio == RADEON_AUDIO_AUTO)))
  636. return ATOM_ENCODER_MODE_HDMI;
  637. else
  638. return ATOM_ENCODER_MODE_DVI;
  639. break;
  640. case DRM_MODE_CONNECTOR_eDP:
  641. return ATOM_ENCODER_MODE_DP;
  642. case DRM_MODE_CONNECTOR_DVIA:
  643. case DRM_MODE_CONNECTOR_VGA:
  644. return ATOM_ENCODER_MODE_CRT;
  645. break;
  646. case DRM_MODE_CONNECTOR_Composite:
  647. case DRM_MODE_CONNECTOR_SVIDEO:
  648. case DRM_MODE_CONNECTOR_9PinDIN:
  649. /* fix me */
  650. return ATOM_ENCODER_MODE_TV;
  651. /*return ATOM_ENCODER_MODE_CV;*/
  652. break;
  653. }
  654. }
  655. /*
  656. * DIG Encoder/Transmitter Setup
  657. *
  658. * DCE 3.0/3.1
  659. * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
  660. * Supports up to 3 digital outputs
  661. * - 2 DIG encoder blocks.
  662. * DIG1 can drive UNIPHY link A or link B
  663. * DIG2 can drive UNIPHY link B or LVTMA
  664. *
  665. * DCE 3.2
  666. * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
  667. * Supports up to 5 digital outputs
  668. * - 2 DIG encoder blocks.
  669. * DIG1/2 can drive UNIPHY0/1/2 link A or link B
  670. *
  671. * DCE 4.0/5.0/6.0
  672. * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
  673. * Supports up to 6 digital outputs
  674. * - 6 DIG encoder blocks.
  675. * - DIG to PHY mapping is hardcoded
  676. * DIG1 drives UNIPHY0 link A, A+B
  677. * DIG2 drives UNIPHY0 link B
  678. * DIG3 drives UNIPHY1 link A, A+B
  679. * DIG4 drives UNIPHY1 link B
  680. * DIG5 drives UNIPHY2 link A, A+B
  681. * DIG6 drives UNIPHY2 link B
  682. *
  683. * DCE 4.1
  684. * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
  685. * Supports up to 6 digital outputs
  686. * - 2 DIG encoder blocks.
  687. * llano
  688. * DIG1/2 can drive UNIPHY0/1/2 link A or link B
  689. * ontario
  690. * DIG1 drives UNIPHY0/1/2 link A
  691. * DIG2 drives UNIPHY0/1/2 link B
  692. *
  693. * Routing
  694. * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
  695. * Examples:
  696. * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
  697. * crtc1 -> dig1 -> UNIPHY0 link B -> DP
  698. * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
  699. * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
  700. */
  701. union dig_encoder_control {
  702. DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
  703. DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
  704. DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
  705. DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
  706. };
  707. void
  708. atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
  709. {
  710. struct drm_device *dev = encoder->dev;
  711. struct radeon_device *rdev = dev->dev_private;
  712. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  713. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  714. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  715. union dig_encoder_control args;
  716. int index = 0;
  717. uint8_t frev, crev;
  718. int dp_clock = 0;
  719. int dp_lane_count = 0;
  720. int hpd_id = RADEON_HPD_NONE;
  721. if (connector) {
  722. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  723. struct radeon_connector_atom_dig *dig_connector =
  724. radeon_connector->con_priv;
  725. dp_clock = dig_connector->dp_clock;
  726. dp_lane_count = dig_connector->dp_lane_count;
  727. hpd_id = radeon_connector->hpd.hpd;
  728. }
  729. /* no dig encoder assigned */
  730. if (dig->dig_encoder == -1)
  731. return;
  732. memset(&args, 0, sizeof(args));
  733. if (ASIC_IS_DCE4(rdev))
  734. index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
  735. else {
  736. if (dig->dig_encoder)
  737. index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
  738. else
  739. index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
  740. }
  741. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  742. return;
  743. switch (frev) {
  744. case 1:
  745. switch (crev) {
  746. case 1:
  747. args.v1.ucAction = action;
  748. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  749. if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
  750. args.v3.ucPanelMode = panel_mode;
  751. else
  752. args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
  753. if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
  754. args.v1.ucLaneNum = dp_lane_count;
  755. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  756. args.v1.ucLaneNum = 8;
  757. else
  758. args.v1.ucLaneNum = 4;
  759. if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
  760. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
  761. switch (radeon_encoder->encoder_id) {
  762. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  763. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
  764. break;
  765. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  766. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  767. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
  768. break;
  769. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  770. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
  771. break;
  772. }
  773. if (dig->linkb)
  774. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
  775. else
  776. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
  777. break;
  778. case 2:
  779. case 3:
  780. args.v3.ucAction = action;
  781. args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  782. if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
  783. args.v3.ucPanelMode = panel_mode;
  784. else
  785. args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
  786. if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
  787. args.v3.ucLaneNum = dp_lane_count;
  788. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  789. args.v3.ucLaneNum = 8;
  790. else
  791. args.v3.ucLaneNum = 4;
  792. if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
  793. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
  794. args.v3.acConfig.ucDigSel = dig->dig_encoder;
  795. args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
  796. break;
  797. case 4:
  798. args.v4.ucAction = action;
  799. args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  800. if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
  801. args.v4.ucPanelMode = panel_mode;
  802. else
  803. args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
  804. if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
  805. args.v4.ucLaneNum = dp_lane_count;
  806. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  807. args.v4.ucLaneNum = 8;
  808. else
  809. args.v4.ucLaneNum = 4;
  810. if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
  811. if (dp_clock == 540000)
  812. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
  813. else if (dp_clock == 324000)
  814. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
  815. else if (dp_clock == 270000)
  816. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
  817. else
  818. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
  819. }
  820. args.v4.acConfig.ucDigSel = dig->dig_encoder;
  821. args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
  822. if (hpd_id == RADEON_HPD_NONE)
  823. args.v4.ucHPD_ID = 0;
  824. else
  825. args.v4.ucHPD_ID = hpd_id + 1;
  826. break;
  827. default:
  828. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  829. break;
  830. }
  831. break;
  832. default:
  833. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  834. break;
  835. }
  836. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  837. }
  838. union dig_transmitter_control {
  839. DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
  840. DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
  841. DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
  842. DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
  843. DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
  844. };
  845. void
  846. atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
  847. {
  848. struct drm_device *dev = encoder->dev;
  849. struct radeon_device *rdev = dev->dev_private;
  850. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  851. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  852. struct drm_connector *connector;
  853. union dig_transmitter_control args;
  854. int index = 0;
  855. uint8_t frev, crev;
  856. bool is_dp = false;
  857. int pll_id = 0;
  858. int dp_clock = 0;
  859. int dp_lane_count = 0;
  860. int connector_object_id = 0;
  861. int igp_lane_info = 0;
  862. int dig_encoder = dig->dig_encoder;
  863. int hpd_id = RADEON_HPD_NONE;
  864. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  865. connector = radeon_get_connector_for_encoder_init(encoder);
  866. /* just needed to avoid bailing in the encoder check. the encoder
  867. * isn't used for init
  868. */
  869. dig_encoder = 0;
  870. } else
  871. connector = radeon_get_connector_for_encoder(encoder);
  872. if (connector) {
  873. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  874. struct radeon_connector_atom_dig *dig_connector =
  875. radeon_connector->con_priv;
  876. hpd_id = radeon_connector->hpd.hpd;
  877. dp_clock = dig_connector->dp_clock;
  878. dp_lane_count = dig_connector->dp_lane_count;
  879. connector_object_id =
  880. (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  881. igp_lane_info = dig_connector->igp_lane_info;
  882. }
  883. if (encoder->crtc) {
  884. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  885. pll_id = radeon_crtc->pll_id;
  886. }
  887. /* no dig encoder assigned */
  888. if (dig_encoder == -1)
  889. return;
  890. if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
  891. is_dp = true;
  892. memset(&args, 0, sizeof(args));
  893. switch (radeon_encoder->encoder_id) {
  894. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  895. index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
  896. break;
  897. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  898. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  899. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  900. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  901. index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
  902. break;
  903. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  904. index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
  905. break;
  906. }
  907. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  908. return;
  909. switch (frev) {
  910. case 1:
  911. switch (crev) {
  912. case 1:
  913. args.v1.ucAction = action;
  914. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  915. args.v1.usInitInfo = cpu_to_le16(connector_object_id);
  916. } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
  917. args.v1.asMode.ucLaneSel = lane_num;
  918. args.v1.asMode.ucLaneSet = lane_set;
  919. } else {
  920. if (is_dp)
  921. args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
  922. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  923. args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
  924. else
  925. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  926. }
  927. args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
  928. if (dig_encoder)
  929. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
  930. else
  931. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
  932. if ((rdev->flags & RADEON_IS_IGP) &&
  933. (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
  934. if (is_dp ||
  935. !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
  936. if (igp_lane_info & 0x1)
  937. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
  938. else if (igp_lane_info & 0x2)
  939. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
  940. else if (igp_lane_info & 0x4)
  941. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
  942. else if (igp_lane_info & 0x8)
  943. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
  944. } else {
  945. if (igp_lane_info & 0x3)
  946. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
  947. else if (igp_lane_info & 0xc)
  948. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
  949. }
  950. }
  951. if (dig->linkb)
  952. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
  953. else
  954. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
  955. if (is_dp)
  956. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
  957. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  958. if (dig->coherent_mode)
  959. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
  960. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  961. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
  962. }
  963. break;
  964. case 2:
  965. args.v2.ucAction = action;
  966. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  967. args.v2.usInitInfo = cpu_to_le16(connector_object_id);
  968. } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
  969. args.v2.asMode.ucLaneSel = lane_num;
  970. args.v2.asMode.ucLaneSet = lane_set;
  971. } else {
  972. if (is_dp)
  973. args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
  974. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  975. args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
  976. else
  977. args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  978. }
  979. args.v2.acConfig.ucEncoderSel = dig_encoder;
  980. if (dig->linkb)
  981. args.v2.acConfig.ucLinkSel = 1;
  982. switch (radeon_encoder->encoder_id) {
  983. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  984. args.v2.acConfig.ucTransmitterSel = 0;
  985. break;
  986. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  987. args.v2.acConfig.ucTransmitterSel = 1;
  988. break;
  989. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  990. args.v2.acConfig.ucTransmitterSel = 2;
  991. break;
  992. }
  993. if (is_dp) {
  994. args.v2.acConfig.fCoherentMode = 1;
  995. args.v2.acConfig.fDPConnector = 1;
  996. } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  997. if (dig->coherent_mode)
  998. args.v2.acConfig.fCoherentMode = 1;
  999. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1000. args.v2.acConfig.fDualLinkConnector = 1;
  1001. }
  1002. break;
  1003. case 3:
  1004. args.v3.ucAction = action;
  1005. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  1006. args.v3.usInitInfo = cpu_to_le16(connector_object_id);
  1007. } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
  1008. args.v3.asMode.ucLaneSel = lane_num;
  1009. args.v3.asMode.ucLaneSet = lane_set;
  1010. } else {
  1011. if (is_dp)
  1012. args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
  1013. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1014. args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
  1015. else
  1016. args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  1017. }
  1018. if (is_dp)
  1019. args.v3.ucLaneNum = dp_lane_count;
  1020. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1021. args.v3.ucLaneNum = 8;
  1022. else
  1023. args.v3.ucLaneNum = 4;
  1024. if (dig->linkb)
  1025. args.v3.acConfig.ucLinkSel = 1;
  1026. if (dig_encoder & 1)
  1027. args.v3.acConfig.ucEncoderSel = 1;
  1028. /* Select the PLL for the PHY
  1029. * DP PHY should be clocked from external src if there is
  1030. * one.
  1031. */
  1032. /* On DCE4, if there is an external clock, it generates the DP ref clock */
  1033. if (is_dp && rdev->clock.dp_extclk)
  1034. args.v3.acConfig.ucRefClkSource = 2; /* external src */
  1035. else
  1036. args.v3.acConfig.ucRefClkSource = pll_id;
  1037. switch (radeon_encoder->encoder_id) {
  1038. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1039. args.v3.acConfig.ucTransmitterSel = 0;
  1040. break;
  1041. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1042. args.v3.acConfig.ucTransmitterSel = 1;
  1043. break;
  1044. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1045. args.v3.acConfig.ucTransmitterSel = 2;
  1046. break;
  1047. }
  1048. if (is_dp)
  1049. args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
  1050. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  1051. if (dig->coherent_mode)
  1052. args.v3.acConfig.fCoherentMode = 1;
  1053. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1054. args.v3.acConfig.fDualLinkConnector = 1;
  1055. }
  1056. break;
  1057. case 4:
  1058. args.v4.ucAction = action;
  1059. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  1060. args.v4.usInitInfo = cpu_to_le16(connector_object_id);
  1061. } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
  1062. args.v4.asMode.ucLaneSel = lane_num;
  1063. args.v4.asMode.ucLaneSet = lane_set;
  1064. } else {
  1065. if (is_dp)
  1066. args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
  1067. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1068. args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
  1069. else
  1070. args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  1071. }
  1072. if (is_dp)
  1073. args.v4.ucLaneNum = dp_lane_count;
  1074. else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1075. args.v4.ucLaneNum = 8;
  1076. else
  1077. args.v4.ucLaneNum = 4;
  1078. if (dig->linkb)
  1079. args.v4.acConfig.ucLinkSel = 1;
  1080. if (dig_encoder & 1)
  1081. args.v4.acConfig.ucEncoderSel = 1;
  1082. /* Select the PLL for the PHY
  1083. * DP PHY should be clocked from external src if there is
  1084. * one.
  1085. */
  1086. /* On DCE5 DCPLL usually generates the DP ref clock */
  1087. if (is_dp) {
  1088. if (rdev->clock.dp_extclk)
  1089. args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
  1090. else
  1091. args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
  1092. } else
  1093. args.v4.acConfig.ucRefClkSource = pll_id;
  1094. switch (radeon_encoder->encoder_id) {
  1095. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1096. args.v4.acConfig.ucTransmitterSel = 0;
  1097. break;
  1098. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1099. args.v4.acConfig.ucTransmitterSel = 1;
  1100. break;
  1101. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1102. args.v4.acConfig.ucTransmitterSel = 2;
  1103. break;
  1104. }
  1105. if (is_dp)
  1106. args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
  1107. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  1108. if (dig->coherent_mode)
  1109. args.v4.acConfig.fCoherentMode = 1;
  1110. if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1111. args.v4.acConfig.fDualLinkConnector = 1;
  1112. }
  1113. break;
  1114. case 5:
  1115. args.v5.ucAction = action;
  1116. if (is_dp)
  1117. args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
  1118. else
  1119. args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  1120. switch (radeon_encoder->encoder_id) {
  1121. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1122. if (dig->linkb)
  1123. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
  1124. else
  1125. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
  1126. break;
  1127. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1128. if (dig->linkb)
  1129. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
  1130. else
  1131. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
  1132. break;
  1133. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1134. if (dig->linkb)
  1135. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
  1136. else
  1137. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
  1138. break;
  1139. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1140. args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
  1141. break;
  1142. }
  1143. if (is_dp)
  1144. args.v5.ucLaneNum = dp_lane_count;
  1145. else if (radeon_encoder->pixel_clock > 165000)
  1146. args.v5.ucLaneNum = 8;
  1147. else
  1148. args.v5.ucLaneNum = 4;
  1149. args.v5.ucConnObjId = connector_object_id;
  1150. args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
  1151. if (is_dp && rdev->clock.dp_extclk)
  1152. args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
  1153. else
  1154. args.v5.asConfig.ucPhyClkSrcId = pll_id;
  1155. if (is_dp)
  1156. args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
  1157. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  1158. if (dig->coherent_mode)
  1159. args.v5.asConfig.ucCoherentMode = 1;
  1160. }
  1161. if (hpd_id == RADEON_HPD_NONE)
  1162. args.v5.asConfig.ucHPDSel = 0;
  1163. else
  1164. args.v5.asConfig.ucHPDSel = hpd_id + 1;
  1165. args.v5.ucDigEncoderSel = 1 << dig_encoder;
  1166. args.v5.ucDPLaneSet = lane_set;
  1167. break;
  1168. default:
  1169. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  1170. break;
  1171. }
  1172. break;
  1173. default:
  1174. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  1175. break;
  1176. }
  1177. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1178. }
  1179. bool
  1180. atombios_set_edp_panel_power(struct drm_connector *connector, int action)
  1181. {
  1182. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  1183. struct drm_device *dev = radeon_connector->base.dev;
  1184. struct radeon_device *rdev = dev->dev_private;
  1185. union dig_transmitter_control args;
  1186. int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
  1187. uint8_t frev, crev;
  1188. if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
  1189. goto done;
  1190. if (!ASIC_IS_DCE4(rdev))
  1191. goto done;
  1192. if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
  1193. (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
  1194. goto done;
  1195. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1196. goto done;
  1197. memset(&args, 0, sizeof(args));
  1198. args.v1.ucAction = action;
  1199. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1200. /* wait for the panel to power up */
  1201. if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
  1202. int i;
  1203. for (i = 0; i < 300; i++) {
  1204. if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
  1205. return true;
  1206. mdelay(1);
  1207. }
  1208. return false;
  1209. }
  1210. done:
  1211. return true;
  1212. }
  1213. union external_encoder_control {
  1214. EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
  1215. EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
  1216. };
  1217. static void
  1218. atombios_external_encoder_setup(struct drm_encoder *encoder,
  1219. struct drm_encoder *ext_encoder,
  1220. int action)
  1221. {
  1222. struct drm_device *dev = encoder->dev;
  1223. struct radeon_device *rdev = dev->dev_private;
  1224. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1225. struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
  1226. union external_encoder_control args;
  1227. struct drm_connector *connector;
  1228. int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
  1229. u8 frev, crev;
  1230. int dp_clock = 0;
  1231. int dp_lane_count = 0;
  1232. int connector_object_id = 0;
  1233. u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
  1234. if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
  1235. connector = radeon_get_connector_for_encoder_init(encoder);
  1236. else
  1237. connector = radeon_get_connector_for_encoder(encoder);
  1238. if (connector) {
  1239. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  1240. struct radeon_connector_atom_dig *dig_connector =
  1241. radeon_connector->con_priv;
  1242. dp_clock = dig_connector->dp_clock;
  1243. dp_lane_count = dig_connector->dp_lane_count;
  1244. connector_object_id =
  1245. (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  1246. }
  1247. memset(&args, 0, sizeof(args));
  1248. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1249. return;
  1250. switch (frev) {
  1251. case 1:
  1252. /* no params on frev 1 */
  1253. break;
  1254. case 2:
  1255. switch (crev) {
  1256. case 1:
  1257. case 2:
  1258. args.v1.sDigEncoder.ucAction = action;
  1259. args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  1260. args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
  1261. if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
  1262. if (dp_clock == 270000)
  1263. args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
  1264. args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
  1265. } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1266. args.v1.sDigEncoder.ucLaneNum = 8;
  1267. else
  1268. args.v1.sDigEncoder.ucLaneNum = 4;
  1269. break;
  1270. case 3:
  1271. args.v3.sExtEncoder.ucAction = action;
  1272. if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
  1273. args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
  1274. else
  1275. args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  1276. args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
  1277. if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
  1278. if (dp_clock == 270000)
  1279. args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
  1280. else if (dp_clock == 540000)
  1281. args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
  1282. args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
  1283. } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
  1284. args.v3.sExtEncoder.ucLaneNum = 8;
  1285. else
  1286. args.v3.sExtEncoder.ucLaneNum = 4;
  1287. switch (ext_enum) {
  1288. case GRAPH_OBJECT_ENUM_ID1:
  1289. args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
  1290. break;
  1291. case GRAPH_OBJECT_ENUM_ID2:
  1292. args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
  1293. break;
  1294. case GRAPH_OBJECT_ENUM_ID3:
  1295. args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
  1296. break;
  1297. }
  1298. args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
  1299. break;
  1300. default:
  1301. DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
  1302. return;
  1303. }
  1304. break;
  1305. default:
  1306. DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
  1307. return;
  1308. }
  1309. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1310. }
  1311. static void
  1312. atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
  1313. {
  1314. struct drm_device *dev = encoder->dev;
  1315. struct radeon_device *rdev = dev->dev_private;
  1316. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1317. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1318. ENABLE_YUV_PS_ALLOCATION args;
  1319. int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
  1320. uint32_t temp, reg;
  1321. memset(&args, 0, sizeof(args));
  1322. if (rdev->family >= CHIP_R600)
  1323. reg = R600_BIOS_3_SCRATCH;
  1324. else
  1325. reg = RADEON_BIOS_3_SCRATCH;
  1326. /* XXX: fix up scratch reg handling */
  1327. temp = RREG32(reg);
  1328. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1329. WREG32(reg, (ATOM_S3_TV1_ACTIVE |
  1330. (radeon_crtc->crtc_id << 18)));
  1331. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1332. WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
  1333. else
  1334. WREG32(reg, 0);
  1335. if (enable)
  1336. args.ucEnable = ATOM_ENABLE;
  1337. args.ucCRTC = radeon_crtc->crtc_id;
  1338. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1339. WREG32(reg, temp);
  1340. }
  1341. static void
  1342. radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
  1343. {
  1344. struct drm_device *dev = encoder->dev;
  1345. struct radeon_device *rdev = dev->dev_private;
  1346. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1347. DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  1348. int index = 0;
  1349. memset(&args, 0, sizeof(args));
  1350. switch (radeon_encoder->encoder_id) {
  1351. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1352. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1353. index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
  1354. break;
  1355. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1356. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1357. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1358. index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
  1359. break;
  1360. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1361. index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
  1362. break;
  1363. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1364. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  1365. index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
  1366. else
  1367. index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
  1368. break;
  1369. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1370. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1371. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1372. index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
  1373. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1374. index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
  1375. else
  1376. index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
  1377. break;
  1378. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1379. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1380. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1381. index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
  1382. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1383. index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
  1384. else
  1385. index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
  1386. break;
  1387. default:
  1388. return;
  1389. }
  1390. switch (mode) {
  1391. case DRM_MODE_DPMS_ON:
  1392. args.ucAction = ATOM_ENABLE;
  1393. /* workaround for DVOOutputControl on some RS690 systems */
  1394. if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
  1395. u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
  1396. WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
  1397. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1398. WREG32(RADEON_BIOS_3_SCRATCH, reg);
  1399. } else
  1400. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1401. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  1402. args.ucAction = ATOM_LCD_BLON;
  1403. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1404. }
  1405. break;
  1406. case DRM_MODE_DPMS_STANDBY:
  1407. case DRM_MODE_DPMS_SUSPEND:
  1408. case DRM_MODE_DPMS_OFF:
  1409. args.ucAction = ATOM_DISABLE;
  1410. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1411. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  1412. args.ucAction = ATOM_LCD_BLOFF;
  1413. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1414. }
  1415. break;
  1416. }
  1417. }
  1418. static void
  1419. radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
  1420. {
  1421. struct drm_device *dev = encoder->dev;
  1422. struct radeon_device *rdev = dev->dev_private;
  1423. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1424. struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
  1425. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  1426. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  1427. struct radeon_connector *radeon_connector = NULL;
  1428. struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
  1429. if (connector) {
  1430. radeon_connector = to_radeon_connector(connector);
  1431. radeon_dig_connector = radeon_connector->con_priv;
  1432. }
  1433. switch (mode) {
  1434. case DRM_MODE_DPMS_ON:
  1435. if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
  1436. if (!connector)
  1437. dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
  1438. else
  1439. dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
  1440. /* setup and enable the encoder */
  1441. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
  1442. atombios_dig_encoder_setup(encoder,
  1443. ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
  1444. dig->panel_mode);
  1445. if (ext_encoder) {
  1446. if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
  1447. atombios_external_encoder_setup(encoder, ext_encoder,
  1448. EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
  1449. }
  1450. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
  1451. } else if (ASIC_IS_DCE4(rdev)) {
  1452. /* setup and enable the encoder */
  1453. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
  1454. /* enable the transmitter */
  1455. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
  1456. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
  1457. } else {
  1458. /* setup and enable the encoder and transmitter */
  1459. atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
  1460. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
  1461. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
  1462. /* some dce3.x boards have a bug in their transmitter control table.
  1463. * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
  1464. * does the same thing and more.
  1465. */
  1466. if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
  1467. (rdev->family != CHIP_RS880))
  1468. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
  1469. }
  1470. if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
  1471. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
  1472. atombios_set_edp_panel_power(connector,
  1473. ATOM_TRANSMITTER_ACTION_POWER_ON);
  1474. radeon_dig_connector->edp_on = true;
  1475. }
  1476. radeon_dp_link_train(encoder, connector);
  1477. if (ASIC_IS_DCE4(rdev))
  1478. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
  1479. }
  1480. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  1481. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
  1482. break;
  1483. case DRM_MODE_DPMS_STANDBY:
  1484. case DRM_MODE_DPMS_SUSPEND:
  1485. case DRM_MODE_DPMS_OFF:
  1486. if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
  1487. /* disable the transmitter */
  1488. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1489. } else if (ASIC_IS_DCE4(rdev)) {
  1490. /* disable the transmitter */
  1491. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
  1492. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1493. } else {
  1494. /* disable the encoder and transmitter */
  1495. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
  1496. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1497. atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
  1498. }
  1499. if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
  1500. if (ASIC_IS_DCE4(rdev))
  1501. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
  1502. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
  1503. atombios_set_edp_panel_power(connector,
  1504. ATOM_TRANSMITTER_ACTION_POWER_OFF);
  1505. radeon_dig_connector->edp_on = false;
  1506. }
  1507. }
  1508. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  1509. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
  1510. break;
  1511. }
  1512. }
  1513. static void
  1514. radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
  1515. struct drm_encoder *ext_encoder,
  1516. int mode)
  1517. {
  1518. struct drm_device *dev = encoder->dev;
  1519. struct radeon_device *rdev = dev->dev_private;
  1520. switch (mode) {
  1521. case DRM_MODE_DPMS_ON:
  1522. default:
  1523. if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
  1524. atombios_external_encoder_setup(encoder, ext_encoder,
  1525. EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
  1526. atombios_external_encoder_setup(encoder, ext_encoder,
  1527. EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
  1528. } else
  1529. atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
  1530. break;
  1531. case DRM_MODE_DPMS_STANDBY:
  1532. case DRM_MODE_DPMS_SUSPEND:
  1533. case DRM_MODE_DPMS_OFF:
  1534. if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
  1535. atombios_external_encoder_setup(encoder, ext_encoder,
  1536. EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
  1537. atombios_external_encoder_setup(encoder, ext_encoder,
  1538. EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
  1539. } else
  1540. atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
  1541. break;
  1542. }
  1543. }
  1544. static void
  1545. radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
  1546. {
  1547. struct drm_device *dev = encoder->dev;
  1548. struct radeon_device *rdev = dev->dev_private;
  1549. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1550. struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
  1551. DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
  1552. radeon_encoder->encoder_id, mode, radeon_encoder->devices,
  1553. radeon_encoder->active_device);
  1554. switch (radeon_encoder->encoder_id) {
  1555. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1556. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1557. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1558. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1559. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1560. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1561. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1562. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1563. radeon_atom_encoder_dpms_avivo(encoder, mode);
  1564. break;
  1565. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1566. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1567. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1568. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1569. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1570. radeon_atom_encoder_dpms_dig(encoder, mode);
  1571. break;
  1572. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1573. if (ASIC_IS_DCE5(rdev)) {
  1574. switch (mode) {
  1575. case DRM_MODE_DPMS_ON:
  1576. atombios_dvo_setup(encoder, ATOM_ENABLE);
  1577. break;
  1578. case DRM_MODE_DPMS_STANDBY:
  1579. case DRM_MODE_DPMS_SUSPEND:
  1580. case DRM_MODE_DPMS_OFF:
  1581. atombios_dvo_setup(encoder, ATOM_DISABLE);
  1582. break;
  1583. }
  1584. } else if (ASIC_IS_DCE3(rdev))
  1585. radeon_atom_encoder_dpms_dig(encoder, mode);
  1586. else
  1587. radeon_atom_encoder_dpms_avivo(encoder, mode);
  1588. break;
  1589. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1590. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1591. if (ASIC_IS_DCE5(rdev)) {
  1592. switch (mode) {
  1593. case DRM_MODE_DPMS_ON:
  1594. atombios_dac_setup(encoder, ATOM_ENABLE);
  1595. break;
  1596. case DRM_MODE_DPMS_STANDBY:
  1597. case DRM_MODE_DPMS_SUSPEND:
  1598. case DRM_MODE_DPMS_OFF:
  1599. atombios_dac_setup(encoder, ATOM_DISABLE);
  1600. break;
  1601. }
  1602. } else
  1603. radeon_atom_encoder_dpms_avivo(encoder, mode);
  1604. break;
  1605. default:
  1606. return;
  1607. }
  1608. if (ext_encoder)
  1609. radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
  1610. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  1611. }
  1612. union crtc_source_param {
  1613. SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
  1614. SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
  1615. };
  1616. static void
  1617. atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
  1618. {
  1619. struct drm_device *dev = encoder->dev;
  1620. struct radeon_device *rdev = dev->dev_private;
  1621. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1622. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1623. union crtc_source_param args;
  1624. int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
  1625. uint8_t frev, crev;
  1626. struct radeon_encoder_atom_dig *dig;
  1627. memset(&args, 0, sizeof(args));
  1628. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1629. return;
  1630. switch (frev) {
  1631. case 1:
  1632. switch (crev) {
  1633. case 1:
  1634. default:
  1635. if (ASIC_IS_AVIVO(rdev))
  1636. args.v1.ucCRTC = radeon_crtc->crtc_id;
  1637. else {
  1638. if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
  1639. args.v1.ucCRTC = radeon_crtc->crtc_id;
  1640. } else {
  1641. args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
  1642. }
  1643. }
  1644. switch (radeon_encoder->encoder_id) {
  1645. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1646. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1647. args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
  1648. break;
  1649. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1650. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1651. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
  1652. args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
  1653. else
  1654. args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
  1655. break;
  1656. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1657. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1658. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1659. args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
  1660. break;
  1661. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1662. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1663. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1664. args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
  1665. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1666. args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
  1667. else
  1668. args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
  1669. break;
  1670. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1671. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1672. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1673. args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
  1674. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1675. args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
  1676. else
  1677. args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
  1678. break;
  1679. }
  1680. break;
  1681. case 2:
  1682. args.v2.ucCRTC = radeon_crtc->crtc_id;
  1683. if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
  1684. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  1685. if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
  1686. args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
  1687. else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
  1688. args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
  1689. else
  1690. args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
  1691. } else
  1692. args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
  1693. switch (radeon_encoder->encoder_id) {
  1694. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1695. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1696. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1697. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1698. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1699. dig = radeon_encoder->enc_priv;
  1700. switch (dig->dig_encoder) {
  1701. case 0:
  1702. args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
  1703. break;
  1704. case 1:
  1705. args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
  1706. break;
  1707. case 2:
  1708. args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
  1709. break;
  1710. case 3:
  1711. args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
  1712. break;
  1713. case 4:
  1714. args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
  1715. break;
  1716. case 5:
  1717. args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
  1718. break;
  1719. case 6:
  1720. args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
  1721. break;
  1722. }
  1723. break;
  1724. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1725. args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
  1726. break;
  1727. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1728. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1729. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1730. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1731. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1732. else
  1733. args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
  1734. break;
  1735. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1736. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1737. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1738. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1739. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1740. else
  1741. args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
  1742. break;
  1743. }
  1744. break;
  1745. }
  1746. break;
  1747. default:
  1748. DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
  1749. return;
  1750. }
  1751. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1752. /* update scratch regs with new routing */
  1753. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1754. }
  1755. static void
  1756. atombios_apply_encoder_quirks(struct drm_encoder *encoder,
  1757. struct drm_display_mode *mode)
  1758. {
  1759. struct drm_device *dev = encoder->dev;
  1760. struct radeon_device *rdev = dev->dev_private;
  1761. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1762. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1763. /* Funky macbooks */
  1764. if ((dev->pdev->device == 0x71C5) &&
  1765. (dev->pdev->subsystem_vendor == 0x106b) &&
  1766. (dev->pdev->subsystem_device == 0x0080)) {
  1767. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
  1768. uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
  1769. lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
  1770. lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
  1771. WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
  1772. }
  1773. }
  1774. /* set scaler clears this on some chips */
  1775. if (ASIC_IS_AVIVO(rdev) &&
  1776. (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
  1777. if (ASIC_IS_DCE8(rdev)) {
  1778. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1779. WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
  1780. CIK_INTERLEAVE_EN);
  1781. else
  1782. WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
  1783. } else if (ASIC_IS_DCE4(rdev)) {
  1784. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1785. WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
  1786. EVERGREEN_INTERLEAVE_EN);
  1787. else
  1788. WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
  1789. } else {
  1790. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1791. WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
  1792. AVIVO_D1MODE_INTERLEAVE_EN);
  1793. else
  1794. WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
  1795. }
  1796. }
  1797. }
  1798. static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
  1799. {
  1800. struct drm_device *dev = encoder->dev;
  1801. struct radeon_device *rdev = dev->dev_private;
  1802. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1803. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1804. struct drm_encoder *test_encoder;
  1805. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  1806. uint32_t dig_enc_in_use = 0;
  1807. if (ASIC_IS_DCE6(rdev)) {
  1808. /* DCE6 */
  1809. switch (radeon_encoder->encoder_id) {
  1810. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1811. if (dig->linkb)
  1812. return 1;
  1813. else
  1814. return 0;
  1815. break;
  1816. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1817. if (dig->linkb)
  1818. return 3;
  1819. else
  1820. return 2;
  1821. break;
  1822. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1823. if (dig->linkb)
  1824. return 5;
  1825. else
  1826. return 4;
  1827. break;
  1828. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1829. return 6;
  1830. break;
  1831. }
  1832. } else if (ASIC_IS_DCE4(rdev)) {
  1833. /* DCE4/5 */
  1834. if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
  1835. /* ontario follows DCE4 */
  1836. if (rdev->family == CHIP_PALM) {
  1837. if (dig->linkb)
  1838. return 1;
  1839. else
  1840. return 0;
  1841. } else
  1842. /* llano follows DCE3.2 */
  1843. return radeon_crtc->crtc_id;
  1844. } else {
  1845. switch (radeon_encoder->encoder_id) {
  1846. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1847. if (dig->linkb)
  1848. return 1;
  1849. else
  1850. return 0;
  1851. break;
  1852. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1853. if (dig->linkb)
  1854. return 3;
  1855. else
  1856. return 2;
  1857. break;
  1858. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1859. if (dig->linkb)
  1860. return 5;
  1861. else
  1862. return 4;
  1863. break;
  1864. }
  1865. }
  1866. }
  1867. /* on DCE32 and encoder can driver any block so just crtc id */
  1868. if (ASIC_IS_DCE32(rdev)) {
  1869. return radeon_crtc->crtc_id;
  1870. }
  1871. /* on DCE3 - LVTMA can only be driven by DIGB */
  1872. list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
  1873. struct radeon_encoder *radeon_test_encoder;
  1874. if (encoder == test_encoder)
  1875. continue;
  1876. if (!radeon_encoder_is_digital(test_encoder))
  1877. continue;
  1878. radeon_test_encoder = to_radeon_encoder(test_encoder);
  1879. dig = radeon_test_encoder->enc_priv;
  1880. if (dig->dig_encoder >= 0)
  1881. dig_enc_in_use |= (1 << dig->dig_encoder);
  1882. }
  1883. if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
  1884. if (dig_enc_in_use & 0x2)
  1885. DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
  1886. return 1;
  1887. }
  1888. if (!(dig_enc_in_use & 1))
  1889. return 0;
  1890. return 1;
  1891. }
  1892. /* This only needs to be called once at startup */
  1893. void
  1894. radeon_atom_encoder_init(struct radeon_device *rdev)
  1895. {
  1896. struct drm_device *dev = rdev->ddev;
  1897. struct drm_encoder *encoder;
  1898. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1899. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1900. struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
  1901. switch (radeon_encoder->encoder_id) {
  1902. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1903. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1904. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1905. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1906. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1907. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
  1908. break;
  1909. default:
  1910. break;
  1911. }
  1912. if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
  1913. atombios_external_encoder_setup(encoder, ext_encoder,
  1914. EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
  1915. }
  1916. }
  1917. static void
  1918. radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
  1919. struct drm_display_mode *mode,
  1920. struct drm_display_mode *adjusted_mode)
  1921. {
  1922. struct drm_device *dev = encoder->dev;
  1923. struct radeon_device *rdev = dev->dev_private;
  1924. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1925. radeon_encoder->pixel_clock = adjusted_mode->clock;
  1926. /* need to call this here rather than in prepare() since we need some crtc info */
  1927. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  1928. if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
  1929. if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
  1930. atombios_yuv_setup(encoder, true);
  1931. else
  1932. atombios_yuv_setup(encoder, false);
  1933. }
  1934. switch (radeon_encoder->encoder_id) {
  1935. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1936. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1937. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1938. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1939. atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
  1940. break;
  1941. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1942. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1943. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1944. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1945. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1946. /* handled in dpms */
  1947. break;
  1948. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1949. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1950. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1951. atombios_dvo_setup(encoder, ATOM_ENABLE);
  1952. break;
  1953. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1954. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1955. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1956. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1957. atombios_dac_setup(encoder, ATOM_ENABLE);
  1958. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
  1959. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
  1960. atombios_tv_setup(encoder, ATOM_ENABLE);
  1961. else
  1962. atombios_tv_setup(encoder, ATOM_DISABLE);
  1963. }
  1964. break;
  1965. }
  1966. atombios_apply_encoder_quirks(encoder, adjusted_mode);
  1967. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
  1968. if (rdev->asic->display.hdmi_enable)
  1969. radeon_hdmi_enable(rdev, encoder, true);
  1970. if (rdev->asic->display.hdmi_setmode)
  1971. radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
  1972. }
  1973. }
  1974. static bool
  1975. atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  1976. {
  1977. struct drm_device *dev = encoder->dev;
  1978. struct radeon_device *rdev = dev->dev_private;
  1979. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1980. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  1981. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
  1982. ATOM_DEVICE_CV_SUPPORT |
  1983. ATOM_DEVICE_CRT_SUPPORT)) {
  1984. DAC_LOAD_DETECTION_PS_ALLOCATION args;
  1985. int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
  1986. uint8_t frev, crev;
  1987. memset(&args, 0, sizeof(args));
  1988. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1989. return false;
  1990. args.sDacload.ucMisc = 0;
  1991. if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
  1992. (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
  1993. args.sDacload.ucDacType = ATOM_DAC_A;
  1994. else
  1995. args.sDacload.ucDacType = ATOM_DAC_B;
  1996. if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
  1997. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
  1998. else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
  1999. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
  2000. else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
  2001. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
  2002. if (crev >= 3)
  2003. args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
  2004. } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
  2005. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
  2006. if (crev >= 3)
  2007. args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
  2008. }
  2009. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  2010. return true;
  2011. } else
  2012. return false;
  2013. }
  2014. static enum drm_connector_status
  2015. radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  2016. {
  2017. struct drm_device *dev = encoder->dev;
  2018. struct radeon_device *rdev = dev->dev_private;
  2019. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  2020. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  2021. uint32_t bios_0_scratch;
  2022. if (!atombios_dac_load_detect(encoder, connector)) {
  2023. DRM_DEBUG_KMS("detect returned false \n");
  2024. return connector_status_unknown;
  2025. }
  2026. if (rdev->family >= CHIP_R600)
  2027. bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
  2028. else
  2029. bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
  2030. DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
  2031. if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
  2032. if (bios_0_scratch & ATOM_S0_CRT1_MASK)
  2033. return connector_status_connected;
  2034. }
  2035. if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
  2036. if (bios_0_scratch & ATOM_S0_CRT2_MASK)
  2037. return connector_status_connected;
  2038. }
  2039. if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
  2040. if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
  2041. return connector_status_connected;
  2042. }
  2043. if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
  2044. if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
  2045. return connector_status_connected; /* CTV */
  2046. else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
  2047. return connector_status_connected; /* STV */
  2048. }
  2049. return connector_status_disconnected;
  2050. }
  2051. static enum drm_connector_status
  2052. radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  2053. {
  2054. struct drm_device *dev = encoder->dev;
  2055. struct radeon_device *rdev = dev->dev_private;
  2056. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  2057. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  2058. struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
  2059. u32 bios_0_scratch;
  2060. if (!ASIC_IS_DCE4(rdev))
  2061. return connector_status_unknown;
  2062. if (!ext_encoder)
  2063. return connector_status_unknown;
  2064. if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
  2065. return connector_status_unknown;
  2066. /* load detect on the dp bridge */
  2067. atombios_external_encoder_setup(encoder, ext_encoder,
  2068. EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
  2069. bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
  2070. DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
  2071. if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
  2072. if (bios_0_scratch & ATOM_S0_CRT1_MASK)
  2073. return connector_status_connected;
  2074. }
  2075. if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
  2076. if (bios_0_scratch & ATOM_S0_CRT2_MASK)
  2077. return connector_status_connected;
  2078. }
  2079. if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
  2080. if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
  2081. return connector_status_connected;
  2082. }
  2083. if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
  2084. if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
  2085. return connector_status_connected; /* CTV */
  2086. else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
  2087. return connector_status_connected; /* STV */
  2088. }
  2089. return connector_status_disconnected;
  2090. }
  2091. void
  2092. radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
  2093. {
  2094. struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
  2095. if (ext_encoder)
  2096. /* ddc_setup on the dp bridge */
  2097. atombios_external_encoder_setup(encoder, ext_encoder,
  2098. EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
  2099. }
  2100. static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
  2101. {
  2102. struct radeon_device *rdev = encoder->dev->dev_private;
  2103. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  2104. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  2105. if ((radeon_encoder->active_device &
  2106. (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
  2107. (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
  2108. ENCODER_OBJECT_ID_NONE)) {
  2109. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  2110. if (dig) {
  2111. dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
  2112. if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
  2113. if (rdev->family >= CHIP_R600)
  2114. dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
  2115. else
  2116. /* RS600/690/740 have only 1 afmt block */
  2117. dig->afmt = rdev->mode_info.afmt[0];
  2118. }
  2119. }
  2120. }
  2121. radeon_atom_output_lock(encoder, true);
  2122. if (connector) {
  2123. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  2124. /* select the clock/data port if it uses a router */
  2125. if (radeon_connector->router.cd_valid)
  2126. radeon_router_select_cd_port(radeon_connector);
  2127. /* turn eDP panel on for mode set */
  2128. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  2129. atombios_set_edp_panel_power(connector,
  2130. ATOM_TRANSMITTER_ACTION_POWER_ON);
  2131. }
  2132. /* this is needed for the pll/ss setup to work correctly in some cases */
  2133. atombios_set_encoder_crtc_source(encoder);
  2134. }
  2135. static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
  2136. {
  2137. /* need to call this here as we need the crtc set up */
  2138. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
  2139. radeon_atom_output_lock(encoder, false);
  2140. }
  2141. static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
  2142. {
  2143. struct drm_device *dev = encoder->dev;
  2144. struct radeon_device *rdev = dev->dev_private;
  2145. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  2146. struct radeon_encoder_atom_dig *dig;
  2147. /* check for pre-DCE3 cards with shared encoders;
  2148. * can't really use the links individually, so don't disable
  2149. * the encoder if it's in use by another connector
  2150. */
  2151. if (!ASIC_IS_DCE3(rdev)) {
  2152. struct drm_encoder *other_encoder;
  2153. struct radeon_encoder *other_radeon_encoder;
  2154. list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
  2155. other_radeon_encoder = to_radeon_encoder(other_encoder);
  2156. if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
  2157. drm_helper_encoder_in_use(other_encoder))
  2158. goto disable_done;
  2159. }
  2160. }
  2161. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  2162. switch (radeon_encoder->encoder_id) {
  2163. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  2164. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  2165. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  2166. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  2167. atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
  2168. break;
  2169. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  2170. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  2171. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  2172. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  2173. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  2174. /* handled in dpms */
  2175. break;
  2176. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  2177. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  2178. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  2179. atombios_dvo_setup(encoder, ATOM_DISABLE);
  2180. break;
  2181. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  2182. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  2183. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  2184. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  2185. atombios_dac_setup(encoder, ATOM_DISABLE);
  2186. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
  2187. atombios_tv_setup(encoder, ATOM_DISABLE);
  2188. break;
  2189. }
  2190. disable_done:
  2191. if (radeon_encoder_is_digital(encoder)) {
  2192. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
  2193. if (rdev->asic->display.hdmi_enable)
  2194. radeon_hdmi_enable(rdev, encoder, false);
  2195. }
  2196. dig = radeon_encoder->enc_priv;
  2197. dig->dig_encoder = -1;
  2198. }
  2199. radeon_encoder->active_device = 0;
  2200. }
  2201. /* these are handled by the primary encoders */
  2202. static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
  2203. {
  2204. }
  2205. static void radeon_atom_ext_commit(struct drm_encoder *encoder)
  2206. {
  2207. }
  2208. static void
  2209. radeon_atom_ext_mode_set(struct drm_encoder *encoder,
  2210. struct drm_display_mode *mode,
  2211. struct drm_display_mode *adjusted_mode)
  2212. {
  2213. }
  2214. static void radeon_atom_ext_disable(struct drm_encoder *encoder)
  2215. {
  2216. }
  2217. static void
  2218. radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
  2219. {
  2220. }
  2221. static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
  2222. const struct drm_display_mode *mode,
  2223. struct drm_display_mode *adjusted_mode)
  2224. {
  2225. return true;
  2226. }
  2227. static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
  2228. .dpms = radeon_atom_ext_dpms,
  2229. .mode_fixup = radeon_atom_ext_mode_fixup,
  2230. .prepare = radeon_atom_ext_prepare,
  2231. .mode_set = radeon_atom_ext_mode_set,
  2232. .commit = radeon_atom_ext_commit,
  2233. .disable = radeon_atom_ext_disable,
  2234. /* no detect for TMDS/LVDS yet */
  2235. };
  2236. static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
  2237. .dpms = radeon_atom_encoder_dpms,
  2238. .mode_fixup = radeon_atom_mode_fixup,
  2239. .prepare = radeon_atom_encoder_prepare,
  2240. .mode_set = radeon_atom_encoder_mode_set,
  2241. .commit = radeon_atom_encoder_commit,
  2242. .disable = radeon_atom_encoder_disable,
  2243. .detect = radeon_atom_dig_detect,
  2244. };
  2245. static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
  2246. .dpms = radeon_atom_encoder_dpms,
  2247. .mode_fixup = radeon_atom_mode_fixup,
  2248. .prepare = radeon_atom_encoder_prepare,
  2249. .mode_set = radeon_atom_encoder_mode_set,
  2250. .commit = radeon_atom_encoder_commit,
  2251. .detect = radeon_atom_dac_detect,
  2252. };
  2253. void radeon_enc_destroy(struct drm_encoder *encoder)
  2254. {
  2255. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  2256. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  2257. radeon_atom_backlight_exit(radeon_encoder);
  2258. kfree(radeon_encoder->enc_priv);
  2259. drm_encoder_cleanup(encoder);
  2260. kfree(radeon_encoder);
  2261. }
  2262. static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
  2263. .destroy = radeon_enc_destroy,
  2264. };
  2265. static struct radeon_encoder_atom_dac *
  2266. radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
  2267. {
  2268. struct drm_device *dev = radeon_encoder->base.dev;
  2269. struct radeon_device *rdev = dev->dev_private;
  2270. struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
  2271. if (!dac)
  2272. return NULL;
  2273. dac->tv_std = radeon_atombios_get_tv_info(rdev);
  2274. return dac;
  2275. }
  2276. static struct radeon_encoder_atom_dig *
  2277. radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
  2278. {
  2279. int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
  2280. struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
  2281. if (!dig)
  2282. return NULL;
  2283. /* coherent mode by default */
  2284. dig->coherent_mode = true;
  2285. dig->dig_encoder = -1;
  2286. if (encoder_enum == 2)
  2287. dig->linkb = true;
  2288. else
  2289. dig->linkb = false;
  2290. return dig;
  2291. }
  2292. void
  2293. radeon_add_atom_encoder(struct drm_device *dev,
  2294. uint32_t encoder_enum,
  2295. uint32_t supported_device,
  2296. u16 caps)
  2297. {
  2298. struct radeon_device *rdev = dev->dev_private;
  2299. struct drm_encoder *encoder;
  2300. struct radeon_encoder *radeon_encoder;
  2301. /* see if we already added it */
  2302. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2303. radeon_encoder = to_radeon_encoder(encoder);
  2304. if (radeon_encoder->encoder_enum == encoder_enum) {
  2305. radeon_encoder->devices |= supported_device;
  2306. return;
  2307. }
  2308. }
  2309. /* add a new one */
  2310. radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  2311. if (!radeon_encoder)
  2312. return;
  2313. encoder = &radeon_encoder->base;
  2314. switch (rdev->num_crtc) {
  2315. case 1:
  2316. encoder->possible_crtcs = 0x1;
  2317. break;
  2318. case 2:
  2319. default:
  2320. encoder->possible_crtcs = 0x3;
  2321. break;
  2322. case 4:
  2323. encoder->possible_crtcs = 0xf;
  2324. break;
  2325. case 6:
  2326. encoder->possible_crtcs = 0x3f;
  2327. break;
  2328. }
  2329. radeon_encoder->enc_priv = NULL;
  2330. radeon_encoder->encoder_enum = encoder_enum;
  2331. radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  2332. radeon_encoder->devices = supported_device;
  2333. radeon_encoder->rmx_type = RMX_OFF;
  2334. radeon_encoder->underscan_type = UNDERSCAN_OFF;
  2335. radeon_encoder->is_ext_encoder = false;
  2336. radeon_encoder->caps = caps;
  2337. switch (radeon_encoder->encoder_id) {
  2338. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  2339. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  2340. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  2341. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  2342. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  2343. radeon_encoder->rmx_type = RMX_FULL;
  2344. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
  2345. radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  2346. } else {
  2347. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
  2348. radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
  2349. }
  2350. drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
  2351. break;
  2352. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  2353. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
  2354. radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
  2355. drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
  2356. break;
  2357. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  2358. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  2359. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  2360. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  2361. radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
  2362. drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
  2363. break;
  2364. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  2365. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  2366. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  2367. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  2368. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  2369. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  2370. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  2371. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  2372. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  2373. radeon_encoder->rmx_type = RMX_FULL;
  2374. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
  2375. radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  2376. } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
  2377. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
  2378. radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
  2379. } else {
  2380. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
  2381. radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
  2382. }
  2383. drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
  2384. break;
  2385. case ENCODER_OBJECT_ID_SI170B:
  2386. case ENCODER_OBJECT_ID_CH7303:
  2387. case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
  2388. case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
  2389. case ENCODER_OBJECT_ID_TITFP513:
  2390. case ENCODER_OBJECT_ID_VT1623:
  2391. case ENCODER_OBJECT_ID_HDMI_SI1930:
  2392. case ENCODER_OBJECT_ID_TRAVIS:
  2393. case ENCODER_OBJECT_ID_NUTMEG:
  2394. /* these are handled by the primary encoders */
  2395. radeon_encoder->is_ext_encoder = true;
  2396. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  2397. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
  2398. else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
  2399. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
  2400. else
  2401. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
  2402. drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
  2403. break;
  2404. }
  2405. }