psb_intel_sdvo.c 82 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/module.h>
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "psb_intel_drv.h"
  36. #include <drm/gma_drm.h>
  37. #include "psb_drv.h"
  38. #include "psb_intel_sdvo_regs.h"
  39. #include "psb_intel_reg.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct psb_intel_sdvo {
  61. struct gma_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. int sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct psb_intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /**
  82. * This is used to select the color range of RBG outputs in HDMI mode.
  83. * It is only valid when using TMDS encoding and 8 bit per color mode.
  84. */
  85. uint32_t color_range;
  86. /**
  87. * This is set if we're going to treat the device as TV-out.
  88. *
  89. * While we have these nice friendly flags for output types that ought
  90. * to decide this for us, the S-Video output on our HDMI+S-Video card
  91. * shows up as RGB1 (VGA).
  92. */
  93. bool is_tv;
  94. /* This is for current tv format name */
  95. int tv_format_index;
  96. /**
  97. * This is set if we treat the device as HDMI, instead of DVI.
  98. */
  99. bool is_hdmi;
  100. bool has_hdmi_monitor;
  101. bool has_hdmi_audio;
  102. /**
  103. * This is set if we detect output of sdvo device as LVDS and
  104. * have a valid fixed mode to use with the panel.
  105. */
  106. bool is_lvds;
  107. /**
  108. * This is sdvo fixed pannel mode pointer
  109. */
  110. struct drm_display_mode *sdvo_lvds_fixed_mode;
  111. /* DDC bus used by this SDVO encoder */
  112. uint8_t ddc_bus;
  113. /* Input timings for adjusted_mode */
  114. struct psb_intel_sdvo_dtd input_dtd;
  115. /* Saved SDVO output states */
  116. uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */
  117. };
  118. struct psb_intel_sdvo_connector {
  119. struct gma_connector base;
  120. /* Mark the type of connector */
  121. uint16_t output_flag;
  122. int force_audio;
  123. /* This contains all current supported TV format */
  124. u8 tv_format_supported[TV_FORMAT_NUM];
  125. int format_supported_num;
  126. struct drm_property *tv_format;
  127. /* add the property for the SDVO-TV */
  128. struct drm_property *left;
  129. struct drm_property *right;
  130. struct drm_property *top;
  131. struct drm_property *bottom;
  132. struct drm_property *hpos;
  133. struct drm_property *vpos;
  134. struct drm_property *contrast;
  135. struct drm_property *saturation;
  136. struct drm_property *hue;
  137. struct drm_property *sharpness;
  138. struct drm_property *flicker_filter;
  139. struct drm_property *flicker_filter_adaptive;
  140. struct drm_property *flicker_filter_2d;
  141. struct drm_property *tv_chroma_filter;
  142. struct drm_property *tv_luma_filter;
  143. struct drm_property *dot_crawl;
  144. /* add the property for the SDVO-TV/LVDS */
  145. struct drm_property *brightness;
  146. /* Add variable to record current setting for the above property */
  147. u32 left_margin, right_margin, top_margin, bottom_margin;
  148. /* this is to get the range of margin.*/
  149. u32 max_hscan, max_vscan;
  150. u32 max_hpos, cur_hpos;
  151. u32 max_vpos, cur_vpos;
  152. u32 cur_brightness, max_brightness;
  153. u32 cur_contrast, max_contrast;
  154. u32 cur_saturation, max_saturation;
  155. u32 cur_hue, max_hue;
  156. u32 cur_sharpness, max_sharpness;
  157. u32 cur_flicker_filter, max_flicker_filter;
  158. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  159. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  160. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  161. u32 cur_tv_luma_filter, max_tv_luma_filter;
  162. u32 cur_dot_crawl, max_dot_crawl;
  163. };
  164. static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
  165. {
  166. return container_of(encoder, struct psb_intel_sdvo, base.base);
  167. }
  168. static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  169. {
  170. return container_of(gma_attached_encoder(connector),
  171. struct psb_intel_sdvo, base);
  172. }
  173. static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
  174. {
  175. return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base);
  176. }
  177. static bool
  178. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
  179. static bool
  180. psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  181. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  182. int type);
  183. static bool
  184. psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  185. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
  186. /**
  187. * Writes the SDVOB or SDVOC with the given value, but always writes both
  188. * SDVOB and SDVOC to work around apparent hardware issues (according to
  189. * comments in the BIOS).
  190. */
  191. static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
  192. {
  193. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  194. u32 bval = val, cval = val;
  195. int i;
  196. if (psb_intel_sdvo->sdvo_reg == SDVOB) {
  197. cval = REG_READ(SDVOC);
  198. } else {
  199. bval = REG_READ(SDVOB);
  200. }
  201. /*
  202. * Write the registers twice for luck. Sometimes,
  203. * writing them only once doesn't appear to 'stick'.
  204. * The BIOS does this too. Yay, magic
  205. */
  206. for (i = 0; i < 2; i++)
  207. {
  208. REG_WRITE(SDVOB, bval);
  209. REG_READ(SDVOB);
  210. REG_WRITE(SDVOC, cval);
  211. REG_READ(SDVOC);
  212. }
  213. }
  214. static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
  215. {
  216. struct i2c_msg msgs[] = {
  217. {
  218. .addr = psb_intel_sdvo->slave_addr,
  219. .flags = 0,
  220. .len = 1,
  221. .buf = &addr,
  222. },
  223. {
  224. .addr = psb_intel_sdvo->slave_addr,
  225. .flags = I2C_M_RD,
  226. .len = 1,
  227. .buf = ch,
  228. }
  229. };
  230. int ret;
  231. if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
  232. return true;
  233. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  234. return false;
  235. }
  236. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  237. /** Mapping of command numbers to names, for debug output */
  238. static const struct _sdvo_cmd_name {
  239. u8 cmd;
  240. const char *name;
  241. } sdvo_cmd_names[] = {
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  285. /* Add the op code for SDVO enhancements */
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  330. /* HDMI op code */
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  351. };
  352. #define IS_SDVOB(reg) (reg == SDVOB)
  353. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  354. static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  355. const void *args, int args_len)
  356. {
  357. int i;
  358. DRM_DEBUG_KMS("%s: W: %02X ",
  359. SDVO_NAME(psb_intel_sdvo), cmd);
  360. for (i = 0; i < args_len; i++)
  361. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  362. for (; i < 8; i++)
  363. DRM_LOG_KMS(" ");
  364. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  365. if (cmd == sdvo_cmd_names[i].cmd) {
  366. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  367. break;
  368. }
  369. }
  370. if (i == ARRAY_SIZE(sdvo_cmd_names))
  371. DRM_LOG_KMS("(%02X)", cmd);
  372. DRM_LOG_KMS("\n");
  373. }
  374. static const char *cmd_status_names[] = {
  375. "Power on",
  376. "Success",
  377. "Not supported",
  378. "Invalid arg",
  379. "Pending",
  380. "Target not specified",
  381. "Scaling not supported"
  382. };
  383. static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  384. const void *args, int args_len)
  385. {
  386. u8 buf[args_len*2 + 2], status;
  387. struct i2c_msg msgs[args_len + 3];
  388. int i, ret;
  389. psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
  390. for (i = 0; i < args_len; i++) {
  391. msgs[i].addr = psb_intel_sdvo->slave_addr;
  392. msgs[i].flags = 0;
  393. msgs[i].len = 2;
  394. msgs[i].buf = buf + 2 *i;
  395. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  396. buf[2*i + 1] = ((u8*)args)[i];
  397. }
  398. msgs[i].addr = psb_intel_sdvo->slave_addr;
  399. msgs[i].flags = 0;
  400. msgs[i].len = 2;
  401. msgs[i].buf = buf + 2*i;
  402. buf[2*i + 0] = SDVO_I2C_OPCODE;
  403. buf[2*i + 1] = cmd;
  404. /* the following two are to read the response */
  405. status = SDVO_I2C_CMD_STATUS;
  406. msgs[i+1].addr = psb_intel_sdvo->slave_addr;
  407. msgs[i+1].flags = 0;
  408. msgs[i+1].len = 1;
  409. msgs[i+1].buf = &status;
  410. msgs[i+2].addr = psb_intel_sdvo->slave_addr;
  411. msgs[i+2].flags = I2C_M_RD;
  412. msgs[i+2].len = 1;
  413. msgs[i+2].buf = &status;
  414. ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
  415. if (ret < 0) {
  416. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  417. return false;
  418. }
  419. if (ret != i+3) {
  420. /* failure in I2C transfer */
  421. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  422. return false;
  423. }
  424. return true;
  425. }
  426. static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
  427. void *response, int response_len)
  428. {
  429. u8 retry = 5;
  430. u8 status;
  431. int i;
  432. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
  433. /*
  434. * The documentation states that all commands will be
  435. * processed within 15µs, and that we need only poll
  436. * the status byte a maximum of 3 times in order for the
  437. * command to be complete.
  438. *
  439. * Check 5 times in case the hardware failed to read the docs.
  440. */
  441. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  442. SDVO_I2C_CMD_STATUS,
  443. &status))
  444. goto log_fail;
  445. while ((status == SDVO_CMD_STATUS_PENDING ||
  446. status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) {
  447. udelay(15);
  448. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  449. SDVO_I2C_CMD_STATUS,
  450. &status))
  451. goto log_fail;
  452. }
  453. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  454. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  455. else
  456. DRM_LOG_KMS("(??? %d)", status);
  457. if (status != SDVO_CMD_STATUS_SUCCESS)
  458. goto log_fail;
  459. /* Read the command response */
  460. for (i = 0; i < response_len; i++) {
  461. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  462. SDVO_I2C_RETURN_0 + i,
  463. &((u8 *)response)[i]))
  464. goto log_fail;
  465. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  466. }
  467. DRM_LOG_KMS("\n");
  468. return true;
  469. log_fail:
  470. DRM_LOG_KMS("... failed\n");
  471. return false;
  472. }
  473. static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  474. {
  475. if (mode->clock >= 100000)
  476. return 1;
  477. else if (mode->clock >= 50000)
  478. return 2;
  479. else
  480. return 4;
  481. }
  482. static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
  483. u8 ddc_bus)
  484. {
  485. /* This must be the immediately preceding write before the i2c xfer */
  486. return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  487. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  488. &ddc_bus, 1);
  489. }
  490. static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
  491. {
  492. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
  493. return false;
  494. return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
  495. }
  496. static bool
  497. psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
  498. {
  499. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
  500. return false;
  501. return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
  502. }
  503. static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
  504. {
  505. struct psb_intel_sdvo_set_target_input_args targets = {0};
  506. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  507. SDVO_CMD_SET_TARGET_INPUT,
  508. &targets, sizeof(targets));
  509. }
  510. /**
  511. * Return whether each input is trained.
  512. *
  513. * This function is making an assumption about the layout of the response,
  514. * which should be checked against the docs.
  515. */
  516. static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
  517. {
  518. struct psb_intel_sdvo_get_trained_inputs_response response;
  519. BUILD_BUG_ON(sizeof(response) != 1);
  520. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  521. &response, sizeof(response)))
  522. return false;
  523. *input_1 = response.input0_trained;
  524. *input_2 = response.input1_trained;
  525. return true;
  526. }
  527. static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
  528. u16 outputs)
  529. {
  530. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  531. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  532. &outputs, sizeof(outputs));
  533. }
  534. static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
  535. int mode)
  536. {
  537. u8 state = SDVO_ENCODER_STATE_ON;
  538. switch (mode) {
  539. case DRM_MODE_DPMS_ON:
  540. state = SDVO_ENCODER_STATE_ON;
  541. break;
  542. case DRM_MODE_DPMS_STANDBY:
  543. state = SDVO_ENCODER_STATE_STANDBY;
  544. break;
  545. case DRM_MODE_DPMS_SUSPEND:
  546. state = SDVO_ENCODER_STATE_SUSPEND;
  547. break;
  548. case DRM_MODE_DPMS_OFF:
  549. state = SDVO_ENCODER_STATE_OFF;
  550. break;
  551. }
  552. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  553. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  554. }
  555. static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
  556. int *clock_min,
  557. int *clock_max)
  558. {
  559. struct psb_intel_sdvo_pixel_clock_range clocks;
  560. BUILD_BUG_ON(sizeof(clocks) != 4);
  561. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  562. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  563. &clocks, sizeof(clocks)))
  564. return false;
  565. /* Convert the values from units of 10 kHz to kHz. */
  566. *clock_min = clocks.min * 10;
  567. *clock_max = clocks.max * 10;
  568. return true;
  569. }
  570. static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
  571. u16 outputs)
  572. {
  573. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  574. SDVO_CMD_SET_TARGET_OUTPUT,
  575. &outputs, sizeof(outputs));
  576. }
  577. static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  578. struct psb_intel_sdvo_dtd *dtd)
  579. {
  580. return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  581. psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  582. }
  583. static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  584. struct psb_intel_sdvo_dtd *dtd)
  585. {
  586. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  587. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  588. }
  589. static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  590. struct psb_intel_sdvo_dtd *dtd)
  591. {
  592. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  593. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  594. }
  595. static bool
  596. psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  597. uint16_t clock,
  598. uint16_t width,
  599. uint16_t height)
  600. {
  601. struct psb_intel_sdvo_preferred_input_timing_args args;
  602. memset(&args, 0, sizeof(args));
  603. args.clock = clock;
  604. args.width = width;
  605. args.height = height;
  606. args.interlace = 0;
  607. if (psb_intel_sdvo->is_lvds &&
  608. (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  609. psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  610. args.scaled = 1;
  611. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  612. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  613. &args, sizeof(args));
  614. }
  615. static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  616. struct psb_intel_sdvo_dtd *dtd)
  617. {
  618. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  619. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  620. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  621. &dtd->part1, sizeof(dtd->part1)) &&
  622. psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  623. &dtd->part2, sizeof(dtd->part2));
  624. }
  625. static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
  626. {
  627. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  628. }
  629. static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
  630. const struct drm_display_mode *mode)
  631. {
  632. uint16_t width, height;
  633. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  634. uint16_t h_sync_offset, v_sync_offset;
  635. width = mode->crtc_hdisplay;
  636. height = mode->crtc_vdisplay;
  637. /* do some mode translations */
  638. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  639. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  640. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  641. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  642. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  643. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  644. dtd->part1.clock = mode->clock / 10;
  645. dtd->part1.h_active = width & 0xff;
  646. dtd->part1.h_blank = h_blank_len & 0xff;
  647. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  648. ((h_blank_len >> 8) & 0xf);
  649. dtd->part1.v_active = height & 0xff;
  650. dtd->part1.v_blank = v_blank_len & 0xff;
  651. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  652. ((v_blank_len >> 8) & 0xf);
  653. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  654. dtd->part2.h_sync_width = h_sync_len & 0xff;
  655. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  656. (v_sync_len & 0xf);
  657. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  658. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  659. ((v_sync_len & 0x30) >> 4);
  660. dtd->part2.dtd_flags = 0x18;
  661. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  662. dtd->part2.dtd_flags |= 0x2;
  663. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  664. dtd->part2.dtd_flags |= 0x4;
  665. dtd->part2.sdvo_flags = 0;
  666. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  667. dtd->part2.reserved = 0;
  668. }
  669. static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  670. const struct psb_intel_sdvo_dtd *dtd)
  671. {
  672. mode->hdisplay = dtd->part1.h_active;
  673. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  674. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  675. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  676. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  677. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  678. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  679. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  680. mode->vdisplay = dtd->part1.v_active;
  681. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  682. mode->vsync_start = mode->vdisplay;
  683. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  684. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  685. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  686. mode->vsync_end = mode->vsync_start +
  687. (dtd->part2.v_sync_off_width & 0xf);
  688. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  689. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  690. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  691. mode->clock = dtd->part1.clock * 10;
  692. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  693. if (dtd->part2.dtd_flags & 0x2)
  694. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  695. if (dtd->part2.dtd_flags & 0x4)
  696. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  697. }
  698. static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
  699. {
  700. struct psb_intel_sdvo_encode encode;
  701. BUILD_BUG_ON(sizeof(encode) != 2);
  702. return psb_intel_sdvo_get_value(psb_intel_sdvo,
  703. SDVO_CMD_GET_SUPP_ENCODE,
  704. &encode, sizeof(encode));
  705. }
  706. static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
  707. uint8_t mode)
  708. {
  709. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  710. }
  711. static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
  712. uint8_t mode)
  713. {
  714. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  715. }
  716. #if 0
  717. static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
  718. {
  719. int i, j;
  720. uint8_t set_buf_index[2];
  721. uint8_t av_split;
  722. uint8_t buf_size;
  723. uint8_t buf[48];
  724. uint8_t *pos;
  725. psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  726. for (i = 0; i <= av_split; i++) {
  727. set_buf_index[0] = i; set_buf_index[1] = 0;
  728. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  729. set_buf_index, 2);
  730. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  731. psb_intel_sdvo_read_response(encoder, &buf_size, 1);
  732. pos = buf;
  733. for (j = 0; j <= buf_size; j += 8) {
  734. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  735. NULL, 0);
  736. psb_intel_sdvo_read_response(encoder, pos, 8);
  737. pos += 8;
  738. }
  739. }
  740. }
  741. #endif
  742. static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
  743. {
  744. DRM_INFO("HDMI is not supported yet");
  745. return false;
  746. #if 0
  747. struct dip_infoframe avi_if = {
  748. .type = DIP_TYPE_AVI,
  749. .ver = DIP_VERSION_AVI,
  750. .len = DIP_LEN_AVI,
  751. };
  752. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  753. uint8_t set_buf_index[2] = { 1, 0 };
  754. uint64_t *data = (uint64_t *)&avi_if;
  755. unsigned i;
  756. intel_dip_infoframe_csum(&avi_if);
  757. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  758. SDVO_CMD_SET_HBUF_INDEX,
  759. set_buf_index, 2))
  760. return false;
  761. for (i = 0; i < sizeof(avi_if); i += 8) {
  762. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  763. SDVO_CMD_SET_HBUF_DATA,
  764. data, 8))
  765. return false;
  766. data++;
  767. }
  768. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  769. SDVO_CMD_SET_HBUF_TXRATE,
  770. &tx_rate, 1);
  771. #endif
  772. }
  773. static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
  774. {
  775. struct psb_intel_sdvo_tv_format format;
  776. uint32_t format_map;
  777. format_map = 1 << psb_intel_sdvo->tv_format_index;
  778. memset(&format, 0, sizeof(format));
  779. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  780. BUILD_BUG_ON(sizeof(format) != 6);
  781. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  782. SDVO_CMD_SET_TV_FORMAT,
  783. &format, sizeof(format));
  784. }
  785. static bool
  786. psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  787. const struct drm_display_mode *mode)
  788. {
  789. struct psb_intel_sdvo_dtd output_dtd;
  790. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  791. psb_intel_sdvo->attached_output))
  792. return false;
  793. psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  794. if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
  795. return false;
  796. return true;
  797. }
  798. static bool
  799. psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  800. const struct drm_display_mode *mode,
  801. struct drm_display_mode *adjusted_mode)
  802. {
  803. /* Reset the input timing to the screen. Assume always input 0. */
  804. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  805. return false;
  806. if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
  807. mode->clock / 10,
  808. mode->hdisplay,
  809. mode->vdisplay))
  810. return false;
  811. if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
  812. &psb_intel_sdvo->input_dtd))
  813. return false;
  814. psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
  815. drm_mode_set_crtcinfo(adjusted_mode, 0);
  816. return true;
  817. }
  818. static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  819. const struct drm_display_mode *mode,
  820. struct drm_display_mode *adjusted_mode)
  821. {
  822. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  823. int multiplier;
  824. /* We need to construct preferred input timings based on our
  825. * output timings. To do that, we have to set the output
  826. * timings, even though this isn't really the right place in
  827. * the sequence to do it. Oh well.
  828. */
  829. if (psb_intel_sdvo->is_tv) {
  830. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
  831. return false;
  832. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  833. mode,
  834. adjusted_mode);
  835. } else if (psb_intel_sdvo->is_lvds) {
  836. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
  837. psb_intel_sdvo->sdvo_lvds_fixed_mode))
  838. return false;
  839. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  840. mode,
  841. adjusted_mode);
  842. }
  843. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  844. * SDVO device will factor out the multiplier during mode_set.
  845. */
  846. multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
  847. psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  848. return true;
  849. }
  850. static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
  851. struct drm_display_mode *mode,
  852. struct drm_display_mode *adjusted_mode)
  853. {
  854. struct drm_device *dev = encoder->dev;
  855. struct drm_crtc *crtc = encoder->crtc;
  856. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  857. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  858. u32 sdvox;
  859. struct psb_intel_sdvo_in_out_map in_out;
  860. struct psb_intel_sdvo_dtd input_dtd;
  861. int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
  862. int rate;
  863. if (!mode)
  864. return;
  865. /* First, set the input mapping for the first input to our controlled
  866. * output. This is only correct if we're a single-input device, in
  867. * which case the first input is the output from the appropriate SDVO
  868. * channel on the motherboard. In a two-input device, the first input
  869. * will be SDVOB and the second SDVOC.
  870. */
  871. in_out.in0 = psb_intel_sdvo->attached_output;
  872. in_out.in1 = 0;
  873. psb_intel_sdvo_set_value(psb_intel_sdvo,
  874. SDVO_CMD_SET_IN_OUT_MAP,
  875. &in_out, sizeof(in_out));
  876. /* Set the output timings to the screen */
  877. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  878. psb_intel_sdvo->attached_output))
  879. return;
  880. /* We have tried to get input timing in mode_fixup, and filled into
  881. * adjusted_mode.
  882. */
  883. if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
  884. input_dtd = psb_intel_sdvo->input_dtd;
  885. } else {
  886. /* Set the output timing to the screen */
  887. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  888. psb_intel_sdvo->attached_output))
  889. return;
  890. psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  891. (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
  892. }
  893. /* Set the input timing to the screen. Assume always input 0. */
  894. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  895. return;
  896. if (psb_intel_sdvo->has_hdmi_monitor) {
  897. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
  898. psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
  899. SDVO_COLORIMETRY_RGB256);
  900. psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
  901. } else
  902. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
  903. if (psb_intel_sdvo->is_tv &&
  904. !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
  905. return;
  906. (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
  907. switch (pixel_multiplier) {
  908. default:
  909. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  910. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  911. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  912. }
  913. if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
  914. return;
  915. /* Set the SDVO control regs. */
  916. sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
  917. switch (psb_intel_sdvo->sdvo_reg) {
  918. case SDVOB:
  919. sdvox &= SDVOB_PRESERVE_MASK;
  920. break;
  921. case SDVOC:
  922. sdvox &= SDVOC_PRESERVE_MASK;
  923. break;
  924. }
  925. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  926. if (gma_crtc->pipe == 1)
  927. sdvox |= SDVO_PIPE_B_SELECT;
  928. if (psb_intel_sdvo->has_hdmi_audio)
  929. sdvox |= SDVO_AUDIO_ENABLE;
  930. /* FIXME: Check if this is needed for PSB
  931. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  932. */
  933. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
  934. sdvox |= SDVO_STALL_SELECT;
  935. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
  936. }
  937. static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  938. {
  939. struct drm_device *dev = encoder->dev;
  940. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  941. u32 temp;
  942. switch (mode) {
  943. case DRM_MODE_DPMS_ON:
  944. DRM_DEBUG("DPMS_ON");
  945. break;
  946. case DRM_MODE_DPMS_OFF:
  947. DRM_DEBUG("DPMS_OFF");
  948. break;
  949. default:
  950. DRM_DEBUG("DPMS: %d", mode);
  951. }
  952. if (mode != DRM_MODE_DPMS_ON) {
  953. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
  954. if (0)
  955. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  956. if (mode == DRM_MODE_DPMS_OFF) {
  957. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  958. if ((temp & SDVO_ENABLE) != 0) {
  959. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
  960. }
  961. }
  962. } else {
  963. bool input1, input2;
  964. int i;
  965. u8 status;
  966. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  967. if ((temp & SDVO_ENABLE) == 0)
  968. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
  969. for (i = 0; i < 2; i++)
  970. gma_wait_for_vblank(dev);
  971. status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
  972. /* Warn if the device reported failure to sync.
  973. * A lot of SDVO devices fail to notify of sync, but it's
  974. * a given it the status is a success, we succeeded.
  975. */
  976. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  977. DRM_DEBUG_KMS("First %s output reported failure to "
  978. "sync\n", SDVO_NAME(psb_intel_sdvo));
  979. }
  980. if (0)
  981. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  982. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
  983. }
  984. return;
  985. }
  986. static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
  987. struct drm_display_mode *mode)
  988. {
  989. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  990. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  991. return MODE_NO_DBLESCAN;
  992. if (psb_intel_sdvo->pixel_clock_min > mode->clock)
  993. return MODE_CLOCK_LOW;
  994. if (psb_intel_sdvo->pixel_clock_max < mode->clock)
  995. return MODE_CLOCK_HIGH;
  996. if (psb_intel_sdvo->is_lvds) {
  997. if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  998. return MODE_PANEL;
  999. if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1000. return MODE_PANEL;
  1001. }
  1002. return MODE_OK;
  1003. }
  1004. static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
  1005. {
  1006. BUILD_BUG_ON(sizeof(*caps) != 8);
  1007. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1008. SDVO_CMD_GET_DEVICE_CAPS,
  1009. caps, sizeof(*caps)))
  1010. return false;
  1011. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1012. " vendor_id: %d\n"
  1013. " device_id: %d\n"
  1014. " device_rev_id: %d\n"
  1015. " sdvo_version_major: %d\n"
  1016. " sdvo_version_minor: %d\n"
  1017. " sdvo_inputs_mask: %d\n"
  1018. " smooth_scaling: %d\n"
  1019. " sharp_scaling: %d\n"
  1020. " up_scaling: %d\n"
  1021. " down_scaling: %d\n"
  1022. " stall_support: %d\n"
  1023. " output_flags: %d\n",
  1024. caps->vendor_id,
  1025. caps->device_id,
  1026. caps->device_rev_id,
  1027. caps->sdvo_version_major,
  1028. caps->sdvo_version_minor,
  1029. caps->sdvo_inputs_mask,
  1030. caps->smooth_scaling,
  1031. caps->sharp_scaling,
  1032. caps->up_scaling,
  1033. caps->down_scaling,
  1034. caps->stall_support,
  1035. caps->output_flags);
  1036. return true;
  1037. }
  1038. /* No use! */
  1039. #if 0
  1040. struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1041. {
  1042. struct drm_connector *connector = NULL;
  1043. struct psb_intel_sdvo *iout = NULL;
  1044. struct psb_intel_sdvo *sdvo;
  1045. /* find the sdvo connector */
  1046. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1047. iout = to_psb_intel_sdvo(connector);
  1048. if (iout->type != INTEL_OUTPUT_SDVO)
  1049. continue;
  1050. sdvo = iout->dev_priv;
  1051. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1052. return connector;
  1053. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1054. return connector;
  1055. }
  1056. return NULL;
  1057. }
  1058. int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1059. {
  1060. u8 response[2];
  1061. u8 status;
  1062. struct psb_intel_sdvo *psb_intel_sdvo;
  1063. DRM_DEBUG_KMS("\n");
  1064. if (!connector)
  1065. return 0;
  1066. psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1067. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1068. &response, 2) && response[0];
  1069. }
  1070. void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1071. {
  1072. u8 response[2];
  1073. u8 status;
  1074. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1075. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1076. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1077. if (on) {
  1078. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1079. status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1080. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1081. } else {
  1082. response[0] = 0;
  1083. response[1] = 0;
  1084. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1085. }
  1086. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1087. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1088. }
  1089. #endif
  1090. static bool
  1091. psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
  1092. {
  1093. /* Is there more than one type of output? */
  1094. int caps = psb_intel_sdvo->caps.output_flags & 0xf;
  1095. return caps & -caps;
  1096. }
  1097. static struct edid *
  1098. psb_intel_sdvo_get_edid(struct drm_connector *connector)
  1099. {
  1100. struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1101. return drm_get_edid(connector, &sdvo->ddc);
  1102. }
  1103. /* Mac mini hack -- use the same DDC as the analog connector */
  1104. static struct edid *
  1105. psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1106. {
  1107. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1108. return drm_get_edid(connector,
  1109. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1110. }
  1111. static enum drm_connector_status
  1112. psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1113. {
  1114. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1115. enum drm_connector_status status;
  1116. struct edid *edid;
  1117. edid = psb_intel_sdvo_get_edid(connector);
  1118. if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
  1119. u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
  1120. /*
  1121. * Don't use the 1 as the argument of DDC bus switch to get
  1122. * the EDID. It is used for SDVO SPD ROM.
  1123. */
  1124. for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1125. psb_intel_sdvo->ddc_bus = ddc;
  1126. edid = psb_intel_sdvo_get_edid(connector);
  1127. if (edid)
  1128. break;
  1129. }
  1130. /*
  1131. * If we found the EDID on the other bus,
  1132. * assume that is the correct DDC bus.
  1133. */
  1134. if (edid == NULL)
  1135. psb_intel_sdvo->ddc_bus = saved_ddc;
  1136. }
  1137. /*
  1138. * When there is no edid and no monitor is connected with VGA
  1139. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1140. */
  1141. if (edid == NULL)
  1142. edid = psb_intel_sdvo_get_analog_edid(connector);
  1143. status = connector_status_unknown;
  1144. if (edid != NULL) {
  1145. /* DDC bus is shared, match EDID to connector type */
  1146. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1147. status = connector_status_connected;
  1148. if (psb_intel_sdvo->is_hdmi) {
  1149. psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1150. psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1151. }
  1152. } else
  1153. status = connector_status_disconnected;
  1154. kfree(edid);
  1155. }
  1156. if (status == connector_status_connected) {
  1157. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1158. if (psb_intel_sdvo_connector->force_audio)
  1159. psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
  1160. }
  1161. return status;
  1162. }
  1163. static enum drm_connector_status
  1164. psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
  1165. {
  1166. uint16_t response;
  1167. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1168. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1169. enum drm_connector_status ret;
  1170. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1171. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1172. return connector_status_unknown;
  1173. /* add 30ms delay when the output type might be TV */
  1174. if (psb_intel_sdvo->caps.output_flags &
  1175. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1176. mdelay(30);
  1177. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
  1178. return connector_status_unknown;
  1179. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1180. response & 0xff, response >> 8,
  1181. psb_intel_sdvo_connector->output_flag);
  1182. if (response == 0)
  1183. return connector_status_disconnected;
  1184. psb_intel_sdvo->attached_output = response;
  1185. psb_intel_sdvo->has_hdmi_monitor = false;
  1186. psb_intel_sdvo->has_hdmi_audio = false;
  1187. if ((psb_intel_sdvo_connector->output_flag & response) == 0)
  1188. ret = connector_status_disconnected;
  1189. else if (IS_TMDS(psb_intel_sdvo_connector))
  1190. ret = psb_intel_sdvo_hdmi_sink_detect(connector);
  1191. else {
  1192. struct edid *edid;
  1193. /* if we have an edid check it matches the connection */
  1194. edid = psb_intel_sdvo_get_edid(connector);
  1195. if (edid == NULL)
  1196. edid = psb_intel_sdvo_get_analog_edid(connector);
  1197. if (edid != NULL) {
  1198. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1199. ret = connector_status_disconnected;
  1200. else
  1201. ret = connector_status_connected;
  1202. kfree(edid);
  1203. } else
  1204. ret = connector_status_connected;
  1205. }
  1206. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1207. if (ret == connector_status_connected) {
  1208. psb_intel_sdvo->is_tv = false;
  1209. psb_intel_sdvo->is_lvds = false;
  1210. psb_intel_sdvo->base.needs_tv_clock = false;
  1211. if (response & SDVO_TV_MASK) {
  1212. psb_intel_sdvo->is_tv = true;
  1213. psb_intel_sdvo->base.needs_tv_clock = true;
  1214. }
  1215. if (response & SDVO_LVDS_MASK)
  1216. psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1217. }
  1218. return ret;
  1219. }
  1220. static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1221. {
  1222. struct edid *edid;
  1223. /* set the bus switch and get the modes */
  1224. edid = psb_intel_sdvo_get_edid(connector);
  1225. /*
  1226. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1227. * link between analog and digital outputs. So, if the regular SDVO
  1228. * DDC fails, check to see if the analog output is disconnected, in
  1229. * which case we'll look there for the digital DDC data.
  1230. */
  1231. if (edid == NULL)
  1232. edid = psb_intel_sdvo_get_analog_edid(connector);
  1233. if (edid != NULL) {
  1234. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1235. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1236. bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
  1237. if (connector_is_digital == monitor_is_digital) {
  1238. drm_mode_connector_update_edid_property(connector, edid);
  1239. drm_add_edid_modes(connector, edid);
  1240. }
  1241. kfree(edid);
  1242. }
  1243. }
  1244. /*
  1245. * Set of SDVO TV modes.
  1246. * Note! This is in reply order (see loop in get_tv_modes).
  1247. * XXX: all 60Hz refresh?
  1248. */
  1249. static const struct drm_display_mode sdvo_tv_modes[] = {
  1250. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1251. 416, 0, 200, 201, 232, 233, 0,
  1252. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1253. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1254. 416, 0, 240, 241, 272, 273, 0,
  1255. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1256. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1257. 496, 0, 300, 301, 332, 333, 0,
  1258. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1259. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1260. 736, 0, 350, 351, 382, 383, 0,
  1261. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1262. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1263. 736, 0, 400, 401, 432, 433, 0,
  1264. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1265. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1266. 736, 0, 480, 481, 512, 513, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1268. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1269. 800, 0, 480, 481, 512, 513, 0,
  1270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1271. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1272. 800, 0, 576, 577, 608, 609, 0,
  1273. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1274. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1275. 816, 0, 350, 351, 382, 383, 0,
  1276. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1277. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1278. 816, 0, 400, 401, 432, 433, 0,
  1279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1280. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1281. 816, 0, 480, 481, 512, 513, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1283. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1284. 816, 0, 540, 541, 572, 573, 0,
  1285. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1286. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1287. 816, 0, 576, 577, 608, 609, 0,
  1288. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1289. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1290. 864, 0, 576, 577, 608, 609, 0,
  1291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1292. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1293. 896, 0, 600, 601, 632, 633, 0,
  1294. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1295. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1296. 928, 0, 624, 625, 656, 657, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1298. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1299. 1016, 0, 766, 767, 798, 799, 0,
  1300. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1301. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1302. 1120, 0, 768, 769, 800, 801, 0,
  1303. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1304. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1305. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1306. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1307. };
  1308. static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1309. {
  1310. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1311. struct psb_intel_sdvo_sdtv_resolution_request tv_res;
  1312. uint32_t reply = 0, format_map = 0;
  1313. int i;
  1314. /* Read the list of supported input resolutions for the selected TV
  1315. * format.
  1316. */
  1317. format_map = 1 << psb_intel_sdvo->tv_format_index;
  1318. memcpy(&tv_res, &format_map,
  1319. min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
  1320. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
  1321. return;
  1322. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1323. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1324. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1325. &tv_res, sizeof(tv_res)))
  1326. return;
  1327. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
  1328. return;
  1329. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1330. if (reply & (1 << i)) {
  1331. struct drm_display_mode *nmode;
  1332. nmode = drm_mode_duplicate(connector->dev,
  1333. &sdvo_tv_modes[i]);
  1334. if (nmode)
  1335. drm_mode_probed_add(connector, nmode);
  1336. }
  1337. }
  1338. static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1339. {
  1340. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1341. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1342. struct drm_display_mode *newmode;
  1343. /*
  1344. * Attempt to get the mode list from DDC.
  1345. * Assume that the preferred modes are
  1346. * arranged in priority order.
  1347. */
  1348. psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
  1349. if (list_empty(&connector->probed_modes) == false)
  1350. goto end;
  1351. /* Fetch modes from VBT */
  1352. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1353. newmode = drm_mode_duplicate(connector->dev,
  1354. dev_priv->sdvo_lvds_vbt_mode);
  1355. if (newmode != NULL) {
  1356. /* Guarantee the mode is preferred */
  1357. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1358. DRM_MODE_TYPE_DRIVER);
  1359. drm_mode_probed_add(connector, newmode);
  1360. }
  1361. }
  1362. end:
  1363. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1364. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1365. psb_intel_sdvo->sdvo_lvds_fixed_mode =
  1366. drm_mode_duplicate(connector->dev, newmode);
  1367. drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
  1368. 0);
  1369. psb_intel_sdvo->is_lvds = true;
  1370. break;
  1371. }
  1372. }
  1373. }
  1374. static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
  1375. {
  1376. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1377. if (IS_TV(psb_intel_sdvo_connector))
  1378. psb_intel_sdvo_get_tv_modes(connector);
  1379. else if (IS_LVDS(psb_intel_sdvo_connector))
  1380. psb_intel_sdvo_get_lvds_modes(connector);
  1381. else
  1382. psb_intel_sdvo_get_ddc_modes(connector);
  1383. return !list_empty(&connector->probed_modes);
  1384. }
  1385. static void
  1386. psb_intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1387. {
  1388. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1389. struct drm_device *dev = connector->dev;
  1390. if (psb_intel_sdvo_connector->left)
  1391. drm_property_destroy(dev, psb_intel_sdvo_connector->left);
  1392. if (psb_intel_sdvo_connector->right)
  1393. drm_property_destroy(dev, psb_intel_sdvo_connector->right);
  1394. if (psb_intel_sdvo_connector->top)
  1395. drm_property_destroy(dev, psb_intel_sdvo_connector->top);
  1396. if (psb_intel_sdvo_connector->bottom)
  1397. drm_property_destroy(dev, psb_intel_sdvo_connector->bottom);
  1398. if (psb_intel_sdvo_connector->hpos)
  1399. drm_property_destroy(dev, psb_intel_sdvo_connector->hpos);
  1400. if (psb_intel_sdvo_connector->vpos)
  1401. drm_property_destroy(dev, psb_intel_sdvo_connector->vpos);
  1402. if (psb_intel_sdvo_connector->saturation)
  1403. drm_property_destroy(dev, psb_intel_sdvo_connector->saturation);
  1404. if (psb_intel_sdvo_connector->contrast)
  1405. drm_property_destroy(dev, psb_intel_sdvo_connector->contrast);
  1406. if (psb_intel_sdvo_connector->hue)
  1407. drm_property_destroy(dev, psb_intel_sdvo_connector->hue);
  1408. if (psb_intel_sdvo_connector->sharpness)
  1409. drm_property_destroy(dev, psb_intel_sdvo_connector->sharpness);
  1410. if (psb_intel_sdvo_connector->flicker_filter)
  1411. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter);
  1412. if (psb_intel_sdvo_connector->flicker_filter_2d)
  1413. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_2d);
  1414. if (psb_intel_sdvo_connector->flicker_filter_adaptive)
  1415. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_adaptive);
  1416. if (psb_intel_sdvo_connector->tv_luma_filter)
  1417. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_luma_filter);
  1418. if (psb_intel_sdvo_connector->tv_chroma_filter)
  1419. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_chroma_filter);
  1420. if (psb_intel_sdvo_connector->dot_crawl)
  1421. drm_property_destroy(dev, psb_intel_sdvo_connector->dot_crawl);
  1422. if (psb_intel_sdvo_connector->brightness)
  1423. drm_property_destroy(dev, psb_intel_sdvo_connector->brightness);
  1424. }
  1425. static void psb_intel_sdvo_destroy(struct drm_connector *connector)
  1426. {
  1427. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1428. if (psb_intel_sdvo_connector->tv_format)
  1429. drm_property_destroy(connector->dev,
  1430. psb_intel_sdvo_connector->tv_format);
  1431. psb_intel_sdvo_destroy_enhance_property(connector);
  1432. drm_sysfs_connector_remove(connector);
  1433. drm_connector_cleanup(connector);
  1434. kfree(connector);
  1435. }
  1436. static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1437. {
  1438. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1439. struct edid *edid;
  1440. bool has_audio = false;
  1441. if (!psb_intel_sdvo->is_hdmi)
  1442. return false;
  1443. edid = psb_intel_sdvo_get_edid(connector);
  1444. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1445. has_audio = drm_detect_monitor_audio(edid);
  1446. return has_audio;
  1447. }
  1448. static int
  1449. psb_intel_sdvo_set_property(struct drm_connector *connector,
  1450. struct drm_property *property,
  1451. uint64_t val)
  1452. {
  1453. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1454. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1455. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1456. uint16_t temp_value;
  1457. uint8_t cmd;
  1458. int ret;
  1459. ret = drm_object_property_set_value(&connector->base, property, val);
  1460. if (ret)
  1461. return ret;
  1462. if (property == dev_priv->force_audio_property) {
  1463. int i = val;
  1464. bool has_audio;
  1465. if (i == psb_intel_sdvo_connector->force_audio)
  1466. return 0;
  1467. psb_intel_sdvo_connector->force_audio = i;
  1468. if (i == 0)
  1469. has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
  1470. else
  1471. has_audio = i > 0;
  1472. if (has_audio == psb_intel_sdvo->has_hdmi_audio)
  1473. return 0;
  1474. psb_intel_sdvo->has_hdmi_audio = has_audio;
  1475. goto done;
  1476. }
  1477. if (property == dev_priv->broadcast_rgb_property) {
  1478. if (val == !!psb_intel_sdvo->color_range)
  1479. return 0;
  1480. psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1481. goto done;
  1482. }
  1483. #define CHECK_PROPERTY(name, NAME) \
  1484. if (psb_intel_sdvo_connector->name == property) { \
  1485. if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1486. if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1487. cmd = SDVO_CMD_SET_##NAME; \
  1488. psb_intel_sdvo_connector->cur_##name = temp_value; \
  1489. goto set_value; \
  1490. }
  1491. if (property == psb_intel_sdvo_connector->tv_format) {
  1492. if (val >= TV_FORMAT_NUM)
  1493. return -EINVAL;
  1494. if (psb_intel_sdvo->tv_format_index ==
  1495. psb_intel_sdvo_connector->tv_format_supported[val])
  1496. return 0;
  1497. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
  1498. goto done;
  1499. } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
  1500. temp_value = val;
  1501. if (psb_intel_sdvo_connector->left == property) {
  1502. drm_object_property_set_value(&connector->base,
  1503. psb_intel_sdvo_connector->right, val);
  1504. if (psb_intel_sdvo_connector->left_margin == temp_value)
  1505. return 0;
  1506. psb_intel_sdvo_connector->left_margin = temp_value;
  1507. psb_intel_sdvo_connector->right_margin = temp_value;
  1508. temp_value = psb_intel_sdvo_connector->max_hscan -
  1509. psb_intel_sdvo_connector->left_margin;
  1510. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1511. goto set_value;
  1512. } else if (psb_intel_sdvo_connector->right == property) {
  1513. drm_object_property_set_value(&connector->base,
  1514. psb_intel_sdvo_connector->left, val);
  1515. if (psb_intel_sdvo_connector->right_margin == temp_value)
  1516. return 0;
  1517. psb_intel_sdvo_connector->left_margin = temp_value;
  1518. psb_intel_sdvo_connector->right_margin = temp_value;
  1519. temp_value = psb_intel_sdvo_connector->max_hscan -
  1520. psb_intel_sdvo_connector->left_margin;
  1521. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1522. goto set_value;
  1523. } else if (psb_intel_sdvo_connector->top == property) {
  1524. drm_object_property_set_value(&connector->base,
  1525. psb_intel_sdvo_connector->bottom, val);
  1526. if (psb_intel_sdvo_connector->top_margin == temp_value)
  1527. return 0;
  1528. psb_intel_sdvo_connector->top_margin = temp_value;
  1529. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1530. temp_value = psb_intel_sdvo_connector->max_vscan -
  1531. psb_intel_sdvo_connector->top_margin;
  1532. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1533. goto set_value;
  1534. } else if (psb_intel_sdvo_connector->bottom == property) {
  1535. drm_object_property_set_value(&connector->base,
  1536. psb_intel_sdvo_connector->top, val);
  1537. if (psb_intel_sdvo_connector->bottom_margin == temp_value)
  1538. return 0;
  1539. psb_intel_sdvo_connector->top_margin = temp_value;
  1540. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1541. temp_value = psb_intel_sdvo_connector->max_vscan -
  1542. psb_intel_sdvo_connector->top_margin;
  1543. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1544. goto set_value;
  1545. }
  1546. CHECK_PROPERTY(hpos, HPOS)
  1547. CHECK_PROPERTY(vpos, VPOS)
  1548. CHECK_PROPERTY(saturation, SATURATION)
  1549. CHECK_PROPERTY(contrast, CONTRAST)
  1550. CHECK_PROPERTY(hue, HUE)
  1551. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1552. CHECK_PROPERTY(sharpness, SHARPNESS)
  1553. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1554. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1555. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1556. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1557. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1558. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1559. }
  1560. return -EINVAL; /* unknown property */
  1561. set_value:
  1562. if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
  1563. return -EIO;
  1564. done:
  1565. if (psb_intel_sdvo->base.base.crtc) {
  1566. struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
  1567. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1568. crtc->y, crtc->fb);
  1569. }
  1570. return 0;
  1571. #undef CHECK_PROPERTY
  1572. }
  1573. static void psb_intel_sdvo_save(struct drm_connector *connector)
  1574. {
  1575. struct drm_device *dev = connector->dev;
  1576. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  1577. struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base);
  1578. sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);
  1579. }
  1580. static void psb_intel_sdvo_restore(struct drm_connector *connector)
  1581. {
  1582. struct drm_device *dev = connector->dev;
  1583. struct drm_encoder *encoder = &gma_attached_encoder(connector)->base;
  1584. struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder);
  1585. struct drm_crtc *crtc = encoder->crtc;
  1586. REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO);
  1587. /* Force a full mode set on the crtc. We're supposed to have the
  1588. mode_config lock already. */
  1589. if (connector->status == connector_status_connected)
  1590. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  1591. NULL);
  1592. }
  1593. static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
  1594. .dpms = psb_intel_sdvo_dpms,
  1595. .mode_fixup = psb_intel_sdvo_mode_fixup,
  1596. .prepare = gma_encoder_prepare,
  1597. .mode_set = psb_intel_sdvo_mode_set,
  1598. .commit = gma_encoder_commit,
  1599. };
  1600. static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
  1601. .dpms = drm_helper_connector_dpms,
  1602. .save = psb_intel_sdvo_save,
  1603. .restore = psb_intel_sdvo_restore,
  1604. .detect = psb_intel_sdvo_detect,
  1605. .fill_modes = drm_helper_probe_single_connector_modes,
  1606. .set_property = psb_intel_sdvo_set_property,
  1607. .destroy = psb_intel_sdvo_destroy,
  1608. };
  1609. static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
  1610. .get_modes = psb_intel_sdvo_get_modes,
  1611. .mode_valid = psb_intel_sdvo_mode_valid,
  1612. .best_encoder = gma_best_encoder,
  1613. };
  1614. static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1615. {
  1616. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  1617. if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1618. drm_mode_destroy(encoder->dev,
  1619. psb_intel_sdvo->sdvo_lvds_fixed_mode);
  1620. i2c_del_adapter(&psb_intel_sdvo->ddc);
  1621. gma_encoder_destroy(encoder);
  1622. }
  1623. static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
  1624. .destroy = psb_intel_sdvo_enc_destroy,
  1625. };
  1626. static void
  1627. psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
  1628. {
  1629. /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
  1630. * We need to figure out if this is true for all available poulsbo
  1631. * hardware, or if we need to fiddle with the guessing code above.
  1632. * The problem might go away if we can parse sdvo mappings from bios */
  1633. sdvo->ddc_bus = 2;
  1634. #if 0
  1635. uint16_t mask = 0;
  1636. unsigned int num_bits;
  1637. /* Make a mask of outputs less than or equal to our own priority in the
  1638. * list.
  1639. */
  1640. switch (sdvo->controlled_output) {
  1641. case SDVO_OUTPUT_LVDS1:
  1642. mask |= SDVO_OUTPUT_LVDS1;
  1643. case SDVO_OUTPUT_LVDS0:
  1644. mask |= SDVO_OUTPUT_LVDS0;
  1645. case SDVO_OUTPUT_TMDS1:
  1646. mask |= SDVO_OUTPUT_TMDS1;
  1647. case SDVO_OUTPUT_TMDS0:
  1648. mask |= SDVO_OUTPUT_TMDS0;
  1649. case SDVO_OUTPUT_RGB1:
  1650. mask |= SDVO_OUTPUT_RGB1;
  1651. case SDVO_OUTPUT_RGB0:
  1652. mask |= SDVO_OUTPUT_RGB0;
  1653. break;
  1654. }
  1655. /* Count bits to find what number we are in the priority list. */
  1656. mask &= sdvo->caps.output_flags;
  1657. num_bits = hweight16(mask);
  1658. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1659. if (num_bits > 3)
  1660. num_bits = 3;
  1661. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1662. sdvo->ddc_bus = 1 << num_bits;
  1663. #endif
  1664. }
  1665. /**
  1666. * Choose the appropriate DDC bus for control bus switch command for this
  1667. * SDVO output based on the controlled output.
  1668. *
  1669. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1670. * outputs, then LVDS outputs.
  1671. */
  1672. static void
  1673. psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
  1674. struct psb_intel_sdvo *sdvo, u32 reg)
  1675. {
  1676. struct sdvo_device_mapping *mapping;
  1677. if (IS_SDVOB(reg))
  1678. mapping = &(dev_priv->sdvo_mappings[0]);
  1679. else
  1680. mapping = &(dev_priv->sdvo_mappings[1]);
  1681. if (mapping->initialized)
  1682. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1683. else
  1684. psb_intel_sdvo_guess_ddc_bus(sdvo);
  1685. }
  1686. static void
  1687. psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
  1688. struct psb_intel_sdvo *sdvo, u32 reg)
  1689. {
  1690. struct sdvo_device_mapping *mapping;
  1691. u8 pin, speed;
  1692. if (IS_SDVOB(reg))
  1693. mapping = &dev_priv->sdvo_mappings[0];
  1694. else
  1695. mapping = &dev_priv->sdvo_mappings[1];
  1696. pin = GMBUS_PORT_DPB;
  1697. speed = GMBUS_RATE_1MHZ >> 8;
  1698. if (mapping->initialized) {
  1699. pin = mapping->i2c_pin;
  1700. speed = mapping->i2c_speed;
  1701. }
  1702. if (pin < GMBUS_NUM_PORTS) {
  1703. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1704. gma_intel_gmbus_set_speed(sdvo->i2c, speed);
  1705. gma_intel_gmbus_force_bit(sdvo->i2c, true);
  1706. } else
  1707. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1708. }
  1709. static bool
  1710. psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1711. {
  1712. return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
  1713. }
  1714. static u8
  1715. psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1716. {
  1717. struct drm_psb_private *dev_priv = dev->dev_private;
  1718. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1719. if (IS_SDVOB(sdvo_reg)) {
  1720. my_mapping = &dev_priv->sdvo_mappings[0];
  1721. other_mapping = &dev_priv->sdvo_mappings[1];
  1722. } else {
  1723. my_mapping = &dev_priv->sdvo_mappings[1];
  1724. other_mapping = &dev_priv->sdvo_mappings[0];
  1725. }
  1726. /* If the BIOS described our SDVO device, take advantage of it. */
  1727. if (my_mapping->slave_addr)
  1728. return my_mapping->slave_addr;
  1729. /* If the BIOS only described a different SDVO device, use the
  1730. * address that it isn't using.
  1731. */
  1732. if (other_mapping->slave_addr) {
  1733. if (other_mapping->slave_addr == 0x70)
  1734. return 0x72;
  1735. else
  1736. return 0x70;
  1737. }
  1738. /* No SDVO device info is found for another DVO port,
  1739. * so use mapping assumption we had before BIOS parsing.
  1740. */
  1741. if (IS_SDVOB(sdvo_reg))
  1742. return 0x70;
  1743. else
  1744. return 0x72;
  1745. }
  1746. static void
  1747. psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
  1748. struct psb_intel_sdvo *encoder)
  1749. {
  1750. drm_connector_init(encoder->base.base.dev,
  1751. &connector->base.base,
  1752. &psb_intel_sdvo_connector_funcs,
  1753. connector->base.base.connector_type);
  1754. drm_connector_helper_add(&connector->base.base,
  1755. &psb_intel_sdvo_connector_helper_funcs);
  1756. connector->base.base.interlace_allowed = 0;
  1757. connector->base.base.doublescan_allowed = 0;
  1758. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1759. gma_connector_attach_encoder(&connector->base, &encoder->base);
  1760. drm_sysfs_connector_add(&connector->base.base);
  1761. }
  1762. static void
  1763. psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
  1764. {
  1765. /* FIXME: We don't support HDMI at the moment
  1766. struct drm_device *dev = connector->base.base.dev;
  1767. intel_attach_force_audio_property(&connector->base.base);
  1768. intel_attach_broadcast_rgb_property(&connector->base.base);
  1769. */
  1770. }
  1771. static bool
  1772. psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1773. {
  1774. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1775. struct drm_connector *connector;
  1776. struct gma_connector *intel_connector;
  1777. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1778. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1779. if (!psb_intel_sdvo_connector)
  1780. return false;
  1781. if (device == 0) {
  1782. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1783. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1784. } else if (device == 1) {
  1785. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1786. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1787. }
  1788. intel_connector = &psb_intel_sdvo_connector->base;
  1789. connector = &intel_connector->base;
  1790. // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1791. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1792. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1793. if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
  1794. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1795. psb_intel_sdvo->is_hdmi = true;
  1796. }
  1797. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1798. (1 << INTEL_ANALOG_CLONE_BIT));
  1799. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1800. if (psb_intel_sdvo->is_hdmi)
  1801. psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
  1802. return true;
  1803. }
  1804. static bool
  1805. psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
  1806. {
  1807. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1808. struct drm_connector *connector;
  1809. struct gma_connector *intel_connector;
  1810. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1811. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1812. if (!psb_intel_sdvo_connector)
  1813. return false;
  1814. intel_connector = &psb_intel_sdvo_connector->base;
  1815. connector = &intel_connector->base;
  1816. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1817. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1818. psb_intel_sdvo->controlled_output |= type;
  1819. psb_intel_sdvo_connector->output_flag = type;
  1820. psb_intel_sdvo->is_tv = true;
  1821. psb_intel_sdvo->base.needs_tv_clock = true;
  1822. psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1823. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1824. if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
  1825. goto err;
  1826. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1827. goto err;
  1828. return true;
  1829. err:
  1830. psb_intel_sdvo_destroy(connector);
  1831. return false;
  1832. }
  1833. static bool
  1834. psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1835. {
  1836. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1837. struct drm_connector *connector;
  1838. struct gma_connector *intel_connector;
  1839. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1840. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1841. if (!psb_intel_sdvo_connector)
  1842. return false;
  1843. intel_connector = &psb_intel_sdvo_connector->base;
  1844. connector = &intel_connector->base;
  1845. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1846. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1847. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1848. if (device == 0) {
  1849. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1850. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1851. } else if (device == 1) {
  1852. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1853. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1854. }
  1855. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1856. (1 << INTEL_ANALOG_CLONE_BIT));
  1857. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
  1858. psb_intel_sdvo);
  1859. return true;
  1860. }
  1861. static bool
  1862. psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1863. {
  1864. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1865. struct drm_connector *connector;
  1866. struct gma_connector *intel_connector;
  1867. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1868. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1869. if (!psb_intel_sdvo_connector)
  1870. return false;
  1871. intel_connector = &psb_intel_sdvo_connector->base;
  1872. connector = &intel_connector->base;
  1873. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1874. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1875. if (device == 0) {
  1876. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1877. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1878. } else if (device == 1) {
  1879. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1880. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1881. }
  1882. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1883. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1884. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1885. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1886. goto err;
  1887. return true;
  1888. err:
  1889. psb_intel_sdvo_destroy(connector);
  1890. return false;
  1891. }
  1892. static bool
  1893. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
  1894. {
  1895. psb_intel_sdvo->is_tv = false;
  1896. psb_intel_sdvo->base.needs_tv_clock = false;
  1897. psb_intel_sdvo->is_lvds = false;
  1898. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1899. if (flags & SDVO_OUTPUT_TMDS0)
  1900. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
  1901. return false;
  1902. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1903. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
  1904. return false;
  1905. /* TV has no XXX1 function block */
  1906. if (flags & SDVO_OUTPUT_SVID0)
  1907. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
  1908. return false;
  1909. if (flags & SDVO_OUTPUT_CVBS0)
  1910. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
  1911. return false;
  1912. if (flags & SDVO_OUTPUT_RGB0)
  1913. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
  1914. return false;
  1915. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1916. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
  1917. return false;
  1918. if (flags & SDVO_OUTPUT_LVDS0)
  1919. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
  1920. return false;
  1921. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1922. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
  1923. return false;
  1924. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1925. unsigned char bytes[2];
  1926. psb_intel_sdvo->controlled_output = 0;
  1927. memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
  1928. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1929. SDVO_NAME(psb_intel_sdvo),
  1930. bytes[0], bytes[1]);
  1931. return false;
  1932. }
  1933. psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1934. return true;
  1935. }
  1936. static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  1937. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1938. int type)
  1939. {
  1940. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1941. struct psb_intel_sdvo_tv_format format;
  1942. uint32_t format_map, i;
  1943. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
  1944. return false;
  1945. BUILD_BUG_ON(sizeof(format) != 6);
  1946. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1947. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1948. &format, sizeof(format)))
  1949. return false;
  1950. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1951. if (format_map == 0)
  1952. return false;
  1953. psb_intel_sdvo_connector->format_supported_num = 0;
  1954. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1955. if (format_map & (1 << i))
  1956. psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
  1957. psb_intel_sdvo_connector->tv_format =
  1958. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1959. "mode", psb_intel_sdvo_connector->format_supported_num);
  1960. if (!psb_intel_sdvo_connector->tv_format)
  1961. return false;
  1962. for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
  1963. drm_property_add_enum(
  1964. psb_intel_sdvo_connector->tv_format, i,
  1965. i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
  1966. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
  1967. drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base,
  1968. psb_intel_sdvo_connector->tv_format, 0);
  1969. return true;
  1970. }
  1971. #define ENHANCEMENT(name, NAME) do { \
  1972. if (enhancements.name) { \
  1973. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1974. !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1975. return false; \
  1976. psb_intel_sdvo_connector->max_##name = data_value[0]; \
  1977. psb_intel_sdvo_connector->cur_##name = response; \
  1978. psb_intel_sdvo_connector->name = \
  1979. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1980. if (!psb_intel_sdvo_connector->name) return false; \
  1981. drm_object_attach_property(&connector->base, \
  1982. psb_intel_sdvo_connector->name, \
  1983. psb_intel_sdvo_connector->cur_##name); \
  1984. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1985. data_value[0], data_value[1], response); \
  1986. } \
  1987. } while(0)
  1988. static bool
  1989. psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
  1990. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1991. struct psb_intel_sdvo_enhancements_reply enhancements)
  1992. {
  1993. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1994. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  1995. uint16_t response, data_value[2];
  1996. /* when horizontal overscan is supported, Add the left/right property */
  1997. if (enhancements.overscan_h) {
  1998. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1999. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2000. &data_value, 4))
  2001. return false;
  2002. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2003. SDVO_CMD_GET_OVERSCAN_H,
  2004. &response, 2))
  2005. return false;
  2006. psb_intel_sdvo_connector->max_hscan = data_value[0];
  2007. psb_intel_sdvo_connector->left_margin = data_value[0] - response;
  2008. psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
  2009. psb_intel_sdvo_connector->left =
  2010. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2011. if (!psb_intel_sdvo_connector->left)
  2012. return false;
  2013. drm_object_attach_property(&connector->base,
  2014. psb_intel_sdvo_connector->left,
  2015. psb_intel_sdvo_connector->left_margin);
  2016. psb_intel_sdvo_connector->right =
  2017. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2018. if (!psb_intel_sdvo_connector->right)
  2019. return false;
  2020. drm_object_attach_property(&connector->base,
  2021. psb_intel_sdvo_connector->right,
  2022. psb_intel_sdvo_connector->right_margin);
  2023. DRM_DEBUG_KMS("h_overscan: max %d, "
  2024. "default %d, current %d\n",
  2025. data_value[0], data_value[1], response);
  2026. }
  2027. if (enhancements.overscan_v) {
  2028. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2029. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2030. &data_value, 4))
  2031. return false;
  2032. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2033. SDVO_CMD_GET_OVERSCAN_V,
  2034. &response, 2))
  2035. return false;
  2036. psb_intel_sdvo_connector->max_vscan = data_value[0];
  2037. psb_intel_sdvo_connector->top_margin = data_value[0] - response;
  2038. psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
  2039. psb_intel_sdvo_connector->top =
  2040. drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
  2041. if (!psb_intel_sdvo_connector->top)
  2042. return false;
  2043. drm_object_attach_property(&connector->base,
  2044. psb_intel_sdvo_connector->top,
  2045. psb_intel_sdvo_connector->top_margin);
  2046. psb_intel_sdvo_connector->bottom =
  2047. drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
  2048. if (!psb_intel_sdvo_connector->bottom)
  2049. return false;
  2050. drm_object_attach_property(&connector->base,
  2051. psb_intel_sdvo_connector->bottom,
  2052. psb_intel_sdvo_connector->bottom_margin);
  2053. DRM_DEBUG_KMS("v_overscan: max %d, "
  2054. "default %d, current %d\n",
  2055. data_value[0], data_value[1], response);
  2056. }
  2057. ENHANCEMENT(hpos, HPOS);
  2058. ENHANCEMENT(vpos, VPOS);
  2059. ENHANCEMENT(saturation, SATURATION);
  2060. ENHANCEMENT(contrast, CONTRAST);
  2061. ENHANCEMENT(hue, HUE);
  2062. ENHANCEMENT(sharpness, SHARPNESS);
  2063. ENHANCEMENT(brightness, BRIGHTNESS);
  2064. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2065. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2066. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2067. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2068. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2069. if (enhancements.dot_crawl) {
  2070. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2071. return false;
  2072. psb_intel_sdvo_connector->max_dot_crawl = 1;
  2073. psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2074. psb_intel_sdvo_connector->dot_crawl =
  2075. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2076. if (!psb_intel_sdvo_connector->dot_crawl)
  2077. return false;
  2078. drm_object_attach_property(&connector->base,
  2079. psb_intel_sdvo_connector->dot_crawl,
  2080. psb_intel_sdvo_connector->cur_dot_crawl);
  2081. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2082. }
  2083. return true;
  2084. }
  2085. static bool
  2086. psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
  2087. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  2088. struct psb_intel_sdvo_enhancements_reply enhancements)
  2089. {
  2090. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  2091. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  2092. uint16_t response, data_value[2];
  2093. ENHANCEMENT(brightness, BRIGHTNESS);
  2094. return true;
  2095. }
  2096. #undef ENHANCEMENT
  2097. static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  2098. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
  2099. {
  2100. union {
  2101. struct psb_intel_sdvo_enhancements_reply reply;
  2102. uint16_t response;
  2103. } enhancements;
  2104. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2105. enhancements.response = 0;
  2106. psb_intel_sdvo_get_value(psb_intel_sdvo,
  2107. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2108. &enhancements, sizeof(enhancements));
  2109. if (enhancements.response == 0) {
  2110. DRM_DEBUG_KMS("No enhancement is supported\n");
  2111. return true;
  2112. }
  2113. if (IS_TV(psb_intel_sdvo_connector))
  2114. return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2115. else if(IS_LVDS(psb_intel_sdvo_connector))
  2116. return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2117. else
  2118. return true;
  2119. }
  2120. static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2121. struct i2c_msg *msgs,
  2122. int num)
  2123. {
  2124. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2125. if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2126. return -EIO;
  2127. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2128. }
  2129. static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2130. {
  2131. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2132. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2133. }
  2134. static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
  2135. .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
  2136. .functionality = psb_intel_sdvo_ddc_proxy_func
  2137. };
  2138. static bool
  2139. psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
  2140. struct drm_device *dev)
  2141. {
  2142. sdvo->ddc.owner = THIS_MODULE;
  2143. sdvo->ddc.class = I2C_CLASS_DDC;
  2144. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2145. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2146. sdvo->ddc.algo_data = sdvo;
  2147. sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
  2148. return i2c_add_adapter(&sdvo->ddc) == 0;
  2149. }
  2150. bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2151. {
  2152. struct drm_psb_private *dev_priv = dev->dev_private;
  2153. struct gma_encoder *gma_encoder;
  2154. struct psb_intel_sdvo *psb_intel_sdvo;
  2155. int i;
  2156. psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
  2157. if (!psb_intel_sdvo)
  2158. return false;
  2159. psb_intel_sdvo->sdvo_reg = sdvo_reg;
  2160. psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2161. psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2162. if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
  2163. kfree(psb_intel_sdvo);
  2164. return false;
  2165. }
  2166. /* encoder type will be decided later */
  2167. gma_encoder = &psb_intel_sdvo->base;
  2168. gma_encoder->type = INTEL_OUTPUT_SDVO;
  2169. drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
  2170. /* Read the regs to test if we can talk to the device */
  2171. for (i = 0; i < 0x40; i++) {
  2172. u8 byte;
  2173. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
  2174. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2175. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2176. goto err;
  2177. }
  2178. }
  2179. if (IS_SDVOB(sdvo_reg))
  2180. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2181. else
  2182. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2183. drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs);
  2184. /* In default case sdvo lvds is false */
  2185. if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
  2186. goto err;
  2187. if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
  2188. psb_intel_sdvo->caps.output_flags) != true) {
  2189. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2190. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2191. goto err;
  2192. }
  2193. psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2194. /* Set the input timing to the screen. Assume always input 0. */
  2195. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  2196. goto err;
  2197. if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
  2198. &psb_intel_sdvo->pixel_clock_min,
  2199. &psb_intel_sdvo->pixel_clock_max))
  2200. goto err;
  2201. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2202. "clock range %dMHz - %dMHz, "
  2203. "input 1: %c, input 2: %c, "
  2204. "output 1: %c, output 2: %c\n",
  2205. SDVO_NAME(psb_intel_sdvo),
  2206. psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
  2207. psb_intel_sdvo->caps.device_rev_id,
  2208. psb_intel_sdvo->pixel_clock_min / 1000,
  2209. psb_intel_sdvo->pixel_clock_max / 1000,
  2210. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2211. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2212. /* check currently supported outputs */
  2213. psb_intel_sdvo->caps.output_flags &
  2214. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2215. psb_intel_sdvo->caps.output_flags &
  2216. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2217. return true;
  2218. err:
  2219. drm_encoder_cleanup(&gma_encoder->base);
  2220. i2c_del_adapter(&psb_intel_sdvo->ddc);
  2221. kfree(psb_intel_sdvo);
  2222. return false;
  2223. }