psb_device.c 10.0 KB

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  1. /**************************************************************************
  2. * Copyright (c) 2011, Intel Corporation.
  3. * All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. **************************************************************************/
  19. #include <linux/backlight.h>
  20. #include <drm/drmP.h>
  21. #include <drm/drm.h>
  22. #include <drm/gma_drm.h>
  23. #include "psb_drv.h"
  24. #include "psb_reg.h"
  25. #include "psb_intel_reg.h"
  26. #include "intel_bios.h"
  27. #include "psb_device.h"
  28. static int psb_output_init(struct drm_device *dev)
  29. {
  30. struct drm_psb_private *dev_priv = dev->dev_private;
  31. psb_intel_lvds_init(dev, &dev_priv->mode_dev);
  32. psb_intel_sdvo_init(dev, SDVOB);
  33. return 0;
  34. }
  35. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  36. /*
  37. * Poulsbo Backlight Interfaces
  38. */
  39. #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
  40. #define BLC_PWM_FREQ_CALC_CONSTANT 32
  41. #define MHz 1000000
  42. #define PSB_BLC_PWM_PRECISION_FACTOR 10
  43. #define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
  44. #define PSB_BLC_MIN_PWM_REG_FREQ 0x2
  45. #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
  46. #define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
  47. static int psb_brightness;
  48. static struct backlight_device *psb_backlight_device;
  49. static int psb_get_brightness(struct backlight_device *bd)
  50. {
  51. /* return locally cached var instead of HW read (due to DPST etc.) */
  52. /* FIXME: ideally return actual value in case firmware fiddled with
  53. it */
  54. return psb_brightness;
  55. }
  56. static int psb_backlight_setup(struct drm_device *dev)
  57. {
  58. struct drm_psb_private *dev_priv = dev->dev_private;
  59. unsigned long core_clock;
  60. /* u32 bl_max_freq; */
  61. /* unsigned long value; */
  62. u16 bl_max_freq;
  63. uint32_t value;
  64. uint32_t blc_pwm_precision_factor;
  65. /* get bl_max_freq and pol from dev_priv*/
  66. if (!dev_priv->lvds_bl) {
  67. dev_err(dev->dev, "Has no valid LVDS backlight info\n");
  68. return -ENOENT;
  69. }
  70. bl_max_freq = dev_priv->lvds_bl->freq;
  71. blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
  72. core_clock = dev_priv->core_freq;
  73. value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
  74. value *= blc_pwm_precision_factor;
  75. value /= bl_max_freq;
  76. value /= blc_pwm_precision_factor;
  77. if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
  78. value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
  79. return -ERANGE;
  80. else {
  81. value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
  82. REG_WRITE(BLC_PWM_CTL,
  83. (value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
  84. }
  85. return 0;
  86. }
  87. static int psb_set_brightness(struct backlight_device *bd)
  88. {
  89. struct drm_device *dev = bl_get_data(psb_backlight_device);
  90. int level = bd->props.brightness;
  91. /* Percentage 1-100% being valid */
  92. if (level < 1)
  93. level = 1;
  94. psb_intel_lvds_set_brightness(dev, level);
  95. psb_brightness = level;
  96. return 0;
  97. }
  98. static const struct backlight_ops psb_ops = {
  99. .get_brightness = psb_get_brightness,
  100. .update_status = psb_set_brightness,
  101. };
  102. static int psb_backlight_init(struct drm_device *dev)
  103. {
  104. struct drm_psb_private *dev_priv = dev->dev_private;
  105. int ret;
  106. struct backlight_properties props;
  107. memset(&props, 0, sizeof(struct backlight_properties));
  108. props.max_brightness = 100;
  109. props.type = BACKLIGHT_PLATFORM;
  110. psb_backlight_device = backlight_device_register("psb-bl",
  111. NULL, (void *)dev, &psb_ops, &props);
  112. if (IS_ERR(psb_backlight_device))
  113. return PTR_ERR(psb_backlight_device);
  114. ret = psb_backlight_setup(dev);
  115. if (ret < 0) {
  116. backlight_device_unregister(psb_backlight_device);
  117. psb_backlight_device = NULL;
  118. return ret;
  119. }
  120. psb_backlight_device->props.brightness = 100;
  121. psb_backlight_device->props.max_brightness = 100;
  122. backlight_update_status(psb_backlight_device);
  123. dev_priv->backlight_device = psb_backlight_device;
  124. /* This must occur after the backlight is properly initialised */
  125. psb_lid_timer_init(dev_priv);
  126. return 0;
  127. }
  128. #endif
  129. /*
  130. * Provide the Poulsbo specific chip logic and low level methods
  131. * for power management
  132. */
  133. static void psb_init_pm(struct drm_device *dev)
  134. {
  135. struct drm_psb_private *dev_priv = dev->dev_private;
  136. u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
  137. gating &= ~3; /* Disable 2D clock gating */
  138. gating |= 1;
  139. PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
  140. PSB_RSGX32(PSB_CR_CLKGATECTL);
  141. }
  142. /**
  143. * psb_save_display_registers - save registers lost on suspend
  144. * @dev: our DRM device
  145. *
  146. * Save the state we need in order to be able to restore the interface
  147. * upon resume from suspend
  148. */
  149. static int psb_save_display_registers(struct drm_device *dev)
  150. {
  151. struct drm_psb_private *dev_priv = dev->dev_private;
  152. struct drm_crtc *crtc;
  153. struct drm_connector *connector;
  154. struct psb_state *regs = &dev_priv->regs.psb;
  155. /* Display arbitration control + watermarks */
  156. regs->saveDSPARB = PSB_RVDC32(DSPARB);
  157. regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
  158. regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
  159. regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
  160. regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
  161. regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
  162. regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
  163. regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
  164. /* Save crtc and output state */
  165. drm_modeset_lock_all(dev);
  166. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  167. if (drm_helper_crtc_in_use(crtc))
  168. crtc->funcs->save(crtc);
  169. }
  170. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  171. if (connector->funcs->save)
  172. connector->funcs->save(connector);
  173. drm_modeset_unlock_all(dev);
  174. return 0;
  175. }
  176. /**
  177. * psb_restore_display_registers - restore lost register state
  178. * @dev: our DRM device
  179. *
  180. * Restore register state that was lost during suspend and resume.
  181. */
  182. static int psb_restore_display_registers(struct drm_device *dev)
  183. {
  184. struct drm_psb_private *dev_priv = dev->dev_private;
  185. struct drm_crtc *crtc;
  186. struct drm_connector *connector;
  187. struct psb_state *regs = &dev_priv->regs.psb;
  188. /* Display arbitration + watermarks */
  189. PSB_WVDC32(regs->saveDSPARB, DSPARB);
  190. PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
  191. PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
  192. PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
  193. PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
  194. PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
  195. PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
  196. PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
  197. /*make sure VGA plane is off. it initializes to on after reset!*/
  198. PSB_WVDC32(0x80000000, VGACNTRL);
  199. drm_modeset_lock_all(dev);
  200. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
  201. if (drm_helper_crtc_in_use(crtc))
  202. crtc->funcs->restore(crtc);
  203. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  204. if (connector->funcs->restore)
  205. connector->funcs->restore(connector);
  206. drm_modeset_unlock_all(dev);
  207. return 0;
  208. }
  209. static int psb_power_down(struct drm_device *dev)
  210. {
  211. return 0;
  212. }
  213. static int psb_power_up(struct drm_device *dev)
  214. {
  215. return 0;
  216. }
  217. static void psb_get_core_freq(struct drm_device *dev)
  218. {
  219. uint32_t clock;
  220. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  221. struct drm_psb_private *dev_priv = dev->dev_private;
  222. /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
  223. /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
  224. pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
  225. pci_read_config_dword(pci_root, 0xD4, &clock);
  226. pci_dev_put(pci_root);
  227. switch (clock & 0x07) {
  228. case 0:
  229. dev_priv->core_freq = 100;
  230. break;
  231. case 1:
  232. dev_priv->core_freq = 133;
  233. break;
  234. case 2:
  235. dev_priv->core_freq = 150;
  236. break;
  237. case 3:
  238. dev_priv->core_freq = 178;
  239. break;
  240. case 4:
  241. dev_priv->core_freq = 200;
  242. break;
  243. case 5:
  244. case 6:
  245. case 7:
  246. dev_priv->core_freq = 266;
  247. break;
  248. default:
  249. dev_priv->core_freq = 0;
  250. }
  251. }
  252. /* Poulsbo */
  253. static const struct psb_offset psb_regmap[2] = {
  254. {
  255. .fp0 = FPA0,
  256. .fp1 = FPA1,
  257. .cntr = DSPACNTR,
  258. .conf = PIPEACONF,
  259. .src = PIPEASRC,
  260. .dpll = DPLL_A,
  261. .htotal = HTOTAL_A,
  262. .hblank = HBLANK_A,
  263. .hsync = HSYNC_A,
  264. .vtotal = VTOTAL_A,
  265. .vblank = VBLANK_A,
  266. .vsync = VSYNC_A,
  267. .stride = DSPASTRIDE,
  268. .size = DSPASIZE,
  269. .pos = DSPAPOS,
  270. .base = DSPABASE,
  271. .surf = DSPASURF,
  272. .addr = DSPABASE,
  273. .status = PIPEASTAT,
  274. .linoff = DSPALINOFF,
  275. .tileoff = DSPATILEOFF,
  276. .palette = PALETTE_A,
  277. },
  278. {
  279. .fp0 = FPB0,
  280. .fp1 = FPB1,
  281. .cntr = DSPBCNTR,
  282. .conf = PIPEBCONF,
  283. .src = PIPEBSRC,
  284. .dpll = DPLL_B,
  285. .htotal = HTOTAL_B,
  286. .hblank = HBLANK_B,
  287. .hsync = HSYNC_B,
  288. .vtotal = VTOTAL_B,
  289. .vblank = VBLANK_B,
  290. .vsync = VSYNC_B,
  291. .stride = DSPBSTRIDE,
  292. .size = DSPBSIZE,
  293. .pos = DSPBPOS,
  294. .base = DSPBBASE,
  295. .surf = DSPBSURF,
  296. .addr = DSPBBASE,
  297. .status = PIPEBSTAT,
  298. .linoff = DSPBLINOFF,
  299. .tileoff = DSPBTILEOFF,
  300. .palette = PALETTE_B,
  301. }
  302. };
  303. static int psb_chip_setup(struct drm_device *dev)
  304. {
  305. struct drm_psb_private *dev_priv = dev->dev_private;
  306. dev_priv->regmap = psb_regmap;
  307. psb_get_core_freq(dev);
  308. gma_intel_setup_gmbus(dev);
  309. psb_intel_opregion_init(dev);
  310. psb_intel_init_bios(dev);
  311. return 0;
  312. }
  313. static void psb_chip_teardown(struct drm_device *dev)
  314. {
  315. struct drm_psb_private *dev_priv = dev->dev_private;
  316. psb_lid_timer_takedown(dev_priv);
  317. gma_intel_teardown_gmbus(dev);
  318. }
  319. const struct psb_ops psb_chip_ops = {
  320. .name = "Poulsbo",
  321. .accel_2d = 1,
  322. .pipes = 2,
  323. .crtcs = 2,
  324. .hdmi_mask = (1 << 0),
  325. .lvds_mask = (1 << 1),
  326. .cursor_needs_phys = 1,
  327. .sgx_offset = PSB_SGX_OFFSET,
  328. .chip_setup = psb_chip_setup,
  329. .chip_teardown = psb_chip_teardown,
  330. .crtc_helper = &psb_intel_helper_funcs,
  331. .crtc_funcs = &psb_intel_crtc_funcs,
  332. .clock_funcs = &psb_clock_funcs,
  333. .output_init = psb_output_init,
  334. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  335. .backlight_init = psb_backlight_init,
  336. #endif
  337. .init_pm = psb_init_pm,
  338. .save_regs = psb_save_display_registers,
  339. .restore_regs = psb_restore_display_registers,
  340. .power_down = psb_power_down,
  341. .power_up = psb_power_up,
  342. };