radeon_pm.c 25 KB

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  1. /*
  2. * Permission is hereby granted, free of charge, to any person obtaining a
  3. * copy of this software and associated documentation files (the "Software"),
  4. * to deal in the Software without restriction, including without limitation
  5. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  6. * and/or sell copies of the Software, and to permit persons to whom the
  7. * Software is furnished to do so, subject to the following conditions:
  8. *
  9. * The above copyright notice and this permission notice shall be included in
  10. * all copies or substantial portions of the Software.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  15. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18. * OTHER DEALINGS IN THE SOFTWARE.
  19. *
  20. * Authors: Rafał Miłecki <zajec5@gmail.com>
  21. * Alex Deucher <alexdeucher@gmail.com>
  22. */
  23. #include "drmP.h"
  24. #include "radeon.h"
  25. #include "avivod.h"
  26. #ifdef CONFIG_ACPI
  27. #include <linux/acpi.h>
  28. #endif
  29. #include <linux/power_supply.h>
  30. #include <linux/hwmon.h>
  31. #include <linux/hwmon-sysfs.h>
  32. #define RADEON_IDLE_LOOP_MS 100
  33. #define RADEON_RECLOCK_DELAY_MS 200
  34. #define RADEON_WAIT_VBLANK_TIMEOUT 200
  35. #define RADEON_WAIT_IDLE_TIMEOUT 200
  36. static const char *radeon_pm_state_type_name[5] = {
  37. "Default",
  38. "Powersave",
  39. "Battery",
  40. "Balanced",
  41. "Performance",
  42. };
  43. static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44. static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45. static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47. static void radeon_pm_update_profile(struct radeon_device *rdev);
  48. static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49. #define ACPI_AC_CLASS "ac_adapter"
  50. #ifdef CONFIG_ACPI
  51. static int radeon_acpi_event(struct notifier_block *nb,
  52. unsigned long val,
  53. void *data)
  54. {
  55. struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  56. struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  57. if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  58. if (power_supply_is_system_supplied() > 0)
  59. DRM_DEBUG_DRIVER("pm: AC\n");
  60. else
  61. DRM_DEBUG_DRIVER("pm: DC\n");
  62. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  63. if (rdev->pm.profile == PM_PROFILE_AUTO) {
  64. mutex_lock(&rdev->pm.mutex);
  65. radeon_pm_update_profile(rdev);
  66. radeon_pm_set_clocks(rdev);
  67. mutex_unlock(&rdev->pm.mutex);
  68. }
  69. }
  70. }
  71. return NOTIFY_OK;
  72. }
  73. #endif
  74. static void radeon_pm_update_profile(struct radeon_device *rdev)
  75. {
  76. switch (rdev->pm.profile) {
  77. case PM_PROFILE_DEFAULT:
  78. rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  79. break;
  80. case PM_PROFILE_AUTO:
  81. if (power_supply_is_system_supplied() > 0) {
  82. if (rdev->pm.active_crtc_count > 1)
  83. rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  84. else
  85. rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  86. } else {
  87. if (rdev->pm.active_crtc_count > 1)
  88. rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  89. else
  90. rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  91. }
  92. break;
  93. case PM_PROFILE_LOW:
  94. if (rdev->pm.active_crtc_count > 1)
  95. rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  96. else
  97. rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  98. break;
  99. case PM_PROFILE_MID:
  100. if (rdev->pm.active_crtc_count > 1)
  101. rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  102. else
  103. rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  104. break;
  105. case PM_PROFILE_HIGH:
  106. if (rdev->pm.active_crtc_count > 1)
  107. rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  108. else
  109. rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  110. break;
  111. }
  112. if (rdev->pm.active_crtc_count == 0) {
  113. rdev->pm.requested_power_state_index =
  114. rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
  115. rdev->pm.requested_clock_mode_index =
  116. rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
  117. } else {
  118. rdev->pm.requested_power_state_index =
  119. rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
  120. rdev->pm.requested_clock_mode_index =
  121. rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
  122. }
  123. }
  124. static void radeon_unmap_vram_bos(struct radeon_device *rdev)
  125. {
  126. struct radeon_bo *bo, *n;
  127. if (list_empty(&rdev->gem.objects))
  128. return;
  129. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  130. if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
  131. ttm_bo_unmap_virtual(&bo->tbo);
  132. }
  133. }
  134. static void radeon_sync_with_vblank(struct radeon_device *rdev)
  135. {
  136. if (rdev->pm.active_crtcs) {
  137. rdev->pm.vblank_sync = false;
  138. wait_event_timeout(
  139. rdev->irq.vblank_queue, rdev->pm.vblank_sync,
  140. msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
  141. }
  142. }
  143. static void radeon_set_power_state(struct radeon_device *rdev)
  144. {
  145. u32 sclk, mclk;
  146. bool misc_after = false;
  147. if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
  148. (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
  149. return;
  150. if (radeon_gui_idle(rdev)) {
  151. sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
  152. clock_info[rdev->pm.requested_clock_mode_index].sclk;
  153. if (sclk > rdev->clock.default_sclk)
  154. sclk = rdev->clock.default_sclk;
  155. mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
  156. clock_info[rdev->pm.requested_clock_mode_index].mclk;
  157. if (mclk > rdev->clock.default_mclk)
  158. mclk = rdev->clock.default_mclk;
  159. /* upvolt before raising clocks, downvolt after lowering clocks */
  160. if (sclk < rdev->pm.current_sclk)
  161. misc_after = true;
  162. radeon_sync_with_vblank(rdev);
  163. if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  164. if (!radeon_pm_in_vbl(rdev))
  165. return;
  166. }
  167. radeon_pm_prepare(rdev);
  168. if (!misc_after)
  169. /* voltage, pcie lanes, etc.*/
  170. radeon_pm_misc(rdev);
  171. /* set engine clock */
  172. if (sclk != rdev->pm.current_sclk) {
  173. radeon_pm_debug_check_in_vbl(rdev, false);
  174. radeon_set_engine_clock(rdev, sclk);
  175. radeon_pm_debug_check_in_vbl(rdev, true);
  176. rdev->pm.current_sclk = sclk;
  177. DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
  178. }
  179. /* set memory clock */
  180. if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
  181. radeon_pm_debug_check_in_vbl(rdev, false);
  182. radeon_set_memory_clock(rdev, mclk);
  183. radeon_pm_debug_check_in_vbl(rdev, true);
  184. rdev->pm.current_mclk = mclk;
  185. DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
  186. }
  187. if (misc_after)
  188. /* voltage, pcie lanes, etc.*/
  189. radeon_pm_misc(rdev);
  190. radeon_pm_finish(rdev);
  191. rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
  192. rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
  193. } else
  194. DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
  195. }
  196. static void radeon_pm_set_clocks(struct radeon_device *rdev)
  197. {
  198. int i;
  199. /* no need to take locks, etc. if nothing's going to change */
  200. if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
  201. (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
  202. return;
  203. mutex_lock(&rdev->ddev->struct_mutex);
  204. mutex_lock(&rdev->vram_mutex);
  205. mutex_lock(&rdev->cp.mutex);
  206. /* gui idle int has issues on older chips it seems */
  207. if (rdev->family >= CHIP_R600) {
  208. if (rdev->irq.installed) {
  209. /* wait for GPU idle */
  210. rdev->pm.gui_idle = false;
  211. rdev->irq.gui_idle = true;
  212. radeon_irq_set(rdev);
  213. wait_event_interruptible_timeout(
  214. rdev->irq.idle_queue, rdev->pm.gui_idle,
  215. msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  216. rdev->irq.gui_idle = false;
  217. radeon_irq_set(rdev);
  218. }
  219. } else {
  220. if (rdev->cp.ready) {
  221. struct radeon_fence *fence;
  222. radeon_ring_alloc(rdev, 64);
  223. radeon_fence_create(rdev, &fence);
  224. radeon_fence_emit(rdev, fence);
  225. radeon_ring_commit(rdev);
  226. radeon_fence_wait(fence, false);
  227. radeon_fence_unref(&fence);
  228. }
  229. }
  230. radeon_unmap_vram_bos(rdev);
  231. if (rdev->irq.installed) {
  232. for (i = 0; i < rdev->num_crtc; i++) {
  233. if (rdev->pm.active_crtcs & (1 << i)) {
  234. rdev->pm.req_vblank |= (1 << i);
  235. drm_vblank_get(rdev->ddev, i);
  236. }
  237. }
  238. }
  239. radeon_set_power_state(rdev);
  240. if (rdev->irq.installed) {
  241. for (i = 0; i < rdev->num_crtc; i++) {
  242. if (rdev->pm.req_vblank & (1 << i)) {
  243. rdev->pm.req_vblank &= ~(1 << i);
  244. drm_vblank_put(rdev->ddev, i);
  245. }
  246. }
  247. }
  248. /* update display watermarks based on new power state */
  249. radeon_update_bandwidth_info(rdev);
  250. if (rdev->pm.active_crtc_count)
  251. radeon_bandwidth_update(rdev);
  252. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  253. mutex_unlock(&rdev->cp.mutex);
  254. mutex_unlock(&rdev->vram_mutex);
  255. mutex_unlock(&rdev->ddev->struct_mutex);
  256. }
  257. static void radeon_pm_print_states(struct radeon_device *rdev)
  258. {
  259. int i, j;
  260. struct radeon_power_state *power_state;
  261. struct radeon_pm_clock_info *clock_info;
  262. DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
  263. for (i = 0; i < rdev->pm.num_power_states; i++) {
  264. power_state = &rdev->pm.power_state[i];
  265. DRM_DEBUG_DRIVER("State %d: %s\n", i,
  266. radeon_pm_state_type_name[power_state->type]);
  267. if (i == rdev->pm.default_power_state_index)
  268. DRM_DEBUG_DRIVER("\tDefault");
  269. if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  270. DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
  271. if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  272. DRM_DEBUG_DRIVER("\tSingle display only\n");
  273. DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
  274. for (j = 0; j < power_state->num_clock_modes; j++) {
  275. clock_info = &(power_state->clock_info[j]);
  276. if (rdev->flags & RADEON_IS_IGP)
  277. DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
  278. j,
  279. clock_info->sclk * 10,
  280. clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
  281. else
  282. DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
  283. j,
  284. clock_info->sclk * 10,
  285. clock_info->mclk * 10,
  286. clock_info->voltage.voltage,
  287. clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
  288. }
  289. }
  290. }
  291. static ssize_t radeon_get_pm_profile(struct device *dev,
  292. struct device_attribute *attr,
  293. char *buf)
  294. {
  295. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  296. struct radeon_device *rdev = ddev->dev_private;
  297. int cp = rdev->pm.profile;
  298. return snprintf(buf, PAGE_SIZE, "%s\n",
  299. (cp == PM_PROFILE_AUTO) ? "auto" :
  300. (cp == PM_PROFILE_LOW) ? "low" :
  301. (cp == PM_PROFILE_MID) ? "mid" :
  302. (cp == PM_PROFILE_HIGH) ? "high" : "default");
  303. }
  304. static ssize_t radeon_set_pm_profile(struct device *dev,
  305. struct device_attribute *attr,
  306. const char *buf,
  307. size_t count)
  308. {
  309. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  310. struct radeon_device *rdev = ddev->dev_private;
  311. mutex_lock(&rdev->pm.mutex);
  312. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  313. if (strncmp("default", buf, strlen("default")) == 0)
  314. rdev->pm.profile = PM_PROFILE_DEFAULT;
  315. else if (strncmp("auto", buf, strlen("auto")) == 0)
  316. rdev->pm.profile = PM_PROFILE_AUTO;
  317. else if (strncmp("low", buf, strlen("low")) == 0)
  318. rdev->pm.profile = PM_PROFILE_LOW;
  319. else if (strncmp("mid", buf, strlen("mid")) == 0)
  320. rdev->pm.profile = PM_PROFILE_MID;
  321. else if (strncmp("high", buf, strlen("high")) == 0)
  322. rdev->pm.profile = PM_PROFILE_HIGH;
  323. else {
  324. DRM_ERROR("invalid power profile!\n");
  325. goto fail;
  326. }
  327. radeon_pm_update_profile(rdev);
  328. radeon_pm_set_clocks(rdev);
  329. }
  330. fail:
  331. mutex_unlock(&rdev->pm.mutex);
  332. return count;
  333. }
  334. static ssize_t radeon_get_pm_method(struct device *dev,
  335. struct device_attribute *attr,
  336. char *buf)
  337. {
  338. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  339. struct radeon_device *rdev = ddev->dev_private;
  340. int pm = rdev->pm.pm_method;
  341. return snprintf(buf, PAGE_SIZE, "%s\n",
  342. (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
  343. }
  344. static ssize_t radeon_set_pm_method(struct device *dev,
  345. struct device_attribute *attr,
  346. const char *buf,
  347. size_t count)
  348. {
  349. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  350. struct radeon_device *rdev = ddev->dev_private;
  351. if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
  352. mutex_lock(&rdev->pm.mutex);
  353. rdev->pm.pm_method = PM_METHOD_DYNPM;
  354. rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
  355. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  356. mutex_unlock(&rdev->pm.mutex);
  357. } else if (strncmp("profile", buf, strlen("profile")) == 0) {
  358. bool flush_wq = false;
  359. mutex_lock(&rdev->pm.mutex);
  360. if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  361. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  362. flush_wq = true;
  363. }
  364. /* disable dynpm */
  365. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  366. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  367. rdev->pm.pm_method = PM_METHOD_PROFILE;
  368. mutex_unlock(&rdev->pm.mutex);
  369. if (flush_wq)
  370. flush_workqueue(rdev->wq);
  371. } else {
  372. DRM_ERROR("invalid power method!\n");
  373. goto fail;
  374. }
  375. radeon_pm_compute_clocks(rdev);
  376. fail:
  377. return count;
  378. }
  379. static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
  380. static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
  381. static ssize_t radeon_hwmon_show_temp(struct device *dev,
  382. struct device_attribute *attr,
  383. char *buf)
  384. {
  385. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  386. struct radeon_device *rdev = ddev->dev_private;
  387. u32 temp;
  388. switch (rdev->pm.int_thermal_type) {
  389. case THERMAL_TYPE_RV6XX:
  390. temp = rv6xx_get_temp(rdev);
  391. break;
  392. case THERMAL_TYPE_RV770:
  393. temp = rv770_get_temp(rdev);
  394. break;
  395. case THERMAL_TYPE_EVERGREEN:
  396. temp = evergreen_get_temp(rdev);
  397. break;
  398. case THERMAL_TYPE_SUMO:
  399. temp = sumo_get_temp(rdev);
  400. break;
  401. default:
  402. temp = 0;
  403. break;
  404. }
  405. return snprintf(buf, PAGE_SIZE, "%d\n", temp);
  406. }
  407. static ssize_t radeon_hwmon_show_name(struct device *dev,
  408. struct device_attribute *attr,
  409. char *buf)
  410. {
  411. return sprintf(buf, "radeon\n");
  412. }
  413. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
  414. static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
  415. static struct attribute *hwmon_attributes[] = {
  416. &sensor_dev_attr_temp1_input.dev_attr.attr,
  417. &sensor_dev_attr_name.dev_attr.attr,
  418. NULL
  419. };
  420. static const struct attribute_group hwmon_attrgroup = {
  421. .attrs = hwmon_attributes,
  422. };
  423. static int radeon_hwmon_init(struct radeon_device *rdev)
  424. {
  425. int err = 0;
  426. rdev->pm.int_hwmon_dev = NULL;
  427. switch (rdev->pm.int_thermal_type) {
  428. case THERMAL_TYPE_RV6XX:
  429. case THERMAL_TYPE_RV770:
  430. case THERMAL_TYPE_EVERGREEN:
  431. case THERMAL_TYPE_SUMO:
  432. rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
  433. if (IS_ERR(rdev->pm.int_hwmon_dev)) {
  434. err = PTR_ERR(rdev->pm.int_hwmon_dev);
  435. dev_err(rdev->dev,
  436. "Unable to register hwmon device: %d\n", err);
  437. break;
  438. }
  439. dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
  440. err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
  441. &hwmon_attrgroup);
  442. if (err) {
  443. dev_err(rdev->dev,
  444. "Unable to create hwmon sysfs file: %d\n", err);
  445. hwmon_device_unregister(rdev->dev);
  446. }
  447. break;
  448. default:
  449. break;
  450. }
  451. return err;
  452. }
  453. static void radeon_hwmon_fini(struct radeon_device *rdev)
  454. {
  455. if (rdev->pm.int_hwmon_dev) {
  456. sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
  457. hwmon_device_unregister(rdev->pm.int_hwmon_dev);
  458. }
  459. }
  460. void radeon_pm_suspend(struct radeon_device *rdev)
  461. {
  462. bool flush_wq = false;
  463. mutex_lock(&rdev->pm.mutex);
  464. if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  465. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  466. if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
  467. rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
  468. flush_wq = true;
  469. }
  470. mutex_unlock(&rdev->pm.mutex);
  471. if (flush_wq)
  472. flush_workqueue(rdev->wq);
  473. }
  474. void radeon_pm_resume(struct radeon_device *rdev)
  475. {
  476. /* asic init will reset the default power state */
  477. mutex_lock(&rdev->pm.mutex);
  478. rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
  479. rdev->pm.current_clock_mode_index = 0;
  480. rdev->pm.current_sclk = rdev->clock.default_sclk;
  481. rdev->pm.current_mclk = rdev->clock.default_mclk;
  482. rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
  483. if (rdev->pm.pm_method == PM_METHOD_DYNPM
  484. && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
  485. rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
  486. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  487. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  488. }
  489. mutex_unlock(&rdev->pm.mutex);
  490. radeon_pm_compute_clocks(rdev);
  491. }
  492. int radeon_pm_init(struct radeon_device *rdev)
  493. {
  494. int ret;
  495. /* default to profile method */
  496. rdev->pm.pm_method = PM_METHOD_PROFILE;
  497. rdev->pm.profile = PM_PROFILE_DEFAULT;
  498. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  499. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  500. rdev->pm.dynpm_can_upclock = true;
  501. rdev->pm.dynpm_can_downclock = true;
  502. rdev->pm.current_sclk = rdev->clock.default_sclk;
  503. rdev->pm.current_mclk = rdev->clock.default_mclk;
  504. rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
  505. if (rdev->bios) {
  506. if (rdev->is_atom_bios)
  507. radeon_atombios_get_power_modes(rdev);
  508. else
  509. radeon_combios_get_power_modes(rdev);
  510. radeon_pm_print_states(rdev);
  511. radeon_pm_init_profile(rdev);
  512. }
  513. /* set up the internal thermal sensor if applicable */
  514. ret = radeon_hwmon_init(rdev);
  515. if (ret)
  516. return ret;
  517. if (rdev->pm.num_power_states > 1) {
  518. /* where's the best place to put these? */
  519. ret = device_create_file(rdev->dev, &dev_attr_power_profile);
  520. if (ret)
  521. DRM_ERROR("failed to create device file for power profile\n");
  522. ret = device_create_file(rdev->dev, &dev_attr_power_method);
  523. if (ret)
  524. DRM_ERROR("failed to create device file for power method\n");
  525. #ifdef CONFIG_ACPI
  526. rdev->acpi_nb.notifier_call = radeon_acpi_event;
  527. register_acpi_notifier(&rdev->acpi_nb);
  528. #endif
  529. INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
  530. if (radeon_debugfs_pm_init(rdev)) {
  531. DRM_ERROR("Failed to register debugfs file for PM!\n");
  532. }
  533. DRM_INFO("radeon: power management initialized\n");
  534. }
  535. return 0;
  536. }
  537. void radeon_pm_fini(struct radeon_device *rdev)
  538. {
  539. if (rdev->pm.num_power_states > 1) {
  540. bool flush_wq = false;
  541. mutex_lock(&rdev->pm.mutex);
  542. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  543. rdev->pm.profile = PM_PROFILE_DEFAULT;
  544. radeon_pm_update_profile(rdev);
  545. radeon_pm_set_clocks(rdev);
  546. } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  547. /* cancel work */
  548. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  549. flush_wq = true;
  550. /* reset default clocks */
  551. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  552. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  553. radeon_pm_set_clocks(rdev);
  554. }
  555. mutex_unlock(&rdev->pm.mutex);
  556. if (flush_wq)
  557. flush_workqueue(rdev->wq);
  558. device_remove_file(rdev->dev, &dev_attr_power_profile);
  559. device_remove_file(rdev->dev, &dev_attr_power_method);
  560. #ifdef CONFIG_ACPI
  561. unregister_acpi_notifier(&rdev->acpi_nb);
  562. #endif
  563. }
  564. radeon_hwmon_fini(rdev);
  565. }
  566. void radeon_pm_compute_clocks(struct radeon_device *rdev)
  567. {
  568. struct drm_device *ddev = rdev->ddev;
  569. struct drm_crtc *crtc;
  570. struct radeon_crtc *radeon_crtc;
  571. if (rdev->pm.num_power_states < 2)
  572. return;
  573. mutex_lock(&rdev->pm.mutex);
  574. rdev->pm.active_crtcs = 0;
  575. rdev->pm.active_crtc_count = 0;
  576. list_for_each_entry(crtc,
  577. &ddev->mode_config.crtc_list, head) {
  578. radeon_crtc = to_radeon_crtc(crtc);
  579. if (radeon_crtc->enabled) {
  580. rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
  581. rdev->pm.active_crtc_count++;
  582. }
  583. }
  584. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  585. radeon_pm_update_profile(rdev);
  586. radeon_pm_set_clocks(rdev);
  587. } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  588. if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
  589. if (rdev->pm.active_crtc_count > 1) {
  590. if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
  591. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  592. rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
  593. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  594. radeon_pm_get_dynpm_state(rdev);
  595. radeon_pm_set_clocks(rdev);
  596. DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
  597. }
  598. } else if (rdev->pm.active_crtc_count == 1) {
  599. /* TODO: Increase clocks if needed for current mode */
  600. if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
  601. rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
  602. rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
  603. radeon_pm_get_dynpm_state(rdev);
  604. radeon_pm_set_clocks(rdev);
  605. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  606. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  607. } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
  608. rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
  609. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  610. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  611. DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
  612. }
  613. } else { /* count == 0 */
  614. if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
  615. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  616. rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
  617. rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
  618. radeon_pm_get_dynpm_state(rdev);
  619. radeon_pm_set_clocks(rdev);
  620. }
  621. }
  622. }
  623. }
  624. mutex_unlock(&rdev->pm.mutex);
  625. }
  626. static bool radeon_pm_in_vbl(struct radeon_device *rdev)
  627. {
  628. int crtc, vpos, hpos, vbl_status;
  629. bool in_vbl = true;
  630. /* Iterate over all active crtc's. All crtc's must be in vblank,
  631. * otherwise return in_vbl == false.
  632. */
  633. for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
  634. if (rdev->pm.active_crtcs & (1 << crtc)) {
  635. vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
  636. if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
  637. !(vbl_status & DRM_SCANOUTPOS_INVBL))
  638. in_vbl = false;
  639. }
  640. }
  641. return in_vbl;
  642. }
  643. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
  644. {
  645. u32 stat_crtc = 0;
  646. bool in_vbl = radeon_pm_in_vbl(rdev);
  647. if (in_vbl == false)
  648. DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
  649. finish ? "exit" : "entry");
  650. return in_vbl;
  651. }
  652. static void radeon_dynpm_idle_work_handler(struct work_struct *work)
  653. {
  654. struct radeon_device *rdev;
  655. int resched;
  656. rdev = container_of(work, struct radeon_device,
  657. pm.dynpm_idle_work.work);
  658. resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
  659. mutex_lock(&rdev->pm.mutex);
  660. if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
  661. unsigned long irq_flags;
  662. int not_processed = 0;
  663. read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  664. if (!list_empty(&rdev->fence_drv.emited)) {
  665. struct list_head *ptr;
  666. list_for_each(ptr, &rdev->fence_drv.emited) {
  667. /* count up to 3, that's enought info */
  668. if (++not_processed >= 3)
  669. break;
  670. }
  671. }
  672. read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  673. if (not_processed >= 3) { /* should upclock */
  674. if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
  675. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  676. } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
  677. rdev->pm.dynpm_can_upclock) {
  678. rdev->pm.dynpm_planned_action =
  679. DYNPM_ACTION_UPCLOCK;
  680. rdev->pm.dynpm_action_timeout = jiffies +
  681. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  682. }
  683. } else if (not_processed == 0) { /* should downclock */
  684. if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
  685. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  686. } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
  687. rdev->pm.dynpm_can_downclock) {
  688. rdev->pm.dynpm_planned_action =
  689. DYNPM_ACTION_DOWNCLOCK;
  690. rdev->pm.dynpm_action_timeout = jiffies +
  691. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  692. }
  693. }
  694. /* Note, radeon_pm_set_clocks is called with static_switch set
  695. * to false since we want to wait for vbl to avoid flicker.
  696. */
  697. if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
  698. jiffies > rdev->pm.dynpm_action_timeout) {
  699. radeon_pm_get_dynpm_state(rdev);
  700. radeon_pm_set_clocks(rdev);
  701. }
  702. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  703. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  704. }
  705. mutex_unlock(&rdev->pm.mutex);
  706. ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
  707. }
  708. /*
  709. * Debugfs info
  710. */
  711. #if defined(CONFIG_DEBUG_FS)
  712. static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
  713. {
  714. struct drm_info_node *node = (struct drm_info_node *) m->private;
  715. struct drm_device *dev = node->minor->dev;
  716. struct radeon_device *rdev = dev->dev_private;
  717. seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
  718. seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
  719. seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
  720. if (rdev->asic->get_memory_clock)
  721. seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
  722. if (rdev->pm.current_vddc)
  723. seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
  724. if (rdev->asic->get_pcie_lanes)
  725. seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
  726. return 0;
  727. }
  728. static struct drm_info_list radeon_pm_info_list[] = {
  729. {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
  730. };
  731. #endif
  732. static int radeon_debugfs_pm_init(struct radeon_device *rdev)
  733. {
  734. #if defined(CONFIG_DEBUG_FS)
  735. return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
  736. #else
  737. return 0;
  738. #endif
  739. }