radeon_irq_kms.c 5.9 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include "drmP.h"
  29. #include "drm_crtc_helper.h"
  30. #include "radeon_drm.h"
  31. #include "radeon_reg.h"
  32. #include "radeon.h"
  33. #include "atom.h"
  34. irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
  35. {
  36. struct drm_device *dev = (struct drm_device *) arg;
  37. struct radeon_device *rdev = dev->dev_private;
  38. return radeon_irq_process(rdev);
  39. }
  40. /*
  41. * Handle hotplug events outside the interrupt handler proper.
  42. */
  43. static void radeon_hotplug_work_func(struct work_struct *work)
  44. {
  45. struct radeon_device *rdev = container_of(work, struct radeon_device,
  46. hotplug_work);
  47. struct drm_device *dev = rdev->ddev;
  48. struct drm_mode_config *mode_config = &dev->mode_config;
  49. struct drm_connector *connector;
  50. if (mode_config->num_connector) {
  51. list_for_each_entry(connector, &mode_config->connector_list, head)
  52. radeon_connector_hotplug(connector);
  53. }
  54. /* Just fire off a uevent and let userspace tell us what to do */
  55. drm_helper_hpd_irq_event(dev);
  56. }
  57. void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
  58. {
  59. struct radeon_device *rdev = dev->dev_private;
  60. unsigned i;
  61. INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
  62. /* Disable *all* interrupts */
  63. rdev->irq.sw_int = false;
  64. rdev->irq.gui_idle = false;
  65. for (i = 0; i < rdev->num_crtc; i++)
  66. rdev->irq.crtc_vblank_int[i] = false;
  67. for (i = 0; i < 6; i++) {
  68. rdev->irq.hpd[i] = false;
  69. rdev->irq.pflip[i] = false;
  70. }
  71. radeon_irq_set(rdev);
  72. /* Clear bits */
  73. radeon_irq_process(rdev);
  74. }
  75. int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
  76. {
  77. struct radeon_device *rdev = dev->dev_private;
  78. dev->max_vblank_count = 0x001fffff;
  79. rdev->irq.sw_int = true;
  80. radeon_irq_set(rdev);
  81. return 0;
  82. }
  83. void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
  84. {
  85. struct radeon_device *rdev = dev->dev_private;
  86. unsigned i;
  87. if (rdev == NULL) {
  88. return;
  89. }
  90. /* Disable *all* interrupts */
  91. rdev->irq.sw_int = false;
  92. rdev->irq.gui_idle = false;
  93. for (i = 0; i < rdev->num_crtc; i++)
  94. rdev->irq.crtc_vblank_int[i] = false;
  95. for (i = 0; i < 6; i++) {
  96. rdev->irq.hpd[i] = false;
  97. rdev->irq.pflip[i] = false;
  98. }
  99. radeon_irq_set(rdev);
  100. }
  101. int radeon_irq_kms_init(struct radeon_device *rdev)
  102. {
  103. int r = 0;
  104. spin_lock_init(&rdev->irq.sw_lock);
  105. r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
  106. if (r) {
  107. return r;
  108. }
  109. /* enable msi */
  110. rdev->msi_enabled = 0;
  111. /* MSIs don't seem to work reliably on all IGP
  112. * chips. Disable MSI on them for now.
  113. */
  114. if ((rdev->family >= CHIP_RV380) &&
  115. ((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
  116. (!(rdev->flags & RADEON_IS_AGP))) {
  117. int ret = pci_enable_msi(rdev->pdev);
  118. if (!ret) {
  119. rdev->msi_enabled = 1;
  120. dev_info(rdev->dev, "radeon: using MSI.\n");
  121. }
  122. }
  123. rdev->irq.installed = true;
  124. r = drm_irq_install(rdev->ddev);
  125. if (r) {
  126. rdev->irq.installed = false;
  127. return r;
  128. }
  129. DRM_INFO("radeon: irq initialized.\n");
  130. return 0;
  131. }
  132. void radeon_irq_kms_fini(struct radeon_device *rdev)
  133. {
  134. drm_vblank_cleanup(rdev->ddev);
  135. if (rdev->irq.installed) {
  136. drm_irq_uninstall(rdev->ddev);
  137. rdev->irq.installed = false;
  138. if (rdev->msi_enabled)
  139. pci_disable_msi(rdev->pdev);
  140. }
  141. }
  142. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev)
  143. {
  144. unsigned long irqflags;
  145. spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
  146. if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount == 1)) {
  147. rdev->irq.sw_int = true;
  148. radeon_irq_set(rdev);
  149. }
  150. spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
  151. }
  152. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev)
  153. {
  154. unsigned long irqflags;
  155. spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
  156. BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount <= 0);
  157. if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount == 0)) {
  158. rdev->irq.sw_int = false;
  159. radeon_irq_set(rdev);
  160. }
  161. spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
  162. }
  163. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
  164. {
  165. unsigned long irqflags;
  166. if (crtc < 0 || crtc >= rdev->num_crtc)
  167. return;
  168. spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
  169. if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
  170. rdev->irq.pflip[crtc] = true;
  171. radeon_irq_set(rdev);
  172. }
  173. spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
  174. }
  175. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
  176. {
  177. unsigned long irqflags;
  178. if (crtc < 0 || crtc >= rdev->num_crtc)
  179. return;
  180. spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
  181. BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
  182. if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
  183. rdev->irq.pflip[crtc] = false;
  184. radeon_irq_set(rdev);
  185. }
  186. spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
  187. }