radeon_fence.c 11 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  42. {
  43. unsigned long irq_flags;
  44. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  45. if (fence->emited) {
  46. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  47. return 0;
  48. }
  49. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  50. if (!rdev->cp.ready) {
  51. /* FIXME: cp is not running assume everythings is done right
  52. * away
  53. */
  54. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  55. } else
  56. radeon_fence_ring_emit(rdev, fence);
  57. fence->emited = true;
  58. list_del(&fence->list);
  59. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  60. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  61. return 0;
  62. }
  63. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  64. {
  65. struct radeon_fence *fence;
  66. struct list_head *i, *n;
  67. uint32_t seq;
  68. bool wake = false;
  69. unsigned long cjiffies;
  70. if (rdev->wb.enabled) {
  71. u32 scratch_index;
  72. if (rdev->wb.use_event)
  73. scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  74. else
  75. scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  76. seq = rdev->wb.wb[scratch_index/4];
  77. } else
  78. seq = RREG32(rdev->fence_drv.scratch_reg);
  79. if (seq != rdev->fence_drv.last_seq) {
  80. rdev->fence_drv.last_seq = seq;
  81. rdev->fence_drv.last_jiffies = jiffies;
  82. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  83. } else {
  84. cjiffies = jiffies;
  85. if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) {
  86. cjiffies -= rdev->fence_drv.last_jiffies;
  87. if (time_after(rdev->fence_drv.last_timeout, cjiffies)) {
  88. /* update the timeout */
  89. rdev->fence_drv.last_timeout -= cjiffies;
  90. } else {
  91. /* the 500ms timeout is elapsed we should test
  92. * for GPU lockup
  93. */
  94. rdev->fence_drv.last_timeout = 1;
  95. }
  96. } else {
  97. /* wrap around update last jiffies, we will just wait
  98. * a little longer
  99. */
  100. rdev->fence_drv.last_jiffies = cjiffies;
  101. }
  102. return false;
  103. }
  104. n = NULL;
  105. list_for_each(i, &rdev->fence_drv.emited) {
  106. fence = list_entry(i, struct radeon_fence, list);
  107. if (fence->seq == seq) {
  108. n = i;
  109. break;
  110. }
  111. }
  112. /* all fence previous to this one are considered as signaled */
  113. if (n) {
  114. i = n;
  115. do {
  116. n = i->prev;
  117. list_del(i);
  118. list_add_tail(i, &rdev->fence_drv.signaled);
  119. fence = list_entry(i, struct radeon_fence, list);
  120. fence->signaled = true;
  121. i = n;
  122. } while (i != &rdev->fence_drv.emited);
  123. wake = true;
  124. }
  125. return wake;
  126. }
  127. static void radeon_fence_destroy(struct kref *kref)
  128. {
  129. unsigned long irq_flags;
  130. struct radeon_fence *fence;
  131. fence = container_of(kref, struct radeon_fence, kref);
  132. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  133. list_del(&fence->list);
  134. fence->emited = false;
  135. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  136. kfree(fence);
  137. }
  138. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  139. {
  140. unsigned long irq_flags;
  141. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  142. if ((*fence) == NULL) {
  143. return -ENOMEM;
  144. }
  145. kref_init(&((*fence)->kref));
  146. (*fence)->rdev = rdev;
  147. (*fence)->emited = false;
  148. (*fence)->signaled = false;
  149. (*fence)->seq = 0;
  150. INIT_LIST_HEAD(&(*fence)->list);
  151. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  152. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  153. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  154. return 0;
  155. }
  156. bool radeon_fence_signaled(struct radeon_fence *fence)
  157. {
  158. unsigned long irq_flags;
  159. bool signaled = false;
  160. if (!fence)
  161. return true;
  162. if (fence->rdev->gpu_lockup)
  163. return true;
  164. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  165. signaled = fence->signaled;
  166. /* if we are shuting down report all fence as signaled */
  167. if (fence->rdev->shutdown) {
  168. signaled = true;
  169. }
  170. if (!fence->emited) {
  171. WARN(1, "Querying an unemited fence : %p !\n", fence);
  172. signaled = true;
  173. }
  174. if (!signaled) {
  175. radeon_fence_poll_locked(fence->rdev);
  176. signaled = fence->signaled;
  177. }
  178. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  179. return signaled;
  180. }
  181. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  182. {
  183. struct radeon_device *rdev;
  184. unsigned long irq_flags, timeout;
  185. u32 seq;
  186. int r;
  187. if (fence == NULL) {
  188. WARN(1, "Querying an invalid fence : %p !\n", fence);
  189. return 0;
  190. }
  191. rdev = fence->rdev;
  192. if (radeon_fence_signaled(fence)) {
  193. return 0;
  194. }
  195. timeout = rdev->fence_drv.last_timeout;
  196. retry:
  197. /* save current sequence used to check for GPU lockup */
  198. seq = rdev->fence_drv.last_seq;
  199. if (intr) {
  200. radeon_irq_kms_sw_irq_get(rdev);
  201. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  202. radeon_fence_signaled(fence), timeout);
  203. radeon_irq_kms_sw_irq_put(rdev);
  204. if (unlikely(r < 0)) {
  205. return r;
  206. }
  207. } else {
  208. radeon_irq_kms_sw_irq_get(rdev);
  209. r = wait_event_timeout(rdev->fence_drv.queue,
  210. radeon_fence_signaled(fence), timeout);
  211. radeon_irq_kms_sw_irq_put(rdev);
  212. }
  213. if (unlikely(!radeon_fence_signaled(fence))) {
  214. /* we were interrupted for some reason and fence isn't
  215. * isn't signaled yet, resume wait
  216. */
  217. if (r) {
  218. timeout = r;
  219. goto retry;
  220. }
  221. /* don't protect read access to rdev->fence_drv.last_seq
  222. * if we experiencing a lockup the value doesn't change
  223. */
  224. if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
  225. /* good news we believe it's a lockup */
  226. WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  227. fence->seq, seq);
  228. /* FIXME: what should we do ? marking everyone
  229. * as signaled for now
  230. */
  231. rdev->gpu_lockup = true;
  232. r = radeon_gpu_reset(rdev);
  233. if (r)
  234. return r;
  235. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  236. rdev->gpu_lockup = false;
  237. }
  238. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  239. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  240. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  241. rdev->fence_drv.last_jiffies = jiffies;
  242. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  243. goto retry;
  244. }
  245. return 0;
  246. }
  247. int radeon_fence_wait_next(struct radeon_device *rdev)
  248. {
  249. unsigned long irq_flags;
  250. struct radeon_fence *fence;
  251. int r;
  252. if (rdev->gpu_lockup) {
  253. return 0;
  254. }
  255. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  256. if (list_empty(&rdev->fence_drv.emited)) {
  257. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  258. return 0;
  259. }
  260. fence = list_entry(rdev->fence_drv.emited.next,
  261. struct radeon_fence, list);
  262. radeon_fence_ref(fence);
  263. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  264. r = radeon_fence_wait(fence, false);
  265. radeon_fence_unref(&fence);
  266. return r;
  267. }
  268. int radeon_fence_wait_last(struct radeon_device *rdev)
  269. {
  270. unsigned long irq_flags;
  271. struct radeon_fence *fence;
  272. int r;
  273. if (rdev->gpu_lockup) {
  274. return 0;
  275. }
  276. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  277. if (list_empty(&rdev->fence_drv.emited)) {
  278. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  279. return 0;
  280. }
  281. fence = list_entry(rdev->fence_drv.emited.prev,
  282. struct radeon_fence, list);
  283. radeon_fence_ref(fence);
  284. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  285. r = radeon_fence_wait(fence, false);
  286. radeon_fence_unref(&fence);
  287. return r;
  288. }
  289. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  290. {
  291. kref_get(&fence->kref);
  292. return fence;
  293. }
  294. void radeon_fence_unref(struct radeon_fence **fence)
  295. {
  296. struct radeon_fence *tmp = *fence;
  297. *fence = NULL;
  298. if (tmp) {
  299. kref_put(&tmp->kref, &radeon_fence_destroy);
  300. }
  301. }
  302. void radeon_fence_process(struct radeon_device *rdev)
  303. {
  304. unsigned long irq_flags;
  305. bool wake;
  306. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  307. wake = radeon_fence_poll_locked(rdev);
  308. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  309. if (wake) {
  310. wake_up_all(&rdev->fence_drv.queue);
  311. }
  312. }
  313. int radeon_fence_driver_init(struct radeon_device *rdev)
  314. {
  315. unsigned long irq_flags;
  316. int r;
  317. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  318. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  319. if (r) {
  320. dev_err(rdev->dev, "fence failed to get scratch register\n");
  321. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  322. return r;
  323. }
  324. WREG32(rdev->fence_drv.scratch_reg, 0);
  325. atomic_set(&rdev->fence_drv.seq, 0);
  326. INIT_LIST_HEAD(&rdev->fence_drv.created);
  327. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  328. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  329. init_waitqueue_head(&rdev->fence_drv.queue);
  330. rdev->fence_drv.initialized = true;
  331. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  332. if (radeon_debugfs_fence_init(rdev)) {
  333. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  334. }
  335. return 0;
  336. }
  337. void radeon_fence_driver_fini(struct radeon_device *rdev)
  338. {
  339. unsigned long irq_flags;
  340. if (!rdev->fence_drv.initialized)
  341. return;
  342. wake_up_all(&rdev->fence_drv.queue);
  343. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  344. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  345. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  346. rdev->fence_drv.initialized = false;
  347. }
  348. /*
  349. * Fence debugfs
  350. */
  351. #if defined(CONFIG_DEBUG_FS)
  352. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  353. {
  354. struct drm_info_node *node = (struct drm_info_node *)m->private;
  355. struct drm_device *dev = node->minor->dev;
  356. struct radeon_device *rdev = dev->dev_private;
  357. struct radeon_fence *fence;
  358. seq_printf(m, "Last signaled fence 0x%08X\n",
  359. RREG32(rdev->fence_drv.scratch_reg));
  360. if (!list_empty(&rdev->fence_drv.emited)) {
  361. fence = list_entry(rdev->fence_drv.emited.prev,
  362. struct radeon_fence, list);
  363. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  364. fence, fence->seq);
  365. }
  366. return 0;
  367. }
  368. static struct drm_info_list radeon_debugfs_fence_list[] = {
  369. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  370. };
  371. #endif
  372. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  373. {
  374. #if defined(CONFIG_DEBUG_FS)
  375. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  376. #else
  377. return 0;
  378. #endif
  379. }