Inicio Explorar Ayuda
Registro Iniciar sesión
phyus
/
linux-vybrid_public
8
0
Fork 0
Archivos Incidencias 0 Pull Requests 0 Wiki
Árbol: d908175cca
Ramas Etiquetas
linux-vybrid_pu...
/
drivers
/
gpu
/
drm
/
radeon
/
radeon_asic.h

radeon_asic.h 15 KB
Histórico Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328 
  1. /*
    2. 

  2.  * Copyright 2008 Advanced Micro Devices, Inc.
    3. 

  3.  * Copyright 2008 Red Hat Inc.
    4. 

  4.  * Copyright 2009 Jerome Glisse.
    5. 

  5.  *
    6. 

  6.  * Permission is hereby granted, free of charge, to any person obtaining a
    7. 

  7.  * copy of this software and associated documentation files (the "Software"),
    8. 

  8.  * to deal in the Software without restriction, including without limitation
    9. 

  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    10. 

  10.  * and/or sell copies of the Software, and to permit persons to whom the
    11. 

  11.  * Software is furnished to do so, subject to the following conditions:
    12. 

  12.  *
    13. 

  13.  * The above copyright notice and this permission notice shall be included in
    14. 

  14.  * all copies or substantial portions of the Software.
    15. 

  15.  *
    16. 

  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    17. 

  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    18. 

  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    19. 

  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    20. 

  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    21. 

  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    22. 

  22.  * OTHER DEALINGS IN THE SOFTWARE.
    23. 

  23.  *
    24. 

  24.  * Authors: Dave Airlie
    25. 

  25.  *          Alex Deucher
    26. 

  26.  *          Jerome Glisse
    27. 

  27.  */
    28. 

  28. #ifndef __RADEON_ASIC_H__
    29. 

  29. #define __RADEON_ASIC_H__
    30. 

  30. 

  31. /*
    32. 

  32.  * common functions
    33. 

  33.  */
    34. 

  34. uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
    35. 

  35. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    36. 

  36. uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
    37. 

  37. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
    38. 

  38. 

  39. uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
    40. 

  40. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    41. 

  41. uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
    42. 

  42. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
    43. 

  43. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
    44. 

  44. 

  45. /*
    46. 

  46.  * r100,rv100,rs100,rv200,rs200
    47. 

  47.  */
    48. 

  48. struct r100_mc_save {
    49. 

  49. 	u32	GENMO_WT;
    50. 

  50. 	u32	CRTC_EXT_CNTL;
    51. 

  51. 	u32	CRTC_GEN_CNTL;
    52. 

  52. 	u32	CRTC2_GEN_CNTL;
    53. 

  53. 	u32	CUR_OFFSET;
    54. 

  54. 	u32	CUR2_OFFSET;
    55. 

  55. };
    56. 

  56. int r100_init(struct radeon_device *rdev);
    57. 

  57. void r100_fini(struct radeon_device *rdev);
    58. 

  58. int r100_suspend(struct radeon_device *rdev);
    59. 

  59. int r100_resume(struct radeon_device *rdev);
    60. 

  60. uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
    61. 

  61. void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    62. 

  62. void r100_vga_set_state(struct radeon_device *rdev, bool state);
    63. 

  63. bool r100_gpu_is_lockup(struct radeon_device *rdev);
    64. 

  64. int r100_asic_reset(struct radeon_device *rdev);
    65. 

  65. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
    66. 

  66. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
    67. 

  67. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    68. 

  68. void r100_cp_commit(struct radeon_device *rdev);
    69. 

  69. void r100_ring_start(struct radeon_device *rdev);
    70. 

  70. int r100_irq_set(struct radeon_device *rdev);
    71. 

  71. int r100_irq_process(struct radeon_device *rdev);
    72. 

  72. void r100_fence_ring_emit(struct radeon_device *rdev,
    73. 

  73. 			  struct radeon_fence *fence);
    74. 

  74. int r100_cs_parse(struct radeon_cs_parser *p);
    75. 

  75. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    76. 

  76. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
    77. 

  77. int r100_copy_blit(struct radeon_device *rdev,
    78. 

  78. 		   uint64_t src_offset,
    79. 

  79. 		   uint64_t dst_offset,
    80. 

  80. 		   unsigned num_pages,
    81. 

  81. 		   struct radeon_fence *fence);
    82. 

  82. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
    83. 

  83. 			 uint32_t tiling_flags, uint32_t pitch,
    84. 

  84. 			 uint32_t offset, uint32_t obj_size);
    85. 

  85. void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
    86. 

  86. void r100_bandwidth_update(struct radeon_device *rdev);
    87. 

  87. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    88. 

  88. int r100_ring_test(struct radeon_device *rdev);
    89. 

  89. void r100_hpd_init(struct radeon_device *rdev);
    90. 

  90. void r100_hpd_fini(struct radeon_device *rdev);
    91. 

  91. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    92. 

  92. void r100_hpd_set_polarity(struct radeon_device *rdev,
    93. 

  93. 			   enum radeon_hpd_id hpd);
    94. 

  94. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
    95. 

  95. int r100_debugfs_cp_init(struct radeon_device *rdev);
    96. 

  96. void r100_cp_disable(struct radeon_device *rdev);
    97. 

  97. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
    98. 

  98. void r100_cp_fini(struct radeon_device *rdev);
    99. 

  99. int r100_pci_gart_init(struct radeon_device *rdev);
    100. 

  100. void r100_pci_gart_fini(struct radeon_device *rdev);
    101. 

  101. int r100_pci_gart_enable(struct radeon_device *rdev);
    102. 

  102. void r100_pci_gart_disable(struct radeon_device *rdev);
    103. 

  103. int r100_debugfs_mc_info_init(struct radeon_device *rdev);
    104. 

  104. int r100_gui_wait_for_idle(struct radeon_device *rdev);
    105. 

  105. void r100_ib_fini(struct radeon_device *rdev);
    106. 

  106. int r100_ib_init(struct radeon_device *rdev);
    107. 

  107. void r100_irq_disable(struct radeon_device *rdev);
    108. 

  108. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
    109. 

  109. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
    110. 

  110. void r100_vram_init_sizes(struct radeon_device *rdev);
    111. 

  111. int r100_cp_reset(struct radeon_device *rdev);
    112. 

  112. void r100_vga_render_disable(struct radeon_device *rdev);
    113. 

  113. void r100_restore_sanity(struct radeon_device *rdev);
    114. 

  114. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
    115. 

  115. 					 struct radeon_cs_packet *pkt,
    116. 

  116. 					 struct radeon_bo *robj);
    117. 

  117. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
    118. 

  118. 			  struct radeon_cs_packet *pkt,
    119. 

  119. 			  const unsigned *auth, unsigned n,
    120. 

  120. 			  radeon_packet0_check_t check);
    121. 

  121. int r100_cs_packet_parse(struct radeon_cs_parser *p,
    122. 

  122. 			 struct radeon_cs_packet *pkt,
    123. 

  123. 			 unsigned idx);
    124. 

  124. void r100_enable_bm(struct radeon_device *rdev);
    125. 

  125. void r100_set_common_regs(struct radeon_device *rdev);
    126. 

  126. void r100_bm_disable(struct radeon_device *rdev);
    127. 

  127. extern bool r100_gui_idle(struct radeon_device *rdev);
    128. 

  128. extern void r100_pm_misc(struct radeon_device *rdev);
    129. 

  129. extern void r100_pm_prepare(struct radeon_device *rdev);
    130. 

  130. extern void r100_pm_finish(struct radeon_device *rdev);
    131. 

  131. extern void r100_pm_init_profile(struct radeon_device *rdev);
    132. 

  132. extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
    133. 

  133. extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
    134. 

  134. extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    135. 

  135. extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
    136. 

  136. 

  137. /*
    138. 

  138.  * r200,rv250,rs300,rv280
    139. 

  139.  */
    140. 

  140. extern int r200_copy_dma(struct radeon_device *rdev,
    141. 

  141. 			uint64_t src_offset,
    142. 

  142. 			uint64_t dst_offset,
    143. 

  143. 			unsigned num_pages,
    144. 

  144. 			 struct radeon_fence *fence);
    145. 

  145. 

  146. /*
    147. 

  147.  * r300,r350,rv350,rv380
    148. 

  148.  */
    149. 

  149. extern int r300_init(struct radeon_device *rdev);
    150. 

  150. extern void r300_fini(struct radeon_device *rdev);
    151. 

  151. extern int r300_suspend(struct radeon_device *rdev);
    152. 

  152. extern int r300_resume(struct radeon_device *rdev);
    153. 

  153. extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
    154. 

  154. extern int r300_asic_reset(struct radeon_device *rdev);
    155. 

  155. extern void r300_ring_start(struct radeon_device *rdev);
    156. 

  156. extern void r300_fence_ring_emit(struct radeon_device *rdev,
    157. 

  157. 				struct radeon_fence *fence);
    158. 

  158. extern int r300_cs_parse(struct radeon_cs_parser *p);
    159. 

  159. extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
    160. 

  160. extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    161. 

  161. extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
    162. 

  162. extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    163. 

  163. extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
    164. 

  164. extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
    165. 

  165. 

  166. /*
    167. 

  167.  * r420,r423,rv410
    168. 

  168.  */
    169. 

  169. extern int r420_init(struct radeon_device *rdev);
    170. 

  170. extern void r420_fini(struct radeon_device *rdev);
    171. 

  171. extern int r420_suspend(struct radeon_device *rdev);
    172. 

  172. extern int r420_resume(struct radeon_device *rdev);
    173. 

  173. extern void r420_pm_init_profile(struct radeon_device *rdev);
    174. 

  174. 

  175. /*
    176. 

  176.  * rs400,rs480
    177. 

  177.  */
    178. 

  178. extern int rs400_init(struct radeon_device *rdev);
    179. 

  179. extern void rs400_fini(struct radeon_device *rdev);
    180. 

  180. extern int rs400_suspend(struct radeon_device *rdev);
    181. 

  181. extern int rs400_resume(struct radeon_device *rdev);
    182. 

  182. void rs400_gart_tlb_flush(struct radeon_device *rdev);
    183. 

  183. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    184. 

  184. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    185. 

  185. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    186. 

  186. 

  187. /*
    188. 

  188.  * rs600.
    189. 

  189.  */
    190. 

  190. extern int rs600_asic_reset(struct radeon_device *rdev);
    191. 

  191. extern int rs600_init(struct radeon_device *rdev);
    192. 

  192. extern void rs600_fini(struct radeon_device *rdev);
    193. 

  193. extern int rs600_suspend(struct radeon_device *rdev);
    194. 

  194. extern int rs600_resume(struct radeon_device *rdev);
    195. 

  195. int rs600_irq_set(struct radeon_device *rdev);
    196. 

  196. int rs600_irq_process(struct radeon_device *rdev);
    197. 

  197. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
    198. 

  198. void rs600_gart_tlb_flush(struct radeon_device *rdev);
    199. 

  199. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    200. 

  200. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    201. 

  201. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    202. 

  202. void rs600_bandwidth_update(struct radeon_device *rdev);
    203. 

  203. void rs600_hpd_init(struct radeon_device *rdev);
    204. 

  204. void rs600_hpd_fini(struct radeon_device *rdev);
    205. 

  205. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    206. 

  206. void rs600_hpd_set_polarity(struct radeon_device *rdev,
    207. 

  207. 			    enum radeon_hpd_id hpd);
    208. 

  208. extern void rs600_pm_misc(struct radeon_device *rdev);
    209. 

  209. extern void rs600_pm_prepare(struct radeon_device *rdev);
    210. 

  210. extern void rs600_pm_finish(struct radeon_device *rdev);
    211. 

  211. extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
    212. 

  212. extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    213. 

  213. extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
    214. 

  214. 

  215. /*
    216. 

  216.  * rs690,rs740
    217. 

  217.  */
    218. 

  218. int rs690_init(struct radeon_device *rdev);
    219. 

  219. void rs690_fini(struct radeon_device *rdev);
    220. 

  220. int rs690_resume(struct radeon_device *rdev);
    221. 

  221. int rs690_suspend(struct radeon_device *rdev);
    222. 

  222. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    223. 

  223. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    224. 

  224. void rs690_bandwidth_update(struct radeon_device *rdev);
    225. 

  225. 

  226. /*
    227. 

  227.  * rv515
    228. 

  228.  */
    229. 

  229. int rv515_init(struct radeon_device *rdev);
    230. 

  230. void rv515_fini(struct radeon_device *rdev);
    231. 

  231. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    232. 

  232. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    233. 

  233. void rv515_ring_start(struct radeon_device *rdev);
    234. 

  234. uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
    235. 

  235. void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    236. 

  236. void rv515_bandwidth_update(struct radeon_device *rdev);
    237. 

  237. int rv515_resume(struct radeon_device *rdev);
    238. 

  238. int rv515_suspend(struct radeon_device *rdev);
    239. 

  239. 

  240. /*
    241. 

  241.  * r520,rv530,rv560,rv570,r580
    242. 

  242.  */
    243. 

  243. int r520_init(struct radeon_device *rdev);
    244. 

  244. int r520_resume(struct radeon_device *rdev);
    245. 

  245. 

  246. /*
    247. 

  247.  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
    248. 

  248.  */
    249. 

  249. int r600_init(struct radeon_device *rdev);
    250. 

  250. void r600_fini(struct radeon_device *rdev);
    251. 

  251. int r600_suspend(struct radeon_device *rdev);
    252. 

  252. int r600_resume(struct radeon_device *rdev);
    253. 

  253. void r600_vga_set_state(struct radeon_device *rdev, bool state);
    254. 

  254. int r600_wb_init(struct radeon_device *rdev);
    255. 

  255. void r600_wb_fini(struct radeon_device *rdev);
    256. 

  256. void r600_cp_commit(struct radeon_device *rdev);
    257. 

  257. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
    258. 

  258. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
    259. 

  259. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    260. 

  260. int r600_cs_parse(struct radeon_cs_parser *p);
    261. 

  261. void r600_fence_ring_emit(struct radeon_device *rdev,
    262. 

  262. 			  struct radeon_fence *fence);
    263. 

  263. int r600_irq_process(struct radeon_device *rdev);
    264. 

  264. int r600_irq_set(struct radeon_device *rdev);
    265. 

  265. bool r600_gpu_is_lockup(struct radeon_device *rdev);
    266. 

  266. int r600_asic_reset(struct radeon_device *rdev);
    267. 

  267. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
    268. 

  268. 			 uint32_t tiling_flags, uint32_t pitch,
    269. 

  269. 			 uint32_t offset, uint32_t obj_size);
    270. 

  270. void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
    271. 

  271. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    272. 

  272. int r600_ring_test(struct radeon_device *rdev);
    273. 

  273. int r600_copy_blit(struct radeon_device *rdev,
    274. 

  274. 		   uint64_t src_offset, uint64_t dst_offset,
    275. 

  275. 		   unsigned num_pages, struct radeon_fence *fence);
    276. 

  276. void r600_hpd_init(struct radeon_device *rdev);
    277. 

  277. void r600_hpd_fini(struct radeon_device *rdev);
    278. 

  278. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    279. 

  279. void r600_hpd_set_polarity(struct radeon_device *rdev,
    280. 

  280. 			   enum radeon_hpd_id hpd);
    281. 

  281. extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
    282. 

  282. extern bool r600_gui_idle(struct radeon_device *rdev);
    283. 

  283. extern void r600_pm_misc(struct radeon_device *rdev);
    284. 

  284. extern void r600_pm_init_profile(struct radeon_device *rdev);
    285. 

  285. extern void rs780_pm_init_profile(struct radeon_device *rdev);
    286. 

  286. extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
    287. 

  287. 

  288. /*
    289. 

  289.  * rv770,rv730,rv710,rv740
    290. 

  290.  */
    291. 

  291. int rv770_init(struct radeon_device *rdev);
    292. 

  292. void rv770_fini(struct radeon_device *rdev);
    293. 

  293. int rv770_suspend(struct radeon_device *rdev);
    294. 

  294. int rv770_resume(struct radeon_device *rdev);
    295. 

  295. extern void rv770_pm_misc(struct radeon_device *rdev);
    296. 

  296. extern u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    297. 

  297. 

  298. /*
    299. 

  299.  * evergreen
    300. 

  300.  */
    301. 

  301. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
    302. 

  302. int evergreen_init(struct radeon_device *rdev);
    303. 

  303. void evergreen_fini(struct radeon_device *rdev);
    304. 

  304. int evergreen_suspend(struct radeon_device *rdev);
    305. 

  305. int evergreen_resume(struct radeon_device *rdev);
    306. 

  306. bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
    307. 

  307. int evergreen_asic_reset(struct radeon_device *rdev);
    308. 

  308. void evergreen_bandwidth_update(struct radeon_device *rdev);
    309. 

  309. int evergreen_copy_blit(struct radeon_device *rdev,
    310. 

  310. 			uint64_t src_offset, uint64_t dst_offset,
    311. 

  311. 			unsigned num_pages, struct radeon_fence *fence);
    312. 

  312. void evergreen_hpd_init(struct radeon_device *rdev);
    313. 

  313. void evergreen_hpd_fini(struct radeon_device *rdev);
    314. 

  314. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    315. 

  315. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
    316. 

  316. 				enum radeon_hpd_id hpd);
    317. 

  317. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
    318. 

  318. int evergreen_irq_set(struct radeon_device *rdev);
    319. 

  319. int evergreen_irq_process(struct radeon_device *rdev);
    320. 

  320. extern int evergreen_cs_parse(struct radeon_cs_parser *p);
    321. 

  321. extern void evergreen_pm_misc(struct radeon_device *rdev);
    322. 

  322. extern void evergreen_pm_prepare(struct radeon_device *rdev);
    323. 

  323. extern void evergreen_pm_finish(struct radeon_device *rdev);
    324. 

  324. extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
    325. 

  325. extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    326. 

  326. extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
    327. 

  327. 

  328. #endif
    329.