nv50_evo.c 8.3 KB

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  1. /*
  2. * Copyright 2010 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. #include "nouveau_dma.h"
  27. #include "nouveau_ramht.h"
  28. static void
  29. nv50_evo_channel_del(struct nouveau_channel **pevo)
  30. {
  31. struct drm_nouveau_private *dev_priv;
  32. struct nouveau_channel *evo = *pevo;
  33. if (!evo)
  34. return;
  35. *pevo = NULL;
  36. dev_priv = evo->dev->dev_private;
  37. dev_priv->evo_alloc &= ~(1 << evo->id);
  38. nouveau_gpuobj_channel_takedown(evo);
  39. nouveau_bo_unmap(evo->pushbuf_bo);
  40. nouveau_bo_ref(NULL, &evo->pushbuf_bo);
  41. if (evo->user)
  42. iounmap(evo->user);
  43. kfree(evo);
  44. }
  45. int
  46. nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
  47. u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
  48. {
  49. struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  50. struct drm_device *dev = evo->dev;
  51. struct nouveau_gpuobj *obj = NULL;
  52. int ret;
  53. ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
  54. if (ret)
  55. return ret;
  56. obj->engine = NVOBJ_ENGINE_DISPLAY;
  57. nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  58. nv_wo32(obj, 4, limit);
  59. nv_wo32(obj, 8, offset);
  60. nv_wo32(obj, 12, 0x00000000);
  61. nv_wo32(obj, 16, 0x00000000);
  62. if (dev_priv->card_type < NV_C0)
  63. nv_wo32(obj, 20, 0x00010000);
  64. else
  65. nv_wo32(obj, 20, 0x00020000);
  66. dev_priv->engine.instmem.flush(dev);
  67. ret = nouveau_ramht_insert(evo, name, obj);
  68. nouveau_gpuobj_ref(NULL, &obj);
  69. if (ret) {
  70. return ret;
  71. }
  72. return 0;
  73. }
  74. static int
  75. nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
  76. {
  77. struct drm_nouveau_private *dev_priv = dev->dev_private;
  78. struct nouveau_channel *evo;
  79. int ret;
  80. evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  81. if (!evo)
  82. return -ENOMEM;
  83. *pevo = evo;
  84. for (evo->id = 0; evo->id < 5; evo->id++) {
  85. if (dev_priv->evo_alloc & (1 << evo->id))
  86. continue;
  87. dev_priv->evo_alloc |= (1 << evo->id);
  88. break;
  89. }
  90. if (evo->id == 5) {
  91. kfree(evo);
  92. return -ENODEV;
  93. }
  94. evo->dev = dev;
  95. evo->user_get = 4;
  96. evo->user_put = 0;
  97. ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
  98. false, true, &evo->pushbuf_bo);
  99. if (ret == 0)
  100. ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
  101. if (ret) {
  102. NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
  103. nv50_evo_channel_del(pevo);
  104. return ret;
  105. }
  106. ret = nouveau_bo_map(evo->pushbuf_bo);
  107. if (ret) {
  108. NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
  109. nv50_evo_channel_del(pevo);
  110. return ret;
  111. }
  112. evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
  113. NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
  114. if (!evo->user) {
  115. NV_ERROR(dev, "Error mapping EVO control regs.\n");
  116. nv50_evo_channel_del(pevo);
  117. return -ENOMEM;
  118. }
  119. /* bind primary evo channel's ramht to the channel */
  120. if (dev_priv->evo && evo != dev_priv->evo)
  121. nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
  122. return 0;
  123. }
  124. static int
  125. nv50_evo_channel_init(struct nouveau_channel *evo)
  126. {
  127. struct drm_device *dev = evo->dev;
  128. int id = evo->id, ret, i;
  129. u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
  130. u32 tmp;
  131. tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
  132. if ((tmp & 0x009f0000) == 0x00020000)
  133. nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
  134. tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
  135. if ((tmp & 0x003f0000) == 0x00030000)
  136. nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
  137. /* initialise fifo */
  138. nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
  139. NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
  140. NV50_PDISPLAY_EVO_DMA_CB_VALID);
  141. nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
  142. nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
  143. nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
  144. NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
  145. nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
  146. nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
  147. NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
  148. if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
  149. NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
  150. nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
  151. return -EBUSY;
  152. }
  153. /* enable error reporting on the channel */
  154. nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
  155. evo->dma.max = (4096/4) - 2;
  156. evo->dma.put = 0;
  157. evo->dma.cur = evo->dma.put;
  158. evo->dma.free = evo->dma.max - evo->dma.cur;
  159. ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
  160. if (ret)
  161. return ret;
  162. for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
  163. OUT_RING(evo, 0);
  164. return 0;
  165. }
  166. static void
  167. nv50_evo_channel_fini(struct nouveau_channel *evo)
  168. {
  169. struct drm_device *dev = evo->dev;
  170. int id = evo->id;
  171. nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
  172. nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
  173. nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
  174. nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
  175. if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
  176. NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
  177. nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
  178. }
  179. }
  180. static int
  181. nv50_evo_create(struct drm_device *dev)
  182. {
  183. struct drm_nouveau_private *dev_priv = dev->dev_private;
  184. struct nouveau_gpuobj *ramht = NULL;
  185. struct nouveau_channel *evo;
  186. int ret;
  187. /* create primary evo channel, the one we use for modesetting
  188. * purporses
  189. */
  190. ret = nv50_evo_channel_new(dev, &dev_priv->evo);
  191. if (ret)
  192. return ret;
  193. evo = dev_priv->evo;
  194. /* setup object management on it, any other evo channel will
  195. * use this also as there's no per-channel support on the
  196. * hardware
  197. */
  198. ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
  199. NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
  200. if (ret) {
  201. NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
  202. nv50_evo_channel_del(&dev_priv->evo);
  203. return ret;
  204. }
  205. ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
  206. if (ret) {
  207. NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
  208. nv50_evo_channel_del(&dev_priv->evo);
  209. return ret;
  210. }
  211. ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
  212. if (ret) {
  213. NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
  214. nv50_evo_channel_del(&dev_priv->evo);
  215. return ret;
  216. }
  217. ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
  218. nouveau_gpuobj_ref(NULL, &ramht);
  219. if (ret) {
  220. nv50_evo_channel_del(&dev_priv->evo);
  221. return ret;
  222. }
  223. /* create some default objects for the scanout memtypes we support */
  224. if (dev_priv->chipset != 0x50) {
  225. ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
  226. 0, 0xffffffff);
  227. if (ret) {
  228. nv50_evo_channel_del(&dev_priv->evo);
  229. return ret;
  230. }
  231. ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
  232. 0, 0xffffffff);
  233. if (ret) {
  234. nv50_evo_channel_del(&dev_priv->evo);
  235. return ret;
  236. }
  237. }
  238. ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
  239. 0, dev_priv->vram_size);
  240. if (ret) {
  241. nv50_evo_channel_del(&dev_priv->evo);
  242. return ret;
  243. }
  244. return 0;
  245. }
  246. int
  247. nv50_evo_init(struct drm_device *dev)
  248. {
  249. struct drm_nouveau_private *dev_priv = dev->dev_private;
  250. int ret;
  251. if (!dev_priv->evo) {
  252. ret = nv50_evo_create(dev);
  253. if (ret)
  254. return ret;
  255. }
  256. return nv50_evo_channel_init(dev_priv->evo);
  257. }
  258. void
  259. nv50_evo_fini(struct drm_device *dev)
  260. {
  261. struct drm_nouveau_private *dev_priv = dev->dev_private;
  262. if (dev_priv->evo) {
  263. nv50_evo_channel_fini(dev_priv->evo);
  264. nv50_evo_channel_del(&dev_priv->evo);
  265. }
  266. }