omap-serial.h 3.0 KB

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  1. /*
  2. * Driver for OMAP-UART controller.
  3. * Based on drivers/serial/8250.c
  4. *
  5. * Copyright (C) 2010 Texas Instruments.
  6. *
  7. * Authors:
  8. * Govindraj R <govindraj.raja@ti.com>
  9. * Thara Gopinath <thara@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. */
  16. #ifndef __OMAP_SERIAL_H__
  17. #define __OMAP_SERIAL_H__
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <plat/mux.h>
  21. #define DRIVER_NAME "omap-hsuart"
  22. /*
  23. * Use tty device name as ttyO, [O -> OMAP]
  24. * in bootargs we specify as console=ttyO0 if uart1
  25. * is used as console uart.
  26. */
  27. #define OMAP_SERIAL_NAME "ttyO"
  28. #define OMAP_MDR1_DISABLE 0x07
  29. #define OMAP_MDR1_MODE13X 0x03
  30. #define OMAP_MDR1_MODE16X 0x00
  31. #define OMAP_MODE13X_SPEED 230400
  32. /*
  33. * LCR = 0XBF: Switch to Configuration Mode B.
  34. * In configuration mode b allow access
  35. * to EFR,DLL,DLH.
  36. * Reference OMAP TRM Chapter 17
  37. * Section: 1.4.3 Mode Selection
  38. */
  39. #define OMAP_UART_LCR_CONF_MDB 0XBF
  40. /* WER = 0x7F
  41. * Enable module level wakeup in WER reg
  42. */
  43. #define OMAP_UART_WER_MOD_WKUP 0X7F
  44. /* Enable XON/XOFF flow control on output */
  45. #define OMAP_UART_SW_TX 0x04
  46. /* Enable XON/XOFF flow control on input */
  47. #define OMAP_UART_SW_RX 0x04
  48. #define OMAP_UART_SYSC_RESET 0X07
  49. #define OMAP_UART_TCR_TRIG 0X0F
  50. #define OMAP_UART_SW_CLR 0XF0
  51. #define OMAP_UART_FIFO_CLR 0X06
  52. #define OMAP_UART_DMA_CH_FREE -1
  53. #define RX_TIMEOUT (3 * HZ)
  54. #define OMAP_MAX_HSUART_PORTS 4
  55. #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
  56. struct omap_uart_port_info {
  57. bool dma_enabled; /* To specify DMA Mode */
  58. unsigned int uartclk; /* UART clock rate */
  59. void __iomem *membase; /* ioremap cookie or NULL */
  60. resource_size_t mapbase; /* resource base */
  61. unsigned long irqflags; /* request_irq flags */
  62. upf_t flags; /* UPF_* flags */
  63. };
  64. struct uart_omap_dma {
  65. u8 uart_dma_tx;
  66. u8 uart_dma_rx;
  67. int rx_dma_channel;
  68. int tx_dma_channel;
  69. dma_addr_t rx_buf_dma_phys;
  70. dma_addr_t tx_buf_dma_phys;
  71. unsigned int uart_base;
  72. /*
  73. * Buffer for rx dma.It is not required for tx because the buffer
  74. * comes from port structure.
  75. */
  76. unsigned char *rx_buf;
  77. unsigned int prev_rx_dma_pos;
  78. int tx_buf_size;
  79. int tx_dma_used;
  80. int rx_dma_used;
  81. spinlock_t tx_lock;
  82. spinlock_t rx_lock;
  83. /* timer to poll activity on rx dma */
  84. struct timer_list rx_timer;
  85. int rx_buf_size;
  86. int rx_timeout;
  87. };
  88. struct uart_omap_port {
  89. struct uart_port port;
  90. struct uart_omap_dma uart_dma;
  91. struct platform_device *pdev;
  92. unsigned char ier;
  93. unsigned char lcr;
  94. unsigned char mcr;
  95. unsigned char fcr;
  96. unsigned char efr;
  97. int use_dma;
  98. /*
  99. * Some bits in registers are cleared on a read, so they must
  100. * be saved whenever the register is read but the bits will not
  101. * be immediately processed.
  102. */
  103. unsigned int lsr_break_flag;
  104. unsigned char msr_saved_flags;
  105. char name[20];
  106. unsigned long port_activity;
  107. };
  108. #endif /* __OMAP_SERIAL_H__ */