stv090x.c 124 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/mutex.h>
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #include "stv6110x.h" /* for demodulator internal modes */
  25. #include "stv090x_reg.h"
  26. #include "stv090x.h"
  27. #include "stv090x_priv.h"
  28. static unsigned int verbose;
  29. module_param(verbose, int, 0644);
  30. /* internal params node */
  31. struct stv090x_dev {
  32. /* pointer for internal params, one for each pair of demods */
  33. struct stv090x_internal *internal;
  34. struct stv090x_dev *next_dev;
  35. };
  36. /* first internal params */
  37. static struct stv090x_dev *stv090x_first_dev;
  38. /* find chip by i2c adapter and i2c address */
  39. static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
  40. u8 i2c_addr)
  41. {
  42. struct stv090x_dev *temp_dev = stv090x_first_dev;
  43. /*
  44. Search of the last stv0900 chip or
  45. find it by i2c adapter and i2c address */
  46. while ((temp_dev != NULL) &&
  47. ((temp_dev->internal->i2c_adap != i2c_adap) ||
  48. (temp_dev->internal->i2c_addr != i2c_addr))) {
  49. temp_dev = temp_dev->next_dev;
  50. }
  51. return temp_dev;
  52. }
  53. /* deallocating chip */
  54. static void remove_dev(struct stv090x_internal *internal)
  55. {
  56. struct stv090x_dev *prev_dev = stv090x_first_dev;
  57. struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
  58. internal->i2c_addr);
  59. if (del_dev != NULL) {
  60. if (del_dev == stv090x_first_dev) {
  61. stv090x_first_dev = del_dev->next_dev;
  62. } else {
  63. while (prev_dev->next_dev != del_dev)
  64. prev_dev = prev_dev->next_dev;
  65. prev_dev->next_dev = del_dev->next_dev;
  66. }
  67. kfree(del_dev);
  68. }
  69. }
  70. /* allocating new chip */
  71. static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
  72. {
  73. struct stv090x_dev *new_dev;
  74. struct stv090x_dev *temp_dev;
  75. new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
  76. if (new_dev != NULL) {
  77. new_dev->internal = internal;
  78. new_dev->next_dev = NULL;
  79. /* append to list */
  80. if (stv090x_first_dev == NULL) {
  81. stv090x_first_dev = new_dev;
  82. } else {
  83. temp_dev = stv090x_first_dev;
  84. while (temp_dev->next_dev != NULL)
  85. temp_dev = temp_dev->next_dev;
  86. temp_dev->next_dev = new_dev;
  87. }
  88. }
  89. return new_dev;
  90. }
  91. /* DVBS1 and DSS C/N Lookup table */
  92. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  93. { 0, 8917 }, /* 0.0dB */
  94. { 5, 8801 }, /* 0.5dB */
  95. { 10, 8667 }, /* 1.0dB */
  96. { 15, 8522 }, /* 1.5dB */
  97. { 20, 8355 }, /* 2.0dB */
  98. { 25, 8175 }, /* 2.5dB */
  99. { 30, 7979 }, /* 3.0dB */
  100. { 35, 7763 }, /* 3.5dB */
  101. { 40, 7530 }, /* 4.0dB */
  102. { 45, 7282 }, /* 4.5dB */
  103. { 50, 7026 }, /* 5.0dB */
  104. { 55, 6781 }, /* 5.5dB */
  105. { 60, 6514 }, /* 6.0dB */
  106. { 65, 6241 }, /* 6.5dB */
  107. { 70, 5965 }, /* 7.0dB */
  108. { 75, 5690 }, /* 7.5dB */
  109. { 80, 5424 }, /* 8.0dB */
  110. { 85, 5161 }, /* 8.5dB */
  111. { 90, 4902 }, /* 9.0dB */
  112. { 95, 4654 }, /* 9.5dB */
  113. { 100, 4417 }, /* 10.0dB */
  114. { 105, 4186 }, /* 10.5dB */
  115. { 110, 3968 }, /* 11.0dB */
  116. { 115, 3757 }, /* 11.5dB */
  117. { 120, 3558 }, /* 12.0dB */
  118. { 125, 3366 }, /* 12.5dB */
  119. { 130, 3185 }, /* 13.0dB */
  120. { 135, 3012 }, /* 13.5dB */
  121. { 140, 2850 }, /* 14.0dB */
  122. { 145, 2698 }, /* 14.5dB */
  123. { 150, 2550 }, /* 15.0dB */
  124. { 160, 2283 }, /* 16.0dB */
  125. { 170, 2042 }, /* 17.0dB */
  126. { 180, 1827 }, /* 18.0dB */
  127. { 190, 1636 }, /* 19.0dB */
  128. { 200, 1466 }, /* 20.0dB */
  129. { 210, 1315 }, /* 21.0dB */
  130. { 220, 1181 }, /* 22.0dB */
  131. { 230, 1064 }, /* 23.0dB */
  132. { 240, 960 }, /* 24.0dB */
  133. { 250, 869 }, /* 25.0dB */
  134. { 260, 792 }, /* 26.0dB */
  135. { 270, 724 }, /* 27.0dB */
  136. { 280, 665 }, /* 28.0dB */
  137. { 290, 616 }, /* 29.0dB */
  138. { 300, 573 }, /* 30.0dB */
  139. { 310, 537 }, /* 31.0dB */
  140. { 320, 507 }, /* 32.0dB */
  141. { 330, 483 }, /* 33.0dB */
  142. { 400, 398 }, /* 40.0dB */
  143. { 450, 381 }, /* 45.0dB */
  144. { 500, 377 } /* 50.0dB */
  145. };
  146. /* DVBS2 C/N Lookup table */
  147. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  148. { -30, 13348 }, /* -3.0dB */
  149. { -20, 12640 }, /* -2d.0B */
  150. { -10, 11883 }, /* -1.0dB */
  151. { 0, 11101 }, /* -0.0dB */
  152. { 5, 10718 }, /* 0.5dB */
  153. { 10, 10339 }, /* 1.0dB */
  154. { 15, 9947 }, /* 1.5dB */
  155. { 20, 9552 }, /* 2.0dB */
  156. { 25, 9183 }, /* 2.5dB */
  157. { 30, 8799 }, /* 3.0dB */
  158. { 35, 8422 }, /* 3.5dB */
  159. { 40, 8062 }, /* 4.0dB */
  160. { 45, 7707 }, /* 4.5dB */
  161. { 50, 7353 }, /* 5.0dB */
  162. { 55, 7025 }, /* 5.5dB */
  163. { 60, 6684 }, /* 6.0dB */
  164. { 65, 6331 }, /* 6.5dB */
  165. { 70, 6036 }, /* 7.0dB */
  166. { 75, 5727 }, /* 7.5dB */
  167. { 80, 5437 }, /* 8.0dB */
  168. { 85, 5164 }, /* 8.5dB */
  169. { 90, 4902 }, /* 9.0dB */
  170. { 95, 4653 }, /* 9.5dB */
  171. { 100, 4408 }, /* 10.0dB */
  172. { 105, 4187 }, /* 10.5dB */
  173. { 110, 3961 }, /* 11.0dB */
  174. { 115, 3751 }, /* 11.5dB */
  175. { 120, 3558 }, /* 12.0dB */
  176. { 125, 3368 }, /* 12.5dB */
  177. { 130, 3191 }, /* 13.0dB */
  178. { 135, 3017 }, /* 13.5dB */
  179. { 140, 2862 }, /* 14.0dB */
  180. { 145, 2710 }, /* 14.5dB */
  181. { 150, 2565 }, /* 15.0dB */
  182. { 160, 2300 }, /* 16.0dB */
  183. { 170, 2058 }, /* 17.0dB */
  184. { 180, 1849 }, /* 18.0dB */
  185. { 190, 1663 }, /* 19.0dB */
  186. { 200, 1495 }, /* 20.0dB */
  187. { 210, 1349 }, /* 21.0dB */
  188. { 220, 1222 }, /* 22.0dB */
  189. { 230, 1110 }, /* 23.0dB */
  190. { 240, 1011 }, /* 24.0dB */
  191. { 250, 925 }, /* 25.0dB */
  192. { 260, 853 }, /* 26.0dB */
  193. { 270, 789 }, /* 27.0dB */
  194. { 280, 734 }, /* 28.0dB */
  195. { 290, 690 }, /* 29.0dB */
  196. { 300, 650 }, /* 30.0dB */
  197. { 310, 619 }, /* 31.0dB */
  198. { 320, 593 }, /* 32.0dB */
  199. { 330, 571 }, /* 33.0dB */
  200. { 400, 498 }, /* 40.0dB */
  201. { 450, 484 }, /* 45.0dB */
  202. { 500, 481 } /* 50.0dB */
  203. };
  204. /* RF level C/N lookup table */
  205. static const struct stv090x_tab stv090x_rf_tab[] = {
  206. { -5, 0xcaa1 }, /* -5dBm */
  207. { -10, 0xc229 }, /* -10dBm */
  208. { -15, 0xbb08 }, /* -15dBm */
  209. { -20, 0xb4bc }, /* -20dBm */
  210. { -25, 0xad5a }, /* -25dBm */
  211. { -30, 0xa298 }, /* -30dBm */
  212. { -35, 0x98a8 }, /* -35dBm */
  213. { -40, 0x8389 }, /* -40dBm */
  214. { -45, 0x59be }, /* -45dBm */
  215. { -50, 0x3a14 }, /* -50dBm */
  216. { -55, 0x2d11 }, /* -55dBm */
  217. { -60, 0x210d }, /* -60dBm */
  218. { -65, 0xa14f }, /* -65dBm */
  219. { -70, 0x07aa } /* -70dBm */
  220. };
  221. static struct stv090x_reg stv0900_initval[] = {
  222. { STV090x_OUTCFG, 0x00 },
  223. { STV090x_MODECFG, 0xff },
  224. { STV090x_AGCRF1CFG, 0x11 },
  225. { STV090x_AGCRF2CFG, 0x13 },
  226. { STV090x_TSGENERAL1X, 0x14 },
  227. { STV090x_TSTTNR2, 0x21 },
  228. { STV090x_TSTTNR4, 0x21 },
  229. { STV090x_P2_DISTXCTL, 0x22 },
  230. { STV090x_P2_F22TX, 0xc0 },
  231. { STV090x_P2_F22RX, 0xc0 },
  232. { STV090x_P2_DISRXCTL, 0x00 },
  233. { STV090x_P2_DMDCFGMD, 0xF9 },
  234. { STV090x_P2_DEMOD, 0x08 },
  235. { STV090x_P2_DMDCFG3, 0xc4 },
  236. { STV090x_P2_CARFREQ, 0xed },
  237. { STV090x_P2_LDT, 0xd0 },
  238. { STV090x_P2_LDT2, 0xb8 },
  239. { STV090x_P2_TMGCFG, 0xd2 },
  240. { STV090x_P2_TMGTHRISE, 0x20 },
  241. { STV090x_P1_TMGCFG, 0xd2 },
  242. { STV090x_P2_TMGTHFALL, 0x00 },
  243. { STV090x_P2_FECSPY, 0x88 },
  244. { STV090x_P2_FSPYDATA, 0x3a },
  245. { STV090x_P2_FBERCPT4, 0x00 },
  246. { STV090x_P2_FSPYBER, 0x10 },
  247. { STV090x_P2_ERRCTRL1, 0x35 },
  248. { STV090x_P2_ERRCTRL2, 0xc1 },
  249. { STV090x_P2_CFRICFG, 0xf8 },
  250. { STV090x_P2_NOSCFG, 0x1c },
  251. { STV090x_P2_DMDTOM, 0x20 },
  252. { STV090x_P2_CORRELMANT, 0x70 },
  253. { STV090x_P2_CORRELABS, 0x88 },
  254. { STV090x_P2_AGC2O, 0x5b },
  255. { STV090x_P2_AGC2REF, 0x38 },
  256. { STV090x_P2_CARCFG, 0xe4 },
  257. { STV090x_P2_ACLC, 0x1A },
  258. { STV090x_P2_BCLC, 0x09 },
  259. { STV090x_P2_CARHDR, 0x08 },
  260. { STV090x_P2_KREFTMG, 0xc1 },
  261. { STV090x_P2_SFRUPRATIO, 0xf0 },
  262. { STV090x_P2_SFRLOWRATIO, 0x70 },
  263. { STV090x_P2_SFRSTEP, 0x58 },
  264. { STV090x_P2_TMGCFG2, 0x01 },
  265. { STV090x_P2_CAR2CFG, 0x26 },
  266. { STV090x_P2_BCLC2S2Q, 0x86 },
  267. { STV090x_P2_BCLC2S28, 0x86 },
  268. { STV090x_P2_SMAPCOEF7, 0x77 },
  269. { STV090x_P2_SMAPCOEF6, 0x85 },
  270. { STV090x_P2_SMAPCOEF5, 0x77 },
  271. { STV090x_P2_TSCFGL, 0x20 },
  272. { STV090x_P2_DMDCFG2, 0x3b },
  273. { STV090x_P2_MODCODLST0, 0xff },
  274. { STV090x_P2_MODCODLST1, 0xff },
  275. { STV090x_P2_MODCODLST2, 0xff },
  276. { STV090x_P2_MODCODLST3, 0xff },
  277. { STV090x_P2_MODCODLST4, 0xff },
  278. { STV090x_P2_MODCODLST5, 0xff },
  279. { STV090x_P2_MODCODLST6, 0xff },
  280. { STV090x_P2_MODCODLST7, 0xcc },
  281. { STV090x_P2_MODCODLST8, 0xcc },
  282. { STV090x_P2_MODCODLST9, 0xcc },
  283. { STV090x_P2_MODCODLSTA, 0xcc },
  284. { STV090x_P2_MODCODLSTB, 0xcc },
  285. { STV090x_P2_MODCODLSTC, 0xcc },
  286. { STV090x_P2_MODCODLSTD, 0xcc },
  287. { STV090x_P2_MODCODLSTE, 0xcc },
  288. { STV090x_P2_MODCODLSTF, 0xcf },
  289. { STV090x_P1_DISTXCTL, 0x22 },
  290. { STV090x_P1_F22TX, 0xc0 },
  291. { STV090x_P1_F22RX, 0xc0 },
  292. { STV090x_P1_DISRXCTL, 0x00 },
  293. { STV090x_P1_DMDCFGMD, 0xf9 },
  294. { STV090x_P1_DEMOD, 0x08 },
  295. { STV090x_P1_DMDCFG3, 0xc4 },
  296. { STV090x_P1_DMDTOM, 0x20 },
  297. { STV090x_P1_CARFREQ, 0xed },
  298. { STV090x_P1_LDT, 0xd0 },
  299. { STV090x_P1_LDT2, 0xb8 },
  300. { STV090x_P1_TMGCFG, 0xd2 },
  301. { STV090x_P1_TMGTHRISE, 0x20 },
  302. { STV090x_P1_TMGTHFALL, 0x00 },
  303. { STV090x_P1_SFRUPRATIO, 0xf0 },
  304. { STV090x_P1_SFRLOWRATIO, 0x70 },
  305. { STV090x_P1_TSCFGL, 0x20 },
  306. { STV090x_P1_FECSPY, 0x88 },
  307. { STV090x_P1_FSPYDATA, 0x3a },
  308. { STV090x_P1_FBERCPT4, 0x00 },
  309. { STV090x_P1_FSPYBER, 0x10 },
  310. { STV090x_P1_ERRCTRL1, 0x35 },
  311. { STV090x_P1_ERRCTRL2, 0xc1 },
  312. { STV090x_P1_CFRICFG, 0xf8 },
  313. { STV090x_P1_NOSCFG, 0x1c },
  314. { STV090x_P1_CORRELMANT, 0x70 },
  315. { STV090x_P1_CORRELABS, 0x88 },
  316. { STV090x_P1_AGC2O, 0x5b },
  317. { STV090x_P1_AGC2REF, 0x38 },
  318. { STV090x_P1_CARCFG, 0xe4 },
  319. { STV090x_P1_ACLC, 0x1A },
  320. { STV090x_P1_BCLC, 0x09 },
  321. { STV090x_P1_CARHDR, 0x08 },
  322. { STV090x_P1_KREFTMG, 0xc1 },
  323. { STV090x_P1_SFRSTEP, 0x58 },
  324. { STV090x_P1_TMGCFG2, 0x01 },
  325. { STV090x_P1_CAR2CFG, 0x26 },
  326. { STV090x_P1_BCLC2S2Q, 0x86 },
  327. { STV090x_P1_BCLC2S28, 0x86 },
  328. { STV090x_P1_SMAPCOEF7, 0x77 },
  329. { STV090x_P1_SMAPCOEF6, 0x85 },
  330. { STV090x_P1_SMAPCOEF5, 0x77 },
  331. { STV090x_P1_DMDCFG2, 0x3b },
  332. { STV090x_P1_MODCODLST0, 0xff },
  333. { STV090x_P1_MODCODLST1, 0xff },
  334. { STV090x_P1_MODCODLST2, 0xff },
  335. { STV090x_P1_MODCODLST3, 0xff },
  336. { STV090x_P1_MODCODLST4, 0xff },
  337. { STV090x_P1_MODCODLST5, 0xff },
  338. { STV090x_P1_MODCODLST6, 0xff },
  339. { STV090x_P1_MODCODLST7, 0xcc },
  340. { STV090x_P1_MODCODLST8, 0xcc },
  341. { STV090x_P1_MODCODLST9, 0xcc },
  342. { STV090x_P1_MODCODLSTA, 0xcc },
  343. { STV090x_P1_MODCODLSTB, 0xcc },
  344. { STV090x_P1_MODCODLSTC, 0xcc },
  345. { STV090x_P1_MODCODLSTD, 0xcc },
  346. { STV090x_P1_MODCODLSTE, 0xcc },
  347. { STV090x_P1_MODCODLSTF, 0xcf },
  348. { STV090x_GENCFG, 0x1d },
  349. { STV090x_NBITER_NF4, 0x37 },
  350. { STV090x_NBITER_NF5, 0x29 },
  351. { STV090x_NBITER_NF6, 0x37 },
  352. { STV090x_NBITER_NF7, 0x33 },
  353. { STV090x_NBITER_NF8, 0x31 },
  354. { STV090x_NBITER_NF9, 0x2f },
  355. { STV090x_NBITER_NF10, 0x39 },
  356. { STV090x_NBITER_NF11, 0x3a },
  357. { STV090x_NBITER_NF12, 0x29 },
  358. { STV090x_NBITER_NF13, 0x37 },
  359. { STV090x_NBITER_NF14, 0x33 },
  360. { STV090x_NBITER_NF15, 0x2f },
  361. { STV090x_NBITER_NF16, 0x39 },
  362. { STV090x_NBITER_NF17, 0x3a },
  363. { STV090x_NBITERNOERR, 0x04 },
  364. { STV090x_GAINLLR_NF4, 0x0C },
  365. { STV090x_GAINLLR_NF5, 0x0F },
  366. { STV090x_GAINLLR_NF6, 0x11 },
  367. { STV090x_GAINLLR_NF7, 0x14 },
  368. { STV090x_GAINLLR_NF8, 0x17 },
  369. { STV090x_GAINLLR_NF9, 0x19 },
  370. { STV090x_GAINLLR_NF10, 0x20 },
  371. { STV090x_GAINLLR_NF11, 0x21 },
  372. { STV090x_GAINLLR_NF12, 0x0D },
  373. { STV090x_GAINLLR_NF13, 0x0F },
  374. { STV090x_GAINLLR_NF14, 0x13 },
  375. { STV090x_GAINLLR_NF15, 0x1A },
  376. { STV090x_GAINLLR_NF16, 0x1F },
  377. { STV090x_GAINLLR_NF17, 0x21 },
  378. { STV090x_RCCFGH, 0x20 },
  379. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  380. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  381. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  382. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  383. };
  384. static struct stv090x_reg stv0903_initval[] = {
  385. { STV090x_OUTCFG, 0x00 },
  386. { STV090x_AGCRF1CFG, 0x11 },
  387. { STV090x_STOPCLK1, 0x48 },
  388. { STV090x_STOPCLK2, 0x14 },
  389. { STV090x_TSTTNR1, 0x27 },
  390. { STV090x_TSTTNR2, 0x21 },
  391. { STV090x_P1_DISTXCTL, 0x22 },
  392. { STV090x_P1_F22TX, 0xc0 },
  393. { STV090x_P1_F22RX, 0xc0 },
  394. { STV090x_P1_DISRXCTL, 0x00 },
  395. { STV090x_P1_DMDCFGMD, 0xF9 },
  396. { STV090x_P1_DEMOD, 0x08 },
  397. { STV090x_P1_DMDCFG3, 0xc4 },
  398. { STV090x_P1_CARFREQ, 0xed },
  399. { STV090x_P1_TNRCFG2, 0x82 },
  400. { STV090x_P1_LDT, 0xd0 },
  401. { STV090x_P1_LDT2, 0xb8 },
  402. { STV090x_P1_TMGCFG, 0xd2 },
  403. { STV090x_P1_TMGTHRISE, 0x20 },
  404. { STV090x_P1_TMGTHFALL, 0x00 },
  405. { STV090x_P1_SFRUPRATIO, 0xf0 },
  406. { STV090x_P1_SFRLOWRATIO, 0x70 },
  407. { STV090x_P1_TSCFGL, 0x20 },
  408. { STV090x_P1_FECSPY, 0x88 },
  409. { STV090x_P1_FSPYDATA, 0x3a },
  410. { STV090x_P1_FBERCPT4, 0x00 },
  411. { STV090x_P1_FSPYBER, 0x10 },
  412. { STV090x_P1_ERRCTRL1, 0x35 },
  413. { STV090x_P1_ERRCTRL2, 0xc1 },
  414. { STV090x_P1_CFRICFG, 0xf8 },
  415. { STV090x_P1_NOSCFG, 0x1c },
  416. { STV090x_P1_DMDTOM, 0x20 },
  417. { STV090x_P1_CORRELMANT, 0x70 },
  418. { STV090x_P1_CORRELABS, 0x88 },
  419. { STV090x_P1_AGC2O, 0x5b },
  420. { STV090x_P1_AGC2REF, 0x38 },
  421. { STV090x_P1_CARCFG, 0xe4 },
  422. { STV090x_P1_ACLC, 0x1A },
  423. { STV090x_P1_BCLC, 0x09 },
  424. { STV090x_P1_CARHDR, 0x08 },
  425. { STV090x_P1_KREFTMG, 0xc1 },
  426. { STV090x_P1_SFRSTEP, 0x58 },
  427. { STV090x_P1_TMGCFG2, 0x01 },
  428. { STV090x_P1_CAR2CFG, 0x26 },
  429. { STV090x_P1_BCLC2S2Q, 0x86 },
  430. { STV090x_P1_BCLC2S28, 0x86 },
  431. { STV090x_P1_SMAPCOEF7, 0x77 },
  432. { STV090x_P1_SMAPCOEF6, 0x85 },
  433. { STV090x_P1_SMAPCOEF5, 0x77 },
  434. { STV090x_P1_DMDCFG2, 0x3b },
  435. { STV090x_P1_MODCODLST0, 0xff },
  436. { STV090x_P1_MODCODLST1, 0xff },
  437. { STV090x_P1_MODCODLST2, 0xff },
  438. { STV090x_P1_MODCODLST3, 0xff },
  439. { STV090x_P1_MODCODLST4, 0xff },
  440. { STV090x_P1_MODCODLST5, 0xff },
  441. { STV090x_P1_MODCODLST6, 0xff },
  442. { STV090x_P1_MODCODLST7, 0xcc },
  443. { STV090x_P1_MODCODLST8, 0xcc },
  444. { STV090x_P1_MODCODLST9, 0xcc },
  445. { STV090x_P1_MODCODLSTA, 0xcc },
  446. { STV090x_P1_MODCODLSTB, 0xcc },
  447. { STV090x_P1_MODCODLSTC, 0xcc },
  448. { STV090x_P1_MODCODLSTD, 0xcc },
  449. { STV090x_P1_MODCODLSTE, 0xcc },
  450. { STV090x_P1_MODCODLSTF, 0xcf },
  451. { STV090x_GENCFG, 0x1c },
  452. { STV090x_NBITER_NF4, 0x37 },
  453. { STV090x_NBITER_NF5, 0x29 },
  454. { STV090x_NBITER_NF6, 0x37 },
  455. { STV090x_NBITER_NF7, 0x33 },
  456. { STV090x_NBITER_NF8, 0x31 },
  457. { STV090x_NBITER_NF9, 0x2f },
  458. { STV090x_NBITER_NF10, 0x39 },
  459. { STV090x_NBITER_NF11, 0x3a },
  460. { STV090x_NBITER_NF12, 0x29 },
  461. { STV090x_NBITER_NF13, 0x37 },
  462. { STV090x_NBITER_NF14, 0x33 },
  463. { STV090x_NBITER_NF15, 0x2f },
  464. { STV090x_NBITER_NF16, 0x39 },
  465. { STV090x_NBITER_NF17, 0x3a },
  466. { STV090x_NBITERNOERR, 0x04 },
  467. { STV090x_GAINLLR_NF4, 0x0C },
  468. { STV090x_GAINLLR_NF5, 0x0F },
  469. { STV090x_GAINLLR_NF6, 0x11 },
  470. { STV090x_GAINLLR_NF7, 0x14 },
  471. { STV090x_GAINLLR_NF8, 0x17 },
  472. { STV090x_GAINLLR_NF9, 0x19 },
  473. { STV090x_GAINLLR_NF10, 0x20 },
  474. { STV090x_GAINLLR_NF11, 0x21 },
  475. { STV090x_GAINLLR_NF12, 0x0D },
  476. { STV090x_GAINLLR_NF13, 0x0F },
  477. { STV090x_GAINLLR_NF14, 0x13 },
  478. { STV090x_GAINLLR_NF15, 0x1A },
  479. { STV090x_GAINLLR_NF16, 0x1F },
  480. { STV090x_GAINLLR_NF17, 0x21 },
  481. { STV090x_RCCFGH, 0x20 },
  482. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  483. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  484. };
  485. static struct stv090x_reg stv0900_cut20_val[] = {
  486. { STV090x_P2_DMDCFG3, 0xe8 },
  487. { STV090x_P2_DMDCFG4, 0x10 },
  488. { STV090x_P2_CARFREQ, 0x38 },
  489. { STV090x_P2_CARHDR, 0x20 },
  490. { STV090x_P2_KREFTMG, 0x5a },
  491. { STV090x_P2_SMAPCOEF7, 0x06 },
  492. { STV090x_P2_SMAPCOEF6, 0x00 },
  493. { STV090x_P2_SMAPCOEF5, 0x04 },
  494. { STV090x_P2_NOSCFG, 0x0c },
  495. { STV090x_P1_DMDCFG3, 0xe8 },
  496. { STV090x_P1_DMDCFG4, 0x10 },
  497. { STV090x_P1_CARFREQ, 0x38 },
  498. { STV090x_P1_CARHDR, 0x20 },
  499. { STV090x_P1_KREFTMG, 0x5a },
  500. { STV090x_P1_SMAPCOEF7, 0x06 },
  501. { STV090x_P1_SMAPCOEF6, 0x00 },
  502. { STV090x_P1_SMAPCOEF5, 0x04 },
  503. { STV090x_P1_NOSCFG, 0x0c },
  504. { STV090x_GAINLLR_NF4, 0x21 },
  505. { STV090x_GAINLLR_NF5, 0x21 },
  506. { STV090x_GAINLLR_NF6, 0x20 },
  507. { STV090x_GAINLLR_NF7, 0x1F },
  508. { STV090x_GAINLLR_NF8, 0x1E },
  509. { STV090x_GAINLLR_NF9, 0x1E },
  510. { STV090x_GAINLLR_NF10, 0x1D },
  511. { STV090x_GAINLLR_NF11, 0x1B },
  512. { STV090x_GAINLLR_NF12, 0x20 },
  513. { STV090x_GAINLLR_NF13, 0x20 },
  514. { STV090x_GAINLLR_NF14, 0x20 },
  515. { STV090x_GAINLLR_NF15, 0x20 },
  516. { STV090x_GAINLLR_NF16, 0x20 },
  517. { STV090x_GAINLLR_NF17, 0x21 },
  518. };
  519. static struct stv090x_reg stv0903_cut20_val[] = {
  520. { STV090x_P1_DMDCFG3, 0xe8 },
  521. { STV090x_P1_DMDCFG4, 0x10 },
  522. { STV090x_P1_CARFREQ, 0x38 },
  523. { STV090x_P1_CARHDR, 0x20 },
  524. { STV090x_P1_KREFTMG, 0x5a },
  525. { STV090x_P1_SMAPCOEF7, 0x06 },
  526. { STV090x_P1_SMAPCOEF6, 0x00 },
  527. { STV090x_P1_SMAPCOEF5, 0x04 },
  528. { STV090x_P1_NOSCFG, 0x0c },
  529. { STV090x_GAINLLR_NF4, 0x21 },
  530. { STV090x_GAINLLR_NF5, 0x21 },
  531. { STV090x_GAINLLR_NF6, 0x20 },
  532. { STV090x_GAINLLR_NF7, 0x1F },
  533. { STV090x_GAINLLR_NF8, 0x1E },
  534. { STV090x_GAINLLR_NF9, 0x1E },
  535. { STV090x_GAINLLR_NF10, 0x1D },
  536. { STV090x_GAINLLR_NF11, 0x1B },
  537. { STV090x_GAINLLR_NF12, 0x20 },
  538. { STV090x_GAINLLR_NF13, 0x20 },
  539. { STV090x_GAINLLR_NF14, 0x20 },
  540. { STV090x_GAINLLR_NF15, 0x20 },
  541. { STV090x_GAINLLR_NF16, 0x20 },
  542. { STV090x_GAINLLR_NF17, 0x21 }
  543. };
  544. /* Cut 2.0 Long Frame Tracking CR loop */
  545. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  546. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  547. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  548. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  549. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  550. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  551. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  552. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  553. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  554. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  555. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  556. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  557. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  558. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  559. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  560. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  561. };
  562. /* Cut 3.0 Long Frame Tracking CR loop */
  563. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
  564. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  565. { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
  566. { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  567. { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  568. { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  569. { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  570. { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  571. { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  572. { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  573. { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
  574. { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
  575. { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
  576. { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
  577. { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
  578. { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
  579. };
  580. /* Cut 2.0 Long Frame Tracking CR Loop */
  581. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  582. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  583. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  584. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  585. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  586. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  587. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  588. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  589. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  590. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  591. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  592. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  593. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  594. };
  595. /* Cut 3.0 Long Frame Tracking CR Loop */
  596. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
  597. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  598. { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
  599. { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
  600. { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  601. { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  602. { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  603. { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  604. { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  605. { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  606. { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  607. { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  608. { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
  609. };
  610. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  611. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  612. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  613. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  614. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  615. };
  616. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
  617. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  618. { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
  619. { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
  620. { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
  621. };
  622. /* Cut 2.0 Short Frame Tracking CR Loop */
  623. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
  624. /* MODCOD 2M 5M 10M 20M 30M */
  625. { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
  626. { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
  627. { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
  628. { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
  629. };
  630. /* Cut 3.0 Short Frame Tracking CR Loop */
  631. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
  632. /* MODCOD 2M 5M 10M 20M 30M */
  633. { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
  634. { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
  635. { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
  636. { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
  637. };
  638. static inline s32 comp2(s32 __x, s32 __width)
  639. {
  640. if (__width == 32)
  641. return __x;
  642. else
  643. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  644. }
  645. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  646. {
  647. const struct stv090x_config *config = state->config;
  648. int ret;
  649. u8 b0[] = { reg >> 8, reg & 0xff };
  650. u8 buf;
  651. struct i2c_msg msg[] = {
  652. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  653. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  654. };
  655. ret = i2c_transfer(state->i2c, msg, 2);
  656. if (ret != 2) {
  657. if (ret != -ERESTARTSYS)
  658. dprintk(FE_ERROR, 1,
  659. "Read error, Reg=[0x%02x], Status=%d",
  660. reg, ret);
  661. return ret < 0 ? ret : -EREMOTEIO;
  662. }
  663. if (unlikely(*state->verbose >= FE_DEBUGREG))
  664. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  665. reg, buf);
  666. return (unsigned int) buf;
  667. }
  668. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  669. {
  670. const struct stv090x_config *config = state->config;
  671. int ret;
  672. u8 buf[2 + count];
  673. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  674. buf[0] = reg >> 8;
  675. buf[1] = reg & 0xff;
  676. memcpy(&buf[2], data, count);
  677. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  678. int i;
  679. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  680. for (i = 0; i < count; i++)
  681. printk(" %02x", data[i]);
  682. printk("\n");
  683. }
  684. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  685. if (ret != 1) {
  686. if (ret != -ERESTARTSYS)
  687. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  688. reg, data[0], count, ret);
  689. return ret < 0 ? ret : -EREMOTEIO;
  690. }
  691. return 0;
  692. }
  693. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  694. {
  695. return stv090x_write_regs(state, reg, &data, 1);
  696. }
  697. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  698. {
  699. struct stv090x_state *state = fe->demodulator_priv;
  700. u32 reg;
  701. if (enable)
  702. mutex_lock(&state->internal->tuner_lock);
  703. reg = STV090x_READ_DEMOD(state, I2CRPT);
  704. if (enable) {
  705. dprintk(FE_DEBUG, 1, "Enable Gate");
  706. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  707. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  708. goto err;
  709. } else {
  710. dprintk(FE_DEBUG, 1, "Disable Gate");
  711. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  712. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  713. goto err;
  714. }
  715. if (!enable)
  716. mutex_unlock(&state->internal->tuner_lock);
  717. return 0;
  718. err:
  719. dprintk(FE_ERROR, 1, "I/O error");
  720. mutex_unlock(&state->internal->tuner_lock);
  721. return -1;
  722. }
  723. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  724. {
  725. switch (state->algo) {
  726. case STV090x_BLIND_SEARCH:
  727. dprintk(FE_DEBUG, 1, "Blind Search");
  728. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  729. state->DemodTimeout = 1500;
  730. state->FecTimeout = 400;
  731. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  732. state->DemodTimeout = 1000;
  733. state->FecTimeout = 300;
  734. } else { /*SR >20Msps*/
  735. state->DemodTimeout = 700;
  736. state->FecTimeout = 100;
  737. }
  738. break;
  739. case STV090x_COLD_SEARCH:
  740. case STV090x_WARM_SEARCH:
  741. default:
  742. dprintk(FE_DEBUG, 1, "Normal Search");
  743. if (state->srate <= 1000000) { /*SR <=1Msps*/
  744. state->DemodTimeout = 4500;
  745. state->FecTimeout = 1700;
  746. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  747. state->DemodTimeout = 2500;
  748. state->FecTimeout = 1100;
  749. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  750. state->DemodTimeout = 1000;
  751. state->FecTimeout = 550;
  752. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  753. state->DemodTimeout = 700;
  754. state->FecTimeout = 250;
  755. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  756. state->DemodTimeout = 400;
  757. state->FecTimeout = 130;
  758. } else { /*SR >20Msps*/
  759. state->DemodTimeout = 300;
  760. state->FecTimeout = 100;
  761. }
  762. break;
  763. }
  764. if (state->algo == STV090x_WARM_SEARCH)
  765. state->DemodTimeout /= 2;
  766. }
  767. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  768. {
  769. u32 sym;
  770. if (srate > 60000000) {
  771. sym = (srate << 4); /* SR * 2^16 / master_clk */
  772. sym /= (state->internal->mclk >> 12);
  773. } else if (srate > 6000000) {
  774. sym = (srate << 6);
  775. sym /= (state->internal->mclk >> 10);
  776. } else {
  777. sym = (srate << 9);
  778. sym /= (state->internal->mclk >> 7);
  779. }
  780. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  781. goto err;
  782. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  783. goto err;
  784. return 0;
  785. err:
  786. dprintk(FE_ERROR, 1, "I/O error");
  787. return -1;
  788. }
  789. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  790. {
  791. u32 sym;
  792. srate = 105 * (srate / 100);
  793. if (srate > 60000000) {
  794. sym = (srate << 4); /* SR * 2^16 / master_clk */
  795. sym /= (state->internal->mclk >> 12);
  796. } else if (srate > 6000000) {
  797. sym = (srate << 6);
  798. sym /= (state->internal->mclk >> 10);
  799. } else {
  800. sym = (srate << 9);
  801. sym /= (state->internal->mclk >> 7);
  802. }
  803. if (sym < 0x7fff) {
  804. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  805. goto err;
  806. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  807. goto err;
  808. } else {
  809. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  810. goto err;
  811. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  812. goto err;
  813. }
  814. return 0;
  815. err:
  816. dprintk(FE_ERROR, 1, "I/O error");
  817. return -1;
  818. }
  819. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  820. {
  821. u32 sym;
  822. srate = 95 * (srate / 100);
  823. if (srate > 60000000) {
  824. sym = (srate << 4); /* SR * 2^16 / master_clk */
  825. sym /= (state->internal->mclk >> 12);
  826. } else if (srate > 6000000) {
  827. sym = (srate << 6);
  828. sym /= (state->internal->mclk >> 10);
  829. } else {
  830. sym = (srate << 9);
  831. sym /= (state->internal->mclk >> 7);
  832. }
  833. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
  834. goto err;
  835. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  836. goto err;
  837. return 0;
  838. err:
  839. dprintk(FE_ERROR, 1, "I/O error");
  840. return -1;
  841. }
  842. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  843. {
  844. u32 ro;
  845. switch (rolloff) {
  846. case STV090x_RO_20:
  847. ro = 20;
  848. break;
  849. case STV090x_RO_25:
  850. ro = 25;
  851. break;
  852. case STV090x_RO_35:
  853. default:
  854. ro = 35;
  855. break;
  856. }
  857. return srate + (srate * ro) / 100;
  858. }
  859. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  860. {
  861. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  862. goto err;
  863. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  864. goto err;
  865. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  866. goto err;
  867. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  868. goto err;
  869. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  870. goto err;
  871. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  872. goto err;
  873. return 0;
  874. err:
  875. dprintk(FE_ERROR, 1, "I/O error");
  876. return -1;
  877. }
  878. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  879. {
  880. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  881. goto err;
  882. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  883. goto err;
  884. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  885. goto err;
  886. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  887. goto err;
  888. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  889. goto err;
  890. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  891. goto err;
  892. return 0;
  893. err:
  894. dprintk(FE_ERROR, 1, "I/O error");
  895. return -1;
  896. }
  897. static int stv090x_set_viterbi(struct stv090x_state *state)
  898. {
  899. switch (state->search_mode) {
  900. case STV090x_SEARCH_AUTO:
  901. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  902. goto err;
  903. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  904. goto err;
  905. break;
  906. case STV090x_SEARCH_DVBS1:
  907. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  908. goto err;
  909. switch (state->fec) {
  910. case STV090x_PR12:
  911. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  912. goto err;
  913. break;
  914. case STV090x_PR23:
  915. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  916. goto err;
  917. break;
  918. case STV090x_PR34:
  919. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  920. goto err;
  921. break;
  922. case STV090x_PR56:
  923. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  924. goto err;
  925. break;
  926. case STV090x_PR78:
  927. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  928. goto err;
  929. break;
  930. default:
  931. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  932. goto err;
  933. break;
  934. }
  935. break;
  936. case STV090x_SEARCH_DSS:
  937. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  938. goto err;
  939. switch (state->fec) {
  940. case STV090x_PR12:
  941. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  942. goto err;
  943. break;
  944. case STV090x_PR23:
  945. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  946. goto err;
  947. break;
  948. case STV090x_PR67:
  949. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  950. goto err;
  951. break;
  952. default:
  953. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  954. goto err;
  955. break;
  956. }
  957. break;
  958. default:
  959. break;
  960. }
  961. return 0;
  962. err:
  963. dprintk(FE_ERROR, 1, "I/O error");
  964. return -1;
  965. }
  966. static int stv090x_stop_modcod(struct stv090x_state *state)
  967. {
  968. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  969. goto err;
  970. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  971. goto err;
  972. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  973. goto err;
  974. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  975. goto err;
  976. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  977. goto err;
  978. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  979. goto err;
  980. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  981. goto err;
  982. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  983. goto err;
  984. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  985. goto err;
  986. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  987. goto err;
  988. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  989. goto err;
  990. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  991. goto err;
  992. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  993. goto err;
  994. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  995. goto err;
  996. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  997. goto err;
  998. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  999. goto err;
  1000. return 0;
  1001. err:
  1002. dprintk(FE_ERROR, 1, "I/O error");
  1003. return -1;
  1004. }
  1005. static int stv090x_activate_modcod(struct stv090x_state *state)
  1006. {
  1007. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1008. goto err;
  1009. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  1010. goto err;
  1011. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  1012. goto err;
  1013. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  1014. goto err;
  1015. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  1016. goto err;
  1017. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  1018. goto err;
  1019. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  1020. goto err;
  1021. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  1022. goto err;
  1023. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  1024. goto err;
  1025. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  1026. goto err;
  1027. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  1028. goto err;
  1029. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  1030. goto err;
  1031. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  1032. goto err;
  1033. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  1034. goto err;
  1035. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  1036. goto err;
  1037. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  1038. goto err;
  1039. return 0;
  1040. err:
  1041. dprintk(FE_ERROR, 1, "I/O error");
  1042. return -1;
  1043. }
  1044. static int stv090x_activate_modcod_single(struct stv090x_state *state)
  1045. {
  1046. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1047. goto err;
  1048. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
  1049. goto err;
  1050. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
  1051. goto err;
  1052. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
  1053. goto err;
  1054. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
  1055. goto err;
  1056. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
  1057. goto err;
  1058. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
  1059. goto err;
  1060. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
  1061. goto err;
  1062. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
  1063. goto err;
  1064. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
  1065. goto err;
  1066. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
  1067. goto err;
  1068. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
  1069. goto err;
  1070. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
  1071. goto err;
  1072. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
  1073. goto err;
  1074. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
  1075. goto err;
  1076. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
  1077. goto err;
  1078. return 0;
  1079. err:
  1080. dprintk(FE_ERROR, 1, "I/O error");
  1081. return -1;
  1082. }
  1083. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  1084. {
  1085. u32 reg;
  1086. switch (state->demod) {
  1087. case STV090x_DEMODULATOR_0:
  1088. mutex_lock(&state->internal->demod_lock);
  1089. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1090. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  1091. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1092. goto err;
  1093. mutex_unlock(&state->internal->demod_lock);
  1094. break;
  1095. case STV090x_DEMODULATOR_1:
  1096. mutex_lock(&state->internal->demod_lock);
  1097. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1098. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  1099. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1100. goto err;
  1101. mutex_unlock(&state->internal->demod_lock);
  1102. break;
  1103. default:
  1104. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1105. break;
  1106. }
  1107. return 0;
  1108. err:
  1109. mutex_unlock(&state->internal->demod_lock);
  1110. dprintk(FE_ERROR, 1, "I/O error");
  1111. return -1;
  1112. }
  1113. static int stv090x_dvbs_track_crl(struct stv090x_state *state)
  1114. {
  1115. if (state->internal->dev_ver >= 0x30) {
  1116. /* Set ACLC BCLC optimised value vs SR */
  1117. if (state->srate >= 15000000) {
  1118. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
  1119. goto err;
  1120. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
  1121. goto err;
  1122. } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
  1123. if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
  1124. goto err;
  1125. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
  1126. goto err;
  1127. } else if (state->srate < 7000000) {
  1128. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
  1129. goto err;
  1130. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
  1131. goto err;
  1132. }
  1133. } else {
  1134. /* Cut 2.0 */
  1135. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1136. goto err;
  1137. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1138. goto err;
  1139. }
  1140. return 0;
  1141. err:
  1142. dprintk(FE_ERROR, 1, "I/O error");
  1143. return -1;
  1144. }
  1145. static int stv090x_delivery_search(struct stv090x_state *state)
  1146. {
  1147. u32 reg;
  1148. switch (state->search_mode) {
  1149. case STV090x_SEARCH_DVBS1:
  1150. case STV090x_SEARCH_DSS:
  1151. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1152. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1153. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1154. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1155. goto err;
  1156. /* Activate Viterbi decoder in legacy search,
  1157. * do not use FRESVIT1, might impact VITERBI2
  1158. */
  1159. if (stv090x_vitclk_ctl(state, 0) < 0)
  1160. goto err;
  1161. if (stv090x_dvbs_track_crl(state) < 0)
  1162. goto err;
  1163. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1164. goto err;
  1165. if (stv090x_set_vit_thacq(state) < 0)
  1166. goto err;
  1167. if (stv090x_set_viterbi(state) < 0)
  1168. goto err;
  1169. break;
  1170. case STV090x_SEARCH_DVBS2:
  1171. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1172. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1173. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1174. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1175. goto err;
  1176. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1177. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1178. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1179. goto err;
  1180. if (stv090x_vitclk_ctl(state, 1) < 0)
  1181. goto err;
  1182. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1183. goto err;
  1184. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1185. goto err;
  1186. if (state->internal->dev_ver <= 0x20) {
  1187. /* enable S2 carrier loop */
  1188. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1189. goto err;
  1190. } else {
  1191. /* > Cut 3: Stop carrier 3 */
  1192. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1193. goto err;
  1194. }
  1195. if (state->demod_mode != STV090x_SINGLE) {
  1196. /* Cut 2: enable link during search */
  1197. if (stv090x_activate_modcod(state) < 0)
  1198. goto err;
  1199. } else {
  1200. /* Single demodulator
  1201. * Authorize SHORT and LONG frames,
  1202. * QPSK, 8PSK, 16APSK and 32APSK
  1203. */
  1204. if (stv090x_activate_modcod_single(state) < 0)
  1205. goto err;
  1206. }
  1207. if (stv090x_set_vit_thtracq(state) < 0)
  1208. goto err;
  1209. break;
  1210. case STV090x_SEARCH_AUTO:
  1211. default:
  1212. /* enable DVB-S2 and DVB-S2 in Auto MODE */
  1213. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1214. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1215. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1216. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1217. goto err;
  1218. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1219. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1220. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1221. goto err;
  1222. if (stv090x_vitclk_ctl(state, 0) < 0)
  1223. goto err;
  1224. if (stv090x_dvbs_track_crl(state) < 0)
  1225. goto err;
  1226. if (state->internal->dev_ver <= 0x20) {
  1227. /* enable S2 carrier loop */
  1228. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1229. goto err;
  1230. } else {
  1231. /* > Cut 3: Stop carrier 3 */
  1232. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1233. goto err;
  1234. }
  1235. if (state->demod_mode != STV090x_SINGLE) {
  1236. /* Cut 2: enable link during search */
  1237. if (stv090x_activate_modcod(state) < 0)
  1238. goto err;
  1239. } else {
  1240. /* Single demodulator
  1241. * Authorize SHORT and LONG frames,
  1242. * QPSK, 8PSK, 16APSK and 32APSK
  1243. */
  1244. if (stv090x_activate_modcod_single(state) < 0)
  1245. goto err;
  1246. }
  1247. if (stv090x_set_vit_thacq(state) < 0)
  1248. goto err;
  1249. if (stv090x_set_viterbi(state) < 0)
  1250. goto err;
  1251. break;
  1252. }
  1253. return 0;
  1254. err:
  1255. dprintk(FE_ERROR, 1, "I/O error");
  1256. return -1;
  1257. }
  1258. static int stv090x_start_search(struct stv090x_state *state)
  1259. {
  1260. u32 reg, freq_abs;
  1261. s16 freq;
  1262. /* Reset demodulator */
  1263. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1264. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1265. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1266. goto err;
  1267. if (state->internal->dev_ver <= 0x20) {
  1268. if (state->srate <= 5000000) {
  1269. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1270. goto err;
  1271. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1272. goto err;
  1273. if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
  1274. goto err;
  1275. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1276. goto err;
  1277. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1278. goto err;
  1279. /*enlarge the timing bandwith for Low SR*/
  1280. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1281. goto err;
  1282. } else {
  1283. /* If the symbol rate is >5 Msps
  1284. Set The carrier search up and low to auto mode */
  1285. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1286. goto err;
  1287. /*reduce the timing bandwith for high SR*/
  1288. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1289. goto err;
  1290. }
  1291. } else {
  1292. /* >= Cut 3 */
  1293. if (state->srate <= 5000000) {
  1294. /* enlarge the timing bandwith for Low SR */
  1295. STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
  1296. } else {
  1297. /* reduce timing bandwith for high SR */
  1298. STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
  1299. }
  1300. /* Set CFR min and max to manual mode */
  1301. STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
  1302. if (state->algo == STV090x_WARM_SEARCH) {
  1303. /* WARM Start
  1304. * CFR min = -1MHz,
  1305. * CFR max = +1MHz
  1306. */
  1307. freq_abs = 1000 << 16;
  1308. freq_abs /= (state->internal->mclk / 1000);
  1309. freq = (s16) freq_abs;
  1310. } else {
  1311. /* COLD Start
  1312. * CFR min =- (SearchRange / 2 + 600KHz)
  1313. * CFR max = +(SearchRange / 2 + 600KHz)
  1314. * (600KHz for the tuner step size)
  1315. */
  1316. freq_abs = (state->search_range / 2000) + 600;
  1317. freq_abs = freq_abs << 16;
  1318. freq_abs /= (state->internal->mclk / 1000);
  1319. freq = (s16) freq_abs;
  1320. }
  1321. if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
  1322. goto err;
  1323. if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
  1324. goto err;
  1325. freq *= -1;
  1326. if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
  1327. goto err;
  1328. if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
  1329. goto err;
  1330. }
  1331. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1332. goto err;
  1333. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1334. goto err;
  1335. if (state->internal->dev_ver >= 0x20) {
  1336. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1337. goto err;
  1338. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1339. goto err;
  1340. if ((state->search_mode == STV090x_DVBS1) ||
  1341. (state->search_mode == STV090x_DSS) ||
  1342. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1343. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1344. goto err;
  1345. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1346. goto err;
  1347. }
  1348. }
  1349. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1350. goto err;
  1351. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1352. goto err;
  1353. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1354. goto err;
  1355. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1356. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1357. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1358. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1359. goto err;
  1360. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1361. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1362. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1363. goto err;
  1364. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
  1365. goto err;
  1366. if (state->internal->dev_ver >= 0x20) {
  1367. /*Frequency offset detector setting*/
  1368. if (state->srate < 2000000) {
  1369. if (state->internal->dev_ver <= 0x20) {
  1370. /* Cut 2 */
  1371. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
  1372. goto err;
  1373. } else {
  1374. /* Cut 3 */
  1375. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
  1376. goto err;
  1377. }
  1378. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
  1379. goto err;
  1380. } else if (state->srate < 10000000) {
  1381. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1382. goto err;
  1383. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1384. goto err;
  1385. } else {
  1386. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1387. goto err;
  1388. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1389. goto err;
  1390. }
  1391. } else {
  1392. if (state->srate < 10000000) {
  1393. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1394. goto err;
  1395. } else {
  1396. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1397. goto err;
  1398. }
  1399. }
  1400. switch (state->algo) {
  1401. case STV090x_WARM_SEARCH:
  1402. /* The symbol rate and the exact
  1403. * carrier Frequency are known
  1404. */
  1405. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1406. goto err;
  1407. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1408. goto err;
  1409. break;
  1410. case STV090x_COLD_SEARCH:
  1411. /* The symbol rate is known */
  1412. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1413. goto err;
  1414. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1415. goto err;
  1416. break;
  1417. default:
  1418. break;
  1419. }
  1420. return 0;
  1421. err:
  1422. dprintk(FE_ERROR, 1, "I/O error");
  1423. return -1;
  1424. }
  1425. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1426. {
  1427. u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
  1428. s32 i, j, steps, dir;
  1429. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1430. goto err;
  1431. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1432. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1433. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1434. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1435. goto err;
  1436. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1437. goto err;
  1438. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1439. goto err;
  1440. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1441. goto err;
  1442. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1443. goto err;
  1444. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1445. goto err;
  1446. if (stv090x_set_srate(state, 1000000) < 0)
  1447. goto err;
  1448. steps = state->search_range / 1000000;
  1449. if (steps <= 0)
  1450. steps = 1;
  1451. dir = 1;
  1452. freq_step = (1000000 * 256) / (state->internal->mclk / 256);
  1453. freq_init = 0;
  1454. for (i = 0; i < steps; i++) {
  1455. if (dir > 0)
  1456. freq_init = freq_init + (freq_step * i);
  1457. else
  1458. freq_init = freq_init - (freq_step * i);
  1459. dir *= -1;
  1460. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1461. goto err;
  1462. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1463. goto err;
  1464. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1465. goto err;
  1466. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1467. goto err;
  1468. msleep(10);
  1469. agc2 = 0;
  1470. for (j = 0; j < 10; j++) {
  1471. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1472. STV090x_READ_DEMOD(state, AGC2I0);
  1473. }
  1474. agc2 /= 10;
  1475. if (agc2 < agc2_min)
  1476. agc2_min = agc2;
  1477. }
  1478. return agc2_min;
  1479. err:
  1480. dprintk(FE_ERROR, 1, "I/O error");
  1481. return -1;
  1482. }
  1483. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1484. {
  1485. u8 r3, r2, r1, r0;
  1486. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1487. r3 = STV090x_READ_DEMOD(state, SFR3);
  1488. r2 = STV090x_READ_DEMOD(state, SFR2);
  1489. r1 = STV090x_READ_DEMOD(state, SFR1);
  1490. r0 = STV090x_READ_DEMOD(state, SFR0);
  1491. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1492. int_1 = clk >> 16;
  1493. int_2 = srate >> 16;
  1494. tmp_1 = clk % 0x10000;
  1495. tmp_2 = srate % 0x10000;
  1496. srate = (int_1 * int_2) +
  1497. ((int_1 * tmp_2) >> 16) +
  1498. ((int_2 * tmp_1) >> 16);
  1499. return srate;
  1500. }
  1501. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1502. {
  1503. struct dvb_frontend *fe = &state->frontend;
  1504. int tmg_lock = 0, i;
  1505. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1506. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1507. u32 agc2th;
  1508. if (state->internal->dev_ver >= 0x30)
  1509. agc2th = 0x2e00;
  1510. else
  1511. agc2th = 0x1f00;
  1512. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1513. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1514. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1515. goto err;
  1516. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1517. goto err;
  1518. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
  1519. goto err;
  1520. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1521. goto err;
  1522. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1523. goto err;
  1524. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1525. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1526. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1527. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1528. goto err;
  1529. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1530. goto err;
  1531. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1532. goto err;
  1533. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1534. goto err;
  1535. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1536. goto err;
  1537. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1538. goto err;
  1539. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
  1540. goto err;
  1541. if (state->internal->dev_ver >= 0x30) {
  1542. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
  1543. goto err;
  1544. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
  1545. goto err;
  1546. } else if (state->internal->dev_ver >= 0x20) {
  1547. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1548. goto err;
  1549. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1550. goto err;
  1551. }
  1552. if (state->srate <= 2000000)
  1553. car_step = 1000;
  1554. else if (state->srate <= 5000000)
  1555. car_step = 2000;
  1556. else if (state->srate <= 12000000)
  1557. car_step = 3000;
  1558. else
  1559. car_step = 5000;
  1560. steps = -1 + ((state->search_range / 1000) / car_step);
  1561. steps /= 2;
  1562. steps = (2 * steps) + 1;
  1563. if (steps < 0)
  1564. steps = 1;
  1565. else if (steps > 10) {
  1566. steps = 11;
  1567. car_step = (state->search_range / 1000) / 10;
  1568. }
  1569. cur_step = 0;
  1570. dir = 1;
  1571. freq = state->frequency;
  1572. while ((!tmg_lock) && (cur_step < steps)) {
  1573. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1574. goto err;
  1575. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1576. goto err;
  1577. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1578. goto err;
  1579. if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
  1580. goto err;
  1581. if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
  1582. goto err;
  1583. /* trigger acquisition */
  1584. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
  1585. goto err;
  1586. msleep(50);
  1587. for (i = 0; i < 10; i++) {
  1588. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1589. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1590. tmg_cpt++;
  1591. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1592. STV090x_READ_DEMOD(state, AGC2I0);
  1593. }
  1594. agc2 /= 10;
  1595. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1596. cur_step++;
  1597. dir *= -1;
  1598. if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
  1599. (srate_coarse < 50000000) && (srate_coarse > 850000))
  1600. tmg_lock = 1;
  1601. else if (cur_step < steps) {
  1602. if (dir > 0)
  1603. freq += cur_step * car_step;
  1604. else
  1605. freq -= cur_step * car_step;
  1606. /* Setup tuner */
  1607. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1608. goto err;
  1609. if (state->config->tuner_set_frequency) {
  1610. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1611. goto err_gateoff;
  1612. }
  1613. if (state->config->tuner_set_bandwidth) {
  1614. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1615. goto err_gateoff;
  1616. }
  1617. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1618. goto err;
  1619. msleep(50);
  1620. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1621. goto err;
  1622. if (state->config->tuner_get_status) {
  1623. if (state->config->tuner_get_status(fe, &reg) < 0)
  1624. goto err_gateoff;
  1625. }
  1626. if (reg)
  1627. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1628. else
  1629. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1630. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1631. goto err;
  1632. }
  1633. }
  1634. if (!tmg_lock)
  1635. srate_coarse = 0;
  1636. else
  1637. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1638. return srate_coarse;
  1639. err_gateoff:
  1640. stv090x_i2c_gate_ctrl(fe, 0);
  1641. err:
  1642. dprintk(FE_ERROR, 1, "I/O error");
  1643. return -1;
  1644. }
  1645. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1646. {
  1647. u32 srate_coarse, freq_coarse, sym, reg;
  1648. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1649. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1650. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1651. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1652. if (sym < state->srate)
  1653. srate_coarse = 0;
  1654. else {
  1655. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1656. goto err;
  1657. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  1658. goto err;
  1659. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1660. goto err;
  1661. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1662. goto err;
  1663. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1664. goto err;
  1665. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1666. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1667. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1668. goto err;
  1669. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1670. goto err;
  1671. if (state->internal->dev_ver >= 0x30) {
  1672. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
  1673. goto err;
  1674. } else if (state->internal->dev_ver >= 0x20) {
  1675. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1676. goto err;
  1677. }
  1678. if (srate_coarse > 3000000) {
  1679. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1680. sym = (sym / 1000) * 65536;
  1681. sym /= (state->internal->mclk / 1000);
  1682. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1683. goto err;
  1684. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1685. goto err;
  1686. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1687. sym = (sym / 1000) * 65536;
  1688. sym /= (state->internal->mclk / 1000);
  1689. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1690. goto err;
  1691. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1692. goto err;
  1693. sym = (srate_coarse / 1000) * 65536;
  1694. sym /= (state->internal->mclk / 1000);
  1695. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1696. goto err;
  1697. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1698. goto err;
  1699. } else {
  1700. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1701. sym = (sym / 100) * 65536;
  1702. sym /= (state->internal->mclk / 100);
  1703. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1704. goto err;
  1705. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1706. goto err;
  1707. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1708. sym = (sym / 100) * 65536;
  1709. sym /= (state->internal->mclk / 100);
  1710. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1711. goto err;
  1712. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1713. goto err;
  1714. sym = (srate_coarse / 100) * 65536;
  1715. sym /= (state->internal->mclk / 100);
  1716. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1717. goto err;
  1718. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1719. goto err;
  1720. }
  1721. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1722. goto err;
  1723. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1724. goto err;
  1725. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1726. goto err;
  1727. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1728. goto err;
  1729. }
  1730. return srate_coarse;
  1731. err:
  1732. dprintk(FE_ERROR, 1, "I/O error");
  1733. return -1;
  1734. }
  1735. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1736. {
  1737. s32 timer = 0, lock = 0;
  1738. u32 reg;
  1739. u8 stat;
  1740. while ((timer < timeout) && (!lock)) {
  1741. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1742. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1743. switch (stat) {
  1744. case 0: /* searching */
  1745. case 1: /* first PLH detected */
  1746. default:
  1747. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1748. lock = 0;
  1749. break;
  1750. case 2: /* DVB-S2 mode */
  1751. case 3: /* DVB-S1/legacy mode */
  1752. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1753. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1754. break;
  1755. }
  1756. if (!lock)
  1757. msleep(10);
  1758. else
  1759. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1760. timer += 10;
  1761. }
  1762. return lock;
  1763. }
  1764. static int stv090x_blind_search(struct stv090x_state *state)
  1765. {
  1766. u32 agc2, reg, srate_coarse;
  1767. s32 cpt_fail, agc2_ovflw, i;
  1768. u8 k_ref, k_max, k_min;
  1769. int coarse_fail, lock;
  1770. k_max = 110;
  1771. k_min = 10;
  1772. agc2 = stv090x_get_agc2_min_level(state);
  1773. if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
  1774. lock = 0;
  1775. } else {
  1776. if (state->internal->dev_ver <= 0x20) {
  1777. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1778. goto err;
  1779. } else {
  1780. /* > Cut 3 */
  1781. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
  1782. goto err;
  1783. }
  1784. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1785. goto err;
  1786. if (state->internal->dev_ver >= 0x20) {
  1787. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1788. goto err;
  1789. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1790. goto err;
  1791. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1792. goto err;
  1793. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1794. goto err;
  1795. }
  1796. k_ref = k_max;
  1797. do {
  1798. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1799. goto err;
  1800. if (stv090x_srate_srch_coarse(state) != 0) {
  1801. srate_coarse = stv090x_srate_srch_fine(state);
  1802. if (srate_coarse != 0) {
  1803. stv090x_get_lock_tmg(state);
  1804. lock = stv090x_get_dmdlock(state,
  1805. state->DemodTimeout);
  1806. } else {
  1807. lock = 0;
  1808. }
  1809. } else {
  1810. cpt_fail = 0;
  1811. agc2_ovflw = 0;
  1812. for (i = 0; i < 10; i++) {
  1813. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1814. STV090x_READ_DEMOD(state, AGC2I0);
  1815. if (agc2 >= 0xff00)
  1816. agc2_ovflw++;
  1817. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1818. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1819. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1820. cpt_fail++;
  1821. }
  1822. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1823. coarse_fail = 1;
  1824. lock = 0;
  1825. }
  1826. k_ref -= 20;
  1827. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1828. }
  1829. return lock;
  1830. err:
  1831. dprintk(FE_ERROR, 1, "I/O error");
  1832. return -1;
  1833. }
  1834. static int stv090x_chk_tmg(struct stv090x_state *state)
  1835. {
  1836. u32 reg;
  1837. s32 tmg_cpt = 0, i;
  1838. u8 freq, tmg_thh, tmg_thl;
  1839. int tmg_lock;
  1840. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1841. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1842. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1843. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1844. goto err;
  1845. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1846. goto err;
  1847. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1848. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1849. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1850. goto err;
  1851. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1852. goto err;
  1853. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1854. goto err;
  1855. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1856. goto err;
  1857. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1858. goto err;
  1859. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1860. goto err;
  1861. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1862. goto err;
  1863. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1864. goto err;
  1865. msleep(10);
  1866. for (i = 0; i < 10; i++) {
  1867. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1868. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1869. tmg_cpt++;
  1870. msleep(1);
  1871. }
  1872. if (tmg_cpt >= 3)
  1873. tmg_lock = 1;
  1874. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1875. goto err;
  1876. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1877. goto err;
  1878. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1879. goto err;
  1880. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1881. goto err;
  1882. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1883. goto err;
  1884. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1885. goto err;
  1886. return tmg_lock;
  1887. err:
  1888. dprintk(FE_ERROR, 1, "I/O error");
  1889. return -1;
  1890. }
  1891. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1892. {
  1893. struct dvb_frontend *fe = &state->frontend;
  1894. u32 reg;
  1895. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1896. int lock = 0;
  1897. if (state->srate >= 10000000)
  1898. timeout_lock = timeout_dmd / 3;
  1899. else
  1900. timeout_lock = timeout_dmd / 2;
  1901. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1902. if (!lock) {
  1903. if (state->srate >= 10000000) {
  1904. if (stv090x_chk_tmg(state)) {
  1905. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1906. goto err;
  1907. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1908. goto err;
  1909. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1910. } else {
  1911. lock = 0;
  1912. }
  1913. } else {
  1914. if (state->srate <= 4000000)
  1915. car_step = 1000;
  1916. else if (state->srate <= 7000000)
  1917. car_step = 2000;
  1918. else if (state->srate <= 10000000)
  1919. car_step = 3000;
  1920. else
  1921. car_step = 5000;
  1922. steps = (state->search_range / 1000) / car_step;
  1923. steps /= 2;
  1924. steps = 2 * (steps + 1);
  1925. if (steps < 0)
  1926. steps = 2;
  1927. else if (steps > 12)
  1928. steps = 12;
  1929. cur_step = 1;
  1930. dir = 1;
  1931. if (!lock) {
  1932. freq = state->frequency;
  1933. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1934. while ((cur_step <= steps) && (!lock)) {
  1935. if (dir > 0)
  1936. freq += cur_step * car_step;
  1937. else
  1938. freq -= cur_step * car_step;
  1939. /* Setup tuner */
  1940. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1941. goto err;
  1942. if (state->config->tuner_set_frequency) {
  1943. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1944. goto err_gateoff;
  1945. }
  1946. if (state->config->tuner_set_bandwidth) {
  1947. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1948. goto err_gateoff;
  1949. }
  1950. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1951. goto err;
  1952. msleep(50);
  1953. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1954. goto err;
  1955. if (state->config->tuner_get_status) {
  1956. if (state->config->tuner_get_status(fe, &reg) < 0)
  1957. goto err_gateoff;
  1958. }
  1959. if (reg)
  1960. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1961. else
  1962. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1963. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1964. goto err;
  1965. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1966. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1967. goto err;
  1968. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1969. goto err;
  1970. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1971. goto err;
  1972. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1973. goto err;
  1974. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1975. dir *= -1;
  1976. cur_step++;
  1977. }
  1978. }
  1979. }
  1980. }
  1981. return lock;
  1982. err_gateoff:
  1983. stv090x_i2c_gate_ctrl(fe, 0);
  1984. err:
  1985. dprintk(FE_ERROR, 1, "I/O error");
  1986. return -1;
  1987. }
  1988. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1989. {
  1990. s32 timeout, inc, steps_max, srate, car_max;
  1991. srate = state->srate;
  1992. car_max = state->search_range / 1000;
  1993. car_max += car_max / 10;
  1994. car_max = 65536 * (car_max / 2);
  1995. car_max /= (state->internal->mclk / 1000);
  1996. if (car_max > 0x4000)
  1997. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  1998. inc = srate;
  1999. inc /= state->internal->mclk / 1000;
  2000. inc *= 256;
  2001. inc *= 256;
  2002. inc /= 1000;
  2003. switch (state->search_mode) {
  2004. case STV090x_SEARCH_DVBS1:
  2005. case STV090x_SEARCH_DSS:
  2006. inc *= 3; /* freq step = 3% of srate */
  2007. timeout = 20;
  2008. break;
  2009. case STV090x_SEARCH_DVBS2:
  2010. inc *= 4;
  2011. timeout = 25;
  2012. break;
  2013. case STV090x_SEARCH_AUTO:
  2014. default:
  2015. inc *= 3;
  2016. timeout = 25;
  2017. break;
  2018. }
  2019. inc /= 100;
  2020. if ((inc > car_max) || (inc < 0))
  2021. inc = car_max / 2; /* increment <= 1/8 Mclk */
  2022. timeout *= 27500; /* 27.5 Msps reference */
  2023. if (srate > 0)
  2024. timeout /= (srate / 1000);
  2025. if ((timeout > 100) || (timeout < 0))
  2026. timeout = 100;
  2027. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  2028. if ((steps_max > 100) || (steps_max < 0)) {
  2029. steps_max = 100; /* max steps <= 100 */
  2030. inc = car_max / steps_max;
  2031. }
  2032. *freq_inc = inc;
  2033. *timeout_sw = timeout;
  2034. *steps = steps_max;
  2035. return 0;
  2036. }
  2037. static int stv090x_chk_signal(struct stv090x_state *state)
  2038. {
  2039. s32 offst_car, agc2, car_max;
  2040. int no_signal;
  2041. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  2042. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  2043. offst_car = comp2(offst_car, 16);
  2044. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  2045. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  2046. car_max = state->search_range / 1000;
  2047. car_max += (car_max / 10); /* 10% margin */
  2048. car_max = (65536 * car_max / 2);
  2049. car_max /= state->internal->mclk / 1000;
  2050. if (car_max > 0x4000)
  2051. car_max = 0x4000;
  2052. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  2053. no_signal = 1;
  2054. dprintk(FE_DEBUG, 1, "No Signal");
  2055. } else {
  2056. no_signal = 0;
  2057. dprintk(FE_DEBUG, 1, "Found Signal");
  2058. }
  2059. return no_signal;
  2060. }
  2061. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  2062. {
  2063. int no_signal, lock = 0;
  2064. s32 cpt_step = 0, offst_freq, car_max;
  2065. u32 reg;
  2066. car_max = state->search_range / 1000;
  2067. car_max += (car_max / 10);
  2068. car_max = (65536 * car_max / 2);
  2069. car_max /= (state->internal->mclk / 1000);
  2070. if (car_max > 0x4000)
  2071. car_max = 0x4000;
  2072. if (zigzag)
  2073. offst_freq = 0;
  2074. else
  2075. offst_freq = -car_max + inc;
  2076. do {
  2077. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2078. goto err;
  2079. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  2080. goto err;
  2081. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  2082. goto err;
  2083. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2084. goto err;
  2085. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2086. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  2087. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2088. goto err;
  2089. if (zigzag) {
  2090. if (offst_freq >= 0)
  2091. offst_freq = -offst_freq - 2 * inc;
  2092. else
  2093. offst_freq = -offst_freq;
  2094. } else {
  2095. offst_freq += 2 * inc;
  2096. }
  2097. cpt_step++;
  2098. lock = stv090x_get_dmdlock(state, timeout);
  2099. no_signal = stv090x_chk_signal(state);
  2100. } while ((!lock) &&
  2101. (!no_signal) &&
  2102. ((offst_freq - inc) < car_max) &&
  2103. ((offst_freq + inc) > -car_max) &&
  2104. (cpt_step < steps_max));
  2105. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2106. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  2107. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2108. goto err;
  2109. return lock;
  2110. err:
  2111. dprintk(FE_ERROR, 1, "I/O error");
  2112. return -1;
  2113. }
  2114. static int stv090x_sw_algo(struct stv090x_state *state)
  2115. {
  2116. int no_signal, zigzag, lock = 0;
  2117. u32 reg;
  2118. s32 dvbs2_fly_wheel;
  2119. s32 inc, timeout_step, trials, steps_max;
  2120. /* get params */
  2121. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
  2122. switch (state->search_mode) {
  2123. case STV090x_SEARCH_DVBS1:
  2124. case STV090x_SEARCH_DSS:
  2125. /* accelerate the frequency detector */
  2126. if (state->internal->dev_ver >= 0x20) {
  2127. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  2128. goto err;
  2129. }
  2130. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  2131. goto err;
  2132. zigzag = 0;
  2133. break;
  2134. case STV090x_SEARCH_DVBS2:
  2135. if (state->internal->dev_ver >= 0x20) {
  2136. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2137. goto err;
  2138. }
  2139. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2140. goto err;
  2141. zigzag = 1;
  2142. break;
  2143. case STV090x_SEARCH_AUTO:
  2144. default:
  2145. /* accelerate the frequency detector */
  2146. if (state->internal->dev_ver >= 0x20) {
  2147. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  2148. goto err;
  2149. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2150. goto err;
  2151. }
  2152. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  2153. goto err;
  2154. zigzag = 0;
  2155. break;
  2156. }
  2157. trials = 0;
  2158. do {
  2159. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  2160. no_signal = stv090x_chk_signal(state);
  2161. trials++;
  2162. /*run the SW search 2 times maximum*/
  2163. if (lock || no_signal || (trials == 2)) {
  2164. /*Check if the demod is not losing lock in DVBS2*/
  2165. if (state->internal->dev_ver >= 0x20) {
  2166. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2167. goto err;
  2168. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2169. goto err;
  2170. }
  2171. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2172. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  2173. /*Check if the demod is not losing lock in DVBS2*/
  2174. msleep(timeout_step);
  2175. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2176. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2177. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  2178. msleep(timeout_step);
  2179. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2180. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2181. }
  2182. if (dvbs2_fly_wheel < 0xd) {
  2183. /*FALSE lock, The demod is loosing lock */
  2184. lock = 0;
  2185. if (trials < 2) {
  2186. if (state->internal->dev_ver >= 0x20) {
  2187. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2188. goto err;
  2189. }
  2190. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2191. goto err;
  2192. }
  2193. }
  2194. }
  2195. }
  2196. } while ((!lock) && (trials < 2) && (!no_signal));
  2197. return lock;
  2198. err:
  2199. dprintk(FE_ERROR, 1, "I/O error");
  2200. return -1;
  2201. }
  2202. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  2203. {
  2204. u32 reg;
  2205. enum stv090x_delsys delsys;
  2206. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2207. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  2208. delsys = STV090x_DVBS2;
  2209. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  2210. reg = STV090x_READ_DEMOD(state, FECM);
  2211. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  2212. delsys = STV090x_DSS;
  2213. else
  2214. delsys = STV090x_DVBS1;
  2215. } else {
  2216. delsys = STV090x_ERROR;
  2217. }
  2218. return delsys;
  2219. }
  2220. /* in Hz */
  2221. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2222. {
  2223. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2224. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2225. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2226. derot |= STV090x_READ_DEMOD(state, CFR0);
  2227. derot = comp2(derot, 24);
  2228. int_1 = mclk >> 12;
  2229. int_2 = derot >> 12;
  2230. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2231. tmp_1 = mclk % 0x1000;
  2232. tmp_2 = derot % 0x1000;
  2233. derot = (int_1 * int_2) +
  2234. ((int_1 * tmp_2) >> 12) +
  2235. ((int_2 * tmp_1) >> 12);
  2236. return derot;
  2237. }
  2238. static int stv090x_get_viterbi(struct stv090x_state *state)
  2239. {
  2240. u32 reg, rate;
  2241. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2242. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2243. switch (rate) {
  2244. case 13:
  2245. state->fec = STV090x_PR12;
  2246. break;
  2247. case 18:
  2248. state->fec = STV090x_PR23;
  2249. break;
  2250. case 21:
  2251. state->fec = STV090x_PR34;
  2252. break;
  2253. case 24:
  2254. state->fec = STV090x_PR56;
  2255. break;
  2256. case 25:
  2257. state->fec = STV090x_PR67;
  2258. break;
  2259. case 26:
  2260. state->fec = STV090x_PR78;
  2261. break;
  2262. default:
  2263. state->fec = STV090x_PRERR;
  2264. break;
  2265. }
  2266. return 0;
  2267. }
  2268. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2269. {
  2270. struct dvb_frontend *fe = &state->frontend;
  2271. u8 tmg;
  2272. u32 reg;
  2273. s32 i = 0, offst_freq;
  2274. msleep(5);
  2275. if (state->algo == STV090x_BLIND_SEARCH) {
  2276. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2277. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2278. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2279. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2280. msleep(5);
  2281. i += 5;
  2282. }
  2283. }
  2284. state->delsys = stv090x_get_std(state);
  2285. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2286. goto err;
  2287. if (state->config->tuner_get_frequency) {
  2288. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2289. goto err_gateoff;
  2290. }
  2291. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2292. goto err;
  2293. offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
  2294. state->frequency += offst_freq;
  2295. if (stv090x_get_viterbi(state) < 0)
  2296. goto err;
  2297. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2298. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2299. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2300. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2301. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2302. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2303. reg = STV090x_READ_DEMOD(state, FECM);
  2304. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2305. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2306. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2307. goto err;
  2308. if (state->config->tuner_get_frequency) {
  2309. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2310. goto err_gateoff;
  2311. }
  2312. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2313. goto err;
  2314. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2315. return STV090x_RANGEOK;
  2316. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2317. return STV090x_RANGEOK;
  2318. else
  2319. return STV090x_OUTOFRANGE; /* Out of Range */
  2320. } else {
  2321. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2322. return STV090x_RANGEOK;
  2323. else
  2324. return STV090x_OUTOFRANGE;
  2325. }
  2326. return STV090x_OUTOFRANGE;
  2327. err_gateoff:
  2328. stv090x_i2c_gate_ctrl(fe, 0);
  2329. err:
  2330. dprintk(FE_ERROR, 1, "I/O error");
  2331. return -1;
  2332. }
  2333. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2334. {
  2335. s32 offst_tmg;
  2336. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2337. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2338. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2339. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2340. if (!offst_tmg)
  2341. offst_tmg = 1;
  2342. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2343. offst_tmg /= 320;
  2344. return offst_tmg;
  2345. }
  2346. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2347. {
  2348. u8 aclc = 0x29;
  2349. s32 i;
  2350. struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
  2351. if (state->internal->dev_ver == 0x20) {
  2352. car_loop = stv090x_s2_crl_cut20;
  2353. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
  2354. car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
  2355. } else {
  2356. /* >= Cut 3 */
  2357. car_loop = stv090x_s2_crl_cut30;
  2358. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
  2359. car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
  2360. }
  2361. if (modcod < STV090x_QPSK_12) {
  2362. i = 0;
  2363. while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
  2364. i++;
  2365. if (i >= 3)
  2366. i = 2;
  2367. } else {
  2368. i = 0;
  2369. while ((i < 14) && (modcod != car_loop[i].modcod))
  2370. i++;
  2371. if (i >= 14) {
  2372. i = 0;
  2373. while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
  2374. i++;
  2375. if (i >= 11)
  2376. i = 10;
  2377. }
  2378. }
  2379. if (modcod <= STV090x_QPSK_25) {
  2380. if (pilots) {
  2381. if (state->srate <= 3000000)
  2382. aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
  2383. else if (state->srate <= 7000000)
  2384. aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
  2385. else if (state->srate <= 15000000)
  2386. aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
  2387. else if (state->srate <= 25000000)
  2388. aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
  2389. else
  2390. aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
  2391. } else {
  2392. if (state->srate <= 3000000)
  2393. aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
  2394. else if (state->srate <= 7000000)
  2395. aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
  2396. else if (state->srate <= 15000000)
  2397. aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
  2398. else if (state->srate <= 25000000)
  2399. aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
  2400. else
  2401. aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
  2402. }
  2403. } else if (modcod <= STV090x_8PSK_910) {
  2404. if (pilots) {
  2405. if (state->srate <= 3000000)
  2406. aclc = car_loop[i].crl_pilots_on_2;
  2407. else if (state->srate <= 7000000)
  2408. aclc = car_loop[i].crl_pilots_on_5;
  2409. else if (state->srate <= 15000000)
  2410. aclc = car_loop[i].crl_pilots_on_10;
  2411. else if (state->srate <= 25000000)
  2412. aclc = car_loop[i].crl_pilots_on_20;
  2413. else
  2414. aclc = car_loop[i].crl_pilots_on_30;
  2415. } else {
  2416. if (state->srate <= 3000000)
  2417. aclc = car_loop[i].crl_pilots_off_2;
  2418. else if (state->srate <= 7000000)
  2419. aclc = car_loop[i].crl_pilots_off_5;
  2420. else if (state->srate <= 15000000)
  2421. aclc = car_loop[i].crl_pilots_off_10;
  2422. else if (state->srate <= 25000000)
  2423. aclc = car_loop[i].crl_pilots_off_20;
  2424. else
  2425. aclc = car_loop[i].crl_pilots_off_30;
  2426. }
  2427. } else { /* 16APSK and 32APSK */
  2428. if (state->srate <= 3000000)
  2429. aclc = car_loop_apsk_low[i].crl_pilots_on_2;
  2430. else if (state->srate <= 7000000)
  2431. aclc = car_loop_apsk_low[i].crl_pilots_on_5;
  2432. else if (state->srate <= 15000000)
  2433. aclc = car_loop_apsk_low[i].crl_pilots_on_10;
  2434. else if (state->srate <= 25000000)
  2435. aclc = car_loop_apsk_low[i].crl_pilots_on_20;
  2436. else
  2437. aclc = car_loop_apsk_low[i].crl_pilots_on_30;
  2438. }
  2439. return aclc;
  2440. }
  2441. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2442. {
  2443. struct stv090x_short_frame_crloop *short_crl = NULL;
  2444. s32 index = 0;
  2445. u8 aclc = 0x0b;
  2446. switch (state->modulation) {
  2447. case STV090x_QPSK:
  2448. default:
  2449. index = 0;
  2450. break;
  2451. case STV090x_8PSK:
  2452. index = 1;
  2453. break;
  2454. case STV090x_16APSK:
  2455. index = 2;
  2456. break;
  2457. case STV090x_32APSK:
  2458. index = 3;
  2459. break;
  2460. }
  2461. if (state->internal->dev_ver >= 0x30) {
  2462. /* Cut 3.0 and up */
  2463. short_crl = stv090x_s2_short_crl_cut30;
  2464. } else {
  2465. /* Cut 2.0 and up: we don't support cuts older than 2.0 */
  2466. short_crl = stv090x_s2_short_crl_cut20;
  2467. }
  2468. if (state->srate <= 3000000)
  2469. aclc = short_crl[index].crl_2;
  2470. else if (state->srate <= 7000000)
  2471. aclc = short_crl[index].crl_5;
  2472. else if (state->srate <= 15000000)
  2473. aclc = short_crl[index].crl_10;
  2474. else if (state->srate <= 25000000)
  2475. aclc = short_crl[index].crl_20;
  2476. else
  2477. aclc = short_crl[index].crl_30;
  2478. return aclc;
  2479. }
  2480. static int stv090x_optimize_track(struct stv090x_state *state)
  2481. {
  2482. struct dvb_frontend *fe = &state->frontend;
  2483. enum stv090x_rolloff rolloff;
  2484. enum stv090x_modcod modcod;
  2485. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2486. u32 reg;
  2487. srate = stv090x_get_srate(state, state->internal->mclk);
  2488. srate += stv090x_get_tmgoffst(state, srate);
  2489. switch (state->delsys) {
  2490. case STV090x_DVBS1:
  2491. case STV090x_DSS:
  2492. if (state->search_mode == STV090x_SEARCH_AUTO) {
  2493. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2494. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2495. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2496. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2497. goto err;
  2498. }
  2499. reg = STV090x_READ_DEMOD(state, DEMOD);
  2500. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2501. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
  2502. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2503. goto err;
  2504. if (state->internal->dev_ver >= 0x30) {
  2505. if (stv090x_get_viterbi(state) < 0)
  2506. goto err;
  2507. if (state->fec == STV090x_PR12) {
  2508. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
  2509. goto err;
  2510. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2511. goto err;
  2512. } else {
  2513. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
  2514. goto err;
  2515. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2516. goto err;
  2517. }
  2518. }
  2519. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2520. goto err;
  2521. break;
  2522. case STV090x_DVBS2:
  2523. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2524. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2525. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2526. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2527. goto err;
  2528. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2529. goto err;
  2530. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2531. goto err;
  2532. if (state->frame_len == STV090x_LONG_FRAME) {
  2533. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2534. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2535. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2536. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2537. if (modcod <= STV090x_QPSK_910) {
  2538. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2539. } else if (modcod <= STV090x_8PSK_910) {
  2540. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2541. goto err;
  2542. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2543. goto err;
  2544. }
  2545. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2546. if (modcod <= STV090x_16APSK_910) {
  2547. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2548. goto err;
  2549. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2550. goto err;
  2551. } else {
  2552. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2553. goto err;
  2554. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2555. goto err;
  2556. }
  2557. }
  2558. } else {
  2559. /*Carrier loop setting for short frame*/
  2560. aclc = stv090x_optimize_carloop_short(state);
  2561. if (state->modulation == STV090x_QPSK) {
  2562. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2563. goto err;
  2564. } else if (state->modulation == STV090x_8PSK) {
  2565. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2566. goto err;
  2567. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2568. goto err;
  2569. } else if (state->modulation == STV090x_16APSK) {
  2570. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2571. goto err;
  2572. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2573. goto err;
  2574. } else if (state->modulation == STV090x_32APSK) {
  2575. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2576. goto err;
  2577. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2578. goto err;
  2579. }
  2580. }
  2581. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2582. break;
  2583. case STV090x_UNKNOWN:
  2584. default:
  2585. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2586. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2587. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2588. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2589. goto err;
  2590. break;
  2591. }
  2592. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2593. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2594. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2595. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2596. if (state->algo == STV090x_BLIND_SEARCH) {
  2597. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2598. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2599. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2600. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2601. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2602. goto err;
  2603. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  2604. goto err;
  2605. if (stv090x_set_srate(state, srate) < 0)
  2606. goto err;
  2607. blind_tune = 1;
  2608. if (stv090x_dvbs_track_crl(state) < 0)
  2609. goto err;
  2610. }
  2611. if (state->internal->dev_ver >= 0x20) {
  2612. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2613. (state->search_mode == STV090x_SEARCH_DSS) ||
  2614. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2615. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2616. goto err;
  2617. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2618. goto err;
  2619. }
  2620. }
  2621. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2622. goto err;
  2623. /* AUTO tracking MODE */
  2624. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
  2625. goto err;
  2626. /* AUTO tracking MODE */
  2627. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
  2628. goto err;
  2629. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
  2630. (state->srate < 10000000)) {
  2631. /* update initial carrier freq with the found freq offset */
  2632. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2633. goto err;
  2634. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2635. goto err;
  2636. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2637. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
  2638. if (state->algo != STV090x_WARM_SEARCH) {
  2639. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2640. goto err;
  2641. if (state->config->tuner_set_bandwidth) {
  2642. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2643. goto err_gateoff;
  2644. }
  2645. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2646. goto err;
  2647. }
  2648. }
  2649. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2650. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2651. else
  2652. msleep(5);
  2653. stv090x_get_lock_tmg(state);
  2654. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2655. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2656. goto err;
  2657. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2658. goto err;
  2659. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2660. goto err;
  2661. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2662. goto err;
  2663. i = 0;
  2664. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2665. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2666. goto err;
  2667. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2668. goto err;
  2669. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2670. goto err;
  2671. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2672. goto err;
  2673. i++;
  2674. }
  2675. }
  2676. }
  2677. if (state->internal->dev_ver >= 0x20) {
  2678. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2679. goto err;
  2680. }
  2681. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2682. stv090x_set_vit_thtracq(state);
  2683. return 0;
  2684. err_gateoff:
  2685. stv090x_i2c_gate_ctrl(fe, 0);
  2686. err:
  2687. dprintk(FE_ERROR, 1, "I/O error");
  2688. return -1;
  2689. }
  2690. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2691. {
  2692. s32 timer = 0, lock = 0, stat;
  2693. u32 reg;
  2694. while ((timer < timeout) && (!lock)) {
  2695. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2696. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2697. switch (stat) {
  2698. case 0: /* searching */
  2699. case 1: /* first PLH detected */
  2700. default:
  2701. lock = 0;
  2702. break;
  2703. case 2: /* DVB-S2 mode */
  2704. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2705. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2706. break;
  2707. case 3: /* DVB-S1/legacy mode */
  2708. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2709. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2710. break;
  2711. }
  2712. if (!lock) {
  2713. msleep(10);
  2714. timer += 10;
  2715. }
  2716. }
  2717. return lock;
  2718. }
  2719. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2720. {
  2721. u32 reg;
  2722. s32 timer = 0;
  2723. int lock;
  2724. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2725. if (lock)
  2726. lock = stv090x_get_feclock(state, timeout_fec);
  2727. if (lock) {
  2728. lock = 0;
  2729. while ((timer < timeout_fec) && (!lock)) {
  2730. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2731. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2732. msleep(1);
  2733. timer++;
  2734. }
  2735. }
  2736. return lock;
  2737. }
  2738. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2739. {
  2740. u32 reg;
  2741. if (state->internal->dev_ver <= 0x20) {
  2742. /* rolloff to auto mode if DVBS2 */
  2743. reg = STV090x_READ_DEMOD(state, DEMOD);
  2744. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
  2745. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2746. goto err;
  2747. } else {
  2748. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2749. reg = STV090x_READ_DEMOD(state, DEMOD);
  2750. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
  2751. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2752. goto err;
  2753. }
  2754. return 0;
  2755. err:
  2756. dprintk(FE_ERROR, 1, "I/O error");
  2757. return -1;
  2758. }
  2759. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2760. {
  2761. struct dvb_frontend *fe = &state->frontend;
  2762. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2763. u32 reg;
  2764. s32 agc1_power, power_iq = 0, i;
  2765. int lock = 0, low_sr = 0, no_signal = 0;
  2766. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2767. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2768. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2769. goto err;
  2770. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2771. goto err;
  2772. if (state->internal->dev_ver >= 0x20) {
  2773. if (state->srate > 5000000) {
  2774. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2775. goto err;
  2776. } else {
  2777. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
  2778. goto err;
  2779. }
  2780. }
  2781. stv090x_get_lock_tmg(state);
  2782. if (state->algo == STV090x_BLIND_SEARCH) {
  2783. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2784. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
  2785. goto err;
  2786. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2787. goto err;
  2788. if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
  2789. goto err;
  2790. } else {
  2791. /* known srate */
  2792. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2793. goto err;
  2794. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2795. goto err;
  2796. if (state->srate < 2000000) {
  2797. /* SR < 2MSPS */
  2798. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
  2799. goto err;
  2800. } else {
  2801. /* SR >= 2Msps */
  2802. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2803. goto err;
  2804. }
  2805. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2806. goto err;
  2807. if (state->internal->dev_ver >= 0x20) {
  2808. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2809. goto err;
  2810. if (state->algo == STV090x_COLD_SEARCH)
  2811. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2812. else if (state->algo == STV090x_WARM_SEARCH)
  2813. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2814. }
  2815. /* if cold start or warm (Symbolrate is known)
  2816. * use a Narrow symbol rate scan range
  2817. */
  2818. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
  2819. goto err;
  2820. if (stv090x_set_srate(state, state->srate) < 0)
  2821. goto err;
  2822. if (stv090x_set_max_srate(state, state->internal->mclk,
  2823. state->srate) < 0)
  2824. goto err;
  2825. if (stv090x_set_min_srate(state, state->internal->mclk,
  2826. state->srate) < 0)
  2827. goto err;
  2828. if (state->srate >= 10000000)
  2829. low_sr = 0;
  2830. else
  2831. low_sr = 1;
  2832. }
  2833. /* Setup tuner */
  2834. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2835. goto err;
  2836. if (state->config->tuner_set_bbgain) {
  2837. reg = state->config->tuner_bbgain;
  2838. if (reg == 0)
  2839. reg = 10; /* default: 10dB */
  2840. if (state->config->tuner_set_bbgain(fe, reg) < 0)
  2841. goto err_gateoff;
  2842. }
  2843. if (state->config->tuner_set_frequency) {
  2844. if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
  2845. goto err_gateoff;
  2846. }
  2847. if (state->config->tuner_set_bandwidth) {
  2848. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2849. goto err_gateoff;
  2850. }
  2851. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2852. goto err;
  2853. msleep(50);
  2854. if (state->config->tuner_get_status) {
  2855. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2856. goto err;
  2857. if (state->config->tuner_get_status(fe, &reg) < 0)
  2858. goto err_gateoff;
  2859. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2860. goto err;
  2861. if (reg)
  2862. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2863. else {
  2864. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2865. return STV090x_NOCARRIER;
  2866. }
  2867. }
  2868. msleep(10);
  2869. agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
  2870. STV090x_READ_DEMOD(state, AGCIQIN0));
  2871. if (agc1_power == 0) {
  2872. /* If AGC1 integrator value is 0
  2873. * then read POWERI, POWERQ
  2874. */
  2875. for (i = 0; i < 5; i++) {
  2876. power_iq += (STV090x_READ_DEMOD(state, POWERI) +
  2877. STV090x_READ_DEMOD(state, POWERQ)) >> 1;
  2878. }
  2879. power_iq /= 5;
  2880. }
  2881. if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
  2882. dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
  2883. lock = 0;
  2884. signal_state = STV090x_NOAGC1;
  2885. } else {
  2886. reg = STV090x_READ_DEMOD(state, DEMOD);
  2887. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2888. if (state->internal->dev_ver <= 0x20) {
  2889. /* rolloff to auto mode if DVBS2 */
  2890. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
  2891. } else {
  2892. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2893. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
  2894. }
  2895. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2896. goto err;
  2897. if (stv090x_delivery_search(state) < 0)
  2898. goto err;
  2899. if (state->algo != STV090x_BLIND_SEARCH) {
  2900. if (stv090x_start_search(state) < 0)
  2901. goto err;
  2902. }
  2903. }
  2904. if (signal_state == STV090x_NOAGC1)
  2905. return signal_state;
  2906. if (state->algo == STV090x_BLIND_SEARCH)
  2907. lock = stv090x_blind_search(state);
  2908. else if (state->algo == STV090x_COLD_SEARCH)
  2909. lock = stv090x_get_coldlock(state, state->DemodTimeout);
  2910. else if (state->algo == STV090x_WARM_SEARCH)
  2911. lock = stv090x_get_dmdlock(state, state->DemodTimeout);
  2912. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2913. if (!low_sr) {
  2914. if (stv090x_chk_tmg(state))
  2915. lock = stv090x_sw_algo(state);
  2916. }
  2917. }
  2918. if (lock)
  2919. signal_state = stv090x_get_sig_params(state);
  2920. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2921. stv090x_optimize_track(state);
  2922. if (state->internal->dev_ver >= 0x20) {
  2923. /* >= Cut 2.0 :release TS reset after
  2924. * demod lock and optimized Tracking
  2925. */
  2926. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2927. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2928. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2929. goto err;
  2930. msleep(3);
  2931. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2932. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2933. goto err;
  2934. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2935. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2936. goto err;
  2937. }
  2938. lock = stv090x_get_lock(state, state->FecTimeout,
  2939. state->FecTimeout);
  2940. if (lock) {
  2941. if (state->delsys == STV090x_DVBS2) {
  2942. stv090x_set_s2rolloff(state);
  2943. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2944. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
  2945. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2946. goto err;
  2947. /* Reset DVBS2 packet delinator error counter */
  2948. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2949. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
  2950. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2951. goto err;
  2952. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2953. goto err;
  2954. } else {
  2955. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2956. goto err;
  2957. }
  2958. /* Reset the Total packet counter */
  2959. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2960. goto err;
  2961. /* Reset the packet Error counter2 */
  2962. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2963. goto err;
  2964. } else {
  2965. signal_state = STV090x_NODATA;
  2966. no_signal = stv090x_chk_signal(state);
  2967. }
  2968. }
  2969. return signal_state;
  2970. err_gateoff:
  2971. stv090x_i2c_gate_ctrl(fe, 0);
  2972. err:
  2973. dprintk(FE_ERROR, 1, "I/O error");
  2974. return -1;
  2975. }
  2976. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2977. {
  2978. struct stv090x_state *state = fe->demodulator_priv;
  2979. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2980. if (p->frequency == 0)
  2981. return DVBFE_ALGO_SEARCH_INVALID;
  2982. state->delsys = props->delivery_system;
  2983. state->frequency = p->frequency;
  2984. state->srate = p->u.qpsk.symbol_rate;
  2985. state->search_mode = STV090x_SEARCH_AUTO;
  2986. state->algo = STV090x_COLD_SEARCH;
  2987. state->fec = STV090x_PRERR;
  2988. if (state->srate > 10000000) {
  2989. dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
  2990. state->search_range = 10000000;
  2991. } else {
  2992. dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
  2993. state->search_range = 5000000;
  2994. }
  2995. if (stv090x_algo(state) == STV090x_RANGEOK) {
  2996. dprintk(FE_DEBUG, 1, "Search success!");
  2997. return DVBFE_ALGO_SEARCH_SUCCESS;
  2998. } else {
  2999. dprintk(FE_DEBUG, 1, "Search failed!");
  3000. return DVBFE_ALGO_SEARCH_FAILED;
  3001. }
  3002. return DVBFE_ALGO_SEARCH_ERROR;
  3003. }
  3004. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  3005. {
  3006. struct stv090x_state *state = fe->demodulator_priv;
  3007. u32 reg;
  3008. u8 search_state;
  3009. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  3010. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  3011. switch (search_state) {
  3012. case 0: /* searching */
  3013. case 1: /* first PLH detected */
  3014. default:
  3015. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  3016. *status = 0;
  3017. break;
  3018. case 2: /* DVB-S2 mode */
  3019. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  3020. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3021. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3022. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  3023. if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
  3024. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3025. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3026. *status = FE_HAS_SIGNAL |
  3027. FE_HAS_CARRIER |
  3028. FE_HAS_VITERBI |
  3029. FE_HAS_SYNC |
  3030. FE_HAS_LOCK;
  3031. }
  3032. }
  3033. }
  3034. break;
  3035. case 3: /* DVB-S1/legacy mode */
  3036. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  3037. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3038. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3039. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  3040. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  3041. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3042. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3043. *status = FE_HAS_SIGNAL |
  3044. FE_HAS_CARRIER |
  3045. FE_HAS_VITERBI |
  3046. FE_HAS_SYNC |
  3047. FE_HAS_LOCK;
  3048. }
  3049. }
  3050. }
  3051. break;
  3052. }
  3053. return 0;
  3054. }
  3055. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  3056. {
  3057. struct stv090x_state *state = fe->demodulator_priv;
  3058. s32 count_4, count_3, count_2, count_1, count_0, count;
  3059. u32 reg, h, m, l;
  3060. enum fe_status status;
  3061. stv090x_read_status(fe, &status);
  3062. if (!(status & FE_HAS_LOCK)) {
  3063. *per = 1 << 23; /* Max PER */
  3064. } else {
  3065. /* Counter 2 */
  3066. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  3067. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  3068. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  3069. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  3070. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  3071. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  3072. *per = ((h << 16) | (m << 8) | l);
  3073. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  3074. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  3075. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  3076. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  3077. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  3078. if ((!count_4) && (!count_3)) {
  3079. count = (count_2 & 0xff) << 16;
  3080. count |= (count_1 & 0xff) << 8;
  3081. count |= count_0 & 0xff;
  3082. } else {
  3083. count = 1 << 24;
  3084. }
  3085. if (count == 0)
  3086. *per = 1;
  3087. }
  3088. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  3089. goto err;
  3090. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  3091. goto err;
  3092. return 0;
  3093. err:
  3094. dprintk(FE_ERROR, 1, "I/O error");
  3095. return -1;
  3096. }
  3097. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  3098. {
  3099. int res = 0;
  3100. int min = 0, med;
  3101. if ((val >= tab[min].read && val < tab[max].read) ||
  3102. (val >= tab[max].read && val < tab[min].read)) {
  3103. while ((max - min) > 1) {
  3104. med = (max + min) / 2;
  3105. if ((val >= tab[min].read && val < tab[med].read) ||
  3106. (val >= tab[med].read && val < tab[min].read))
  3107. max = med;
  3108. else
  3109. min = med;
  3110. }
  3111. res = ((val - tab[min].read) *
  3112. (tab[max].real - tab[min].real) /
  3113. (tab[max].read - tab[min].read)) +
  3114. tab[min].real;
  3115. } else {
  3116. if (tab[min].read < tab[max].read) {
  3117. if (val < tab[min].read)
  3118. res = tab[min].real;
  3119. else if (val >= tab[max].read)
  3120. res = tab[max].real;
  3121. } else {
  3122. if (val >= tab[min].read)
  3123. res = tab[min].real;
  3124. else if (val < tab[max].read)
  3125. res = tab[max].real;
  3126. }
  3127. }
  3128. return res;
  3129. }
  3130. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  3131. {
  3132. struct stv090x_state *state = fe->demodulator_priv;
  3133. u32 reg;
  3134. s32 agc_0, agc_1, agc;
  3135. s32 str;
  3136. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  3137. agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3138. reg = STV090x_READ_DEMOD(state, AGCIQIN0);
  3139. agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3140. agc = MAKEWORD16(agc_1, agc_0);
  3141. str = stv090x_table_lookup(stv090x_rf_tab,
  3142. ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  3143. if (agc > stv090x_rf_tab[0].read)
  3144. str = 0;
  3145. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  3146. str = -100;
  3147. *strength = (str + 100) * 0xFFFF / 100;
  3148. return 0;
  3149. }
  3150. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  3151. {
  3152. struct stv090x_state *state = fe->demodulator_priv;
  3153. u32 reg_0, reg_1, reg, i;
  3154. s32 val_0, val_1, val = 0;
  3155. u8 lock_f;
  3156. s32 div;
  3157. u32 last;
  3158. switch (state->delsys) {
  3159. case STV090x_DVBS2:
  3160. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3161. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3162. if (lock_f) {
  3163. msleep(5);
  3164. for (i = 0; i < 16; i++) {
  3165. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  3166. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  3167. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  3168. val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
  3169. val += MAKEWORD16(val_1, val_0);
  3170. msleep(1);
  3171. }
  3172. val /= 16;
  3173. last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
  3174. div = stv090x_s2cn_tab[0].read -
  3175. stv090x_s2cn_tab[last].read;
  3176. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3177. }
  3178. break;
  3179. case STV090x_DVBS1:
  3180. case STV090x_DSS:
  3181. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3182. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3183. if (lock_f) {
  3184. msleep(5);
  3185. for (i = 0; i < 16; i++) {
  3186. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  3187. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  3188. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  3189. val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
  3190. val += MAKEWORD16(val_1, val_0);
  3191. msleep(1);
  3192. }
  3193. val /= 16;
  3194. last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
  3195. div = stv090x_s1cn_tab[0].read -
  3196. stv090x_s1cn_tab[last].read;
  3197. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3198. }
  3199. break;
  3200. default:
  3201. break;
  3202. }
  3203. return 0;
  3204. }
  3205. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  3206. {
  3207. struct stv090x_state *state = fe->demodulator_priv;
  3208. u32 reg;
  3209. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3210. switch (tone) {
  3211. case SEC_TONE_ON:
  3212. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3213. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3214. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3215. goto err;
  3216. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3217. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3218. goto err;
  3219. break;
  3220. case SEC_TONE_OFF:
  3221. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3222. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3223. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3224. goto err;
  3225. break;
  3226. default:
  3227. return -EINVAL;
  3228. }
  3229. return 0;
  3230. err:
  3231. dprintk(FE_ERROR, 1, "I/O error");
  3232. return -1;
  3233. }
  3234. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  3235. {
  3236. return DVBFE_ALGO_CUSTOM;
  3237. }
  3238. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  3239. {
  3240. struct stv090x_state *state = fe->demodulator_priv;
  3241. u32 reg, idle = 0, fifo_full = 1;
  3242. int i;
  3243. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3244. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
  3245. (state->config->diseqc_envelope_mode) ? 4 : 2);
  3246. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3247. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3248. goto err;
  3249. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3250. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3251. goto err;
  3252. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3253. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3254. goto err;
  3255. for (i = 0; i < cmd->msg_len; i++) {
  3256. while (fifo_full) {
  3257. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3258. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3259. }
  3260. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3261. goto err;
  3262. }
  3263. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3264. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3265. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3266. goto err;
  3267. i = 0;
  3268. while ((!idle) && (i < 10)) {
  3269. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3270. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3271. msleep(10);
  3272. i++;
  3273. }
  3274. return 0;
  3275. err:
  3276. dprintk(FE_ERROR, 1, "I/O error");
  3277. return -1;
  3278. }
  3279. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  3280. {
  3281. struct stv090x_state *state = fe->demodulator_priv;
  3282. u32 reg, idle = 0, fifo_full = 1;
  3283. u8 mode, value;
  3284. int i;
  3285. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3286. if (burst == SEC_MINI_A) {
  3287. mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
  3288. value = 0x00;
  3289. } else {
  3290. mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
  3291. value = 0xFF;
  3292. }
  3293. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3294. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3295. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3296. goto err;
  3297. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3298. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3299. goto err;
  3300. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3301. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3302. goto err;
  3303. while (fifo_full) {
  3304. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3305. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3306. }
  3307. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3308. goto err;
  3309. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3310. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3311. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3312. goto err;
  3313. i = 0;
  3314. while ((!idle) && (i < 10)) {
  3315. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3316. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3317. msleep(10);
  3318. i++;
  3319. }
  3320. return 0;
  3321. err:
  3322. dprintk(FE_ERROR, 1, "I/O error");
  3323. return -1;
  3324. }
  3325. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3326. {
  3327. struct stv090x_state *state = fe->demodulator_priv;
  3328. u32 reg = 0, i = 0, rx_end = 0;
  3329. while ((rx_end != 1) && (i < 10)) {
  3330. msleep(10);
  3331. i++;
  3332. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3333. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3334. }
  3335. if (rx_end) {
  3336. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3337. for (i = 0; i < reply->msg_len; i++)
  3338. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3339. }
  3340. return 0;
  3341. }
  3342. static int stv090x_sleep(struct dvb_frontend *fe)
  3343. {
  3344. struct stv090x_state *state = fe->demodulator_priv;
  3345. u32 reg;
  3346. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3347. state->device == STV0900 ? "STV0900" : "STV0903");
  3348. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3349. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3350. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3351. goto err;
  3352. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3353. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3354. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3355. goto err;
  3356. return 0;
  3357. err:
  3358. dprintk(FE_ERROR, 1, "I/O error");
  3359. return -1;
  3360. }
  3361. static int stv090x_wakeup(struct dvb_frontend *fe)
  3362. {
  3363. struct stv090x_state *state = fe->demodulator_priv;
  3364. u32 reg;
  3365. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3366. state->device == STV0900 ? "STV0900" : "STV0903");
  3367. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3368. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3369. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3370. goto err;
  3371. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3372. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3373. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3374. goto err;
  3375. return 0;
  3376. err:
  3377. dprintk(FE_ERROR, 1, "I/O error");
  3378. return -1;
  3379. }
  3380. static void stv090x_release(struct dvb_frontend *fe)
  3381. {
  3382. struct stv090x_state *state = fe->demodulator_priv;
  3383. state->internal->num_used--;
  3384. if (state->internal->num_used <= 0) {
  3385. dprintk(FE_ERROR, 1, "Actually removing");
  3386. remove_dev(state->internal);
  3387. kfree(state->internal);
  3388. }
  3389. kfree(state);
  3390. }
  3391. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3392. {
  3393. u32 reg = 0;
  3394. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3395. switch (ldpc_mode) {
  3396. case STV090x_DUAL:
  3397. default:
  3398. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3399. /* set LDPC to dual mode */
  3400. if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
  3401. goto err;
  3402. state->demod_mode = STV090x_DUAL;
  3403. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3404. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3405. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3406. goto err;
  3407. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3408. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3409. goto err;
  3410. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  3411. goto err;
  3412. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  3413. goto err;
  3414. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  3415. goto err;
  3416. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  3417. goto err;
  3418. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  3419. goto err;
  3420. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  3421. goto err;
  3422. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  3423. goto err;
  3424. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  3425. goto err;
  3426. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  3427. goto err;
  3428. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  3429. goto err;
  3430. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  3431. goto err;
  3432. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  3433. goto err;
  3434. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  3435. goto err;
  3436. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  3437. goto err;
  3438. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  3439. goto err;
  3440. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  3441. goto err;
  3442. }
  3443. break;
  3444. case STV090x_SINGLE:
  3445. if (stv090x_stop_modcod(state) < 0)
  3446. goto err;
  3447. if (stv090x_activate_modcod_single(state) < 0)
  3448. goto err;
  3449. if (state->demod == STV090x_DEMODULATOR_1) {
  3450. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3451. goto err;
  3452. } else {
  3453. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3454. goto err;
  3455. }
  3456. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3457. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3458. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3459. goto err;
  3460. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3461. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3462. goto err;
  3463. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3464. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3465. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3466. goto err;
  3467. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3468. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3469. goto err;
  3470. break;
  3471. }
  3472. return 0;
  3473. err:
  3474. dprintk(FE_ERROR, 1, "I/O error");
  3475. return -1;
  3476. }
  3477. /* return (Hz), clk in Hz*/
  3478. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3479. {
  3480. const struct stv090x_config *config = state->config;
  3481. u32 div, reg;
  3482. u8 ratio;
  3483. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3484. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3485. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3486. return (div + 1) * config->xtal / ratio; /* kHz */
  3487. }
  3488. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3489. {
  3490. const struct stv090x_config *config = state->config;
  3491. u32 reg, div, clk_sel;
  3492. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3493. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3494. div = ((clk_sel * mclk) / config->xtal) - 1;
  3495. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3496. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3497. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3498. goto err;
  3499. state->internal->mclk = stv090x_get_mclk(state);
  3500. /*Set the DiseqC frequency to 22KHz */
  3501. div = state->internal->mclk / 704000;
  3502. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3503. goto err;
  3504. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3505. goto err;
  3506. return 0;
  3507. err:
  3508. dprintk(FE_ERROR, 1, "I/O error");
  3509. return -1;
  3510. }
  3511. static int stv090x_set_tspath(struct stv090x_state *state)
  3512. {
  3513. u32 reg;
  3514. if (state->internal->dev_ver >= 0x20) {
  3515. switch (state->config->ts1_mode) {
  3516. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3517. case STV090x_TSMODE_DVBCI:
  3518. switch (state->config->ts2_mode) {
  3519. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3520. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3521. default:
  3522. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3523. break;
  3524. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3525. case STV090x_TSMODE_DVBCI:
  3526. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3527. goto err;
  3528. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3529. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3530. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3531. goto err;
  3532. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3533. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3534. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3535. goto err;
  3536. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3537. goto err;
  3538. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3539. goto err;
  3540. break;
  3541. }
  3542. break;
  3543. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3544. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3545. default:
  3546. switch (state->config->ts2_mode) {
  3547. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3548. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3549. default:
  3550. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3551. goto err;
  3552. break;
  3553. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3554. case STV090x_TSMODE_DVBCI:
  3555. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3556. goto err;
  3557. break;
  3558. }
  3559. break;
  3560. }
  3561. } else {
  3562. switch (state->config->ts1_mode) {
  3563. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3564. case STV090x_TSMODE_DVBCI:
  3565. switch (state->config->ts2_mode) {
  3566. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3567. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3568. default:
  3569. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3570. break;
  3571. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3572. case STV090x_TSMODE_DVBCI:
  3573. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3574. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3575. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3576. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3577. goto err;
  3578. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3579. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3580. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3581. goto err;
  3582. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3583. goto err;
  3584. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3585. goto err;
  3586. break;
  3587. }
  3588. break;
  3589. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3590. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3591. default:
  3592. switch (state->config->ts2_mode) {
  3593. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3594. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3595. default:
  3596. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3597. break;
  3598. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3599. case STV090x_TSMODE_DVBCI:
  3600. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3601. break;
  3602. }
  3603. break;
  3604. }
  3605. }
  3606. switch (state->config->ts1_mode) {
  3607. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3608. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3609. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3610. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3611. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3612. goto err;
  3613. break;
  3614. case STV090x_TSMODE_DVBCI:
  3615. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3616. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3617. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3618. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3619. goto err;
  3620. break;
  3621. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3622. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3623. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3624. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3625. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3626. goto err;
  3627. break;
  3628. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3629. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3630. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3631. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3632. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3633. goto err;
  3634. break;
  3635. default:
  3636. break;
  3637. }
  3638. switch (state->config->ts2_mode) {
  3639. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3640. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3641. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3642. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3643. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3644. goto err;
  3645. break;
  3646. case STV090x_TSMODE_DVBCI:
  3647. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3648. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3649. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3650. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3651. goto err;
  3652. break;
  3653. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3654. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3655. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3656. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3657. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3658. goto err;
  3659. break;
  3660. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3661. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3662. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3663. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3664. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3665. goto err;
  3666. break;
  3667. default:
  3668. break;
  3669. }
  3670. if (state->config->ts1_clk > 0) {
  3671. u32 speed;
  3672. switch (state->config->ts1_mode) {
  3673. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3674. case STV090x_TSMODE_DVBCI:
  3675. default:
  3676. speed = state->internal->mclk /
  3677. (state->config->ts1_clk / 4);
  3678. if (speed < 0x08)
  3679. speed = 0x08;
  3680. if (speed > 0xFF)
  3681. speed = 0xFF;
  3682. break;
  3683. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3684. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3685. speed = state->internal->mclk /
  3686. (state->config->ts1_clk / 32);
  3687. if (speed < 0x20)
  3688. speed = 0x20;
  3689. if (speed > 0xFF)
  3690. speed = 0xFF;
  3691. break;
  3692. }
  3693. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3694. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3695. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3696. goto err;
  3697. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
  3698. goto err;
  3699. }
  3700. if (state->config->ts2_clk > 0) {
  3701. u32 speed;
  3702. switch (state->config->ts2_mode) {
  3703. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3704. case STV090x_TSMODE_DVBCI:
  3705. default:
  3706. speed = state->internal->mclk /
  3707. (state->config->ts2_clk / 4);
  3708. if (speed < 0x08)
  3709. speed = 0x08;
  3710. if (speed > 0xFF)
  3711. speed = 0xFF;
  3712. break;
  3713. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3714. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3715. speed = state->internal->mclk /
  3716. (state->config->ts2_clk / 32);
  3717. if (speed < 0x20)
  3718. speed = 0x20;
  3719. if (speed > 0xFF)
  3720. speed = 0xFF;
  3721. break;
  3722. }
  3723. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3724. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3725. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3726. goto err;
  3727. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
  3728. goto err;
  3729. }
  3730. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3731. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3732. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3733. goto err;
  3734. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3735. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3736. goto err;
  3737. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3738. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3739. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3740. goto err;
  3741. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3742. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3743. goto err;
  3744. return 0;
  3745. err:
  3746. dprintk(FE_ERROR, 1, "I/O error");
  3747. return -1;
  3748. }
  3749. static int stv090x_init(struct dvb_frontend *fe)
  3750. {
  3751. struct stv090x_state *state = fe->demodulator_priv;
  3752. const struct stv090x_config *config = state->config;
  3753. u32 reg;
  3754. if (state->internal->mclk == 0) {
  3755. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3756. msleep(5);
  3757. if (stv090x_write_reg(state, STV090x_SYNTCTRL,
  3758. 0x20 | config->clk_mode) < 0)
  3759. goto err;
  3760. stv090x_get_mclk(state);
  3761. }
  3762. if (stv090x_wakeup(fe) < 0) {
  3763. dprintk(FE_ERROR, 1, "Error waking device");
  3764. goto err;
  3765. }
  3766. if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
  3767. goto err;
  3768. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3769. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3770. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3771. goto err;
  3772. reg = STV090x_READ_DEMOD(state, DEMOD);
  3773. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3774. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3775. goto err;
  3776. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  3777. goto err;
  3778. if (config->tuner_set_mode) {
  3779. if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
  3780. goto err_gateoff;
  3781. }
  3782. if (config->tuner_init) {
  3783. if (config->tuner_init(fe) < 0)
  3784. goto err_gateoff;
  3785. }
  3786. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  3787. goto err;
  3788. if (stv090x_set_tspath(state) < 0)
  3789. goto err;
  3790. return 0;
  3791. err_gateoff:
  3792. stv090x_i2c_gate_ctrl(fe, 0);
  3793. err:
  3794. dprintk(FE_ERROR, 1, "I/O error");
  3795. return -1;
  3796. }
  3797. static int stv090x_setup(struct dvb_frontend *fe)
  3798. {
  3799. struct stv090x_state *state = fe->demodulator_priv;
  3800. const struct stv090x_config *config = state->config;
  3801. const struct stv090x_reg *stv090x_initval = NULL;
  3802. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3803. unsigned long t1_size = 0, t2_size = 0;
  3804. u32 reg = 0;
  3805. int i;
  3806. if (state->device == STV0900) {
  3807. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3808. stv090x_initval = stv0900_initval;
  3809. t1_size = ARRAY_SIZE(stv0900_initval);
  3810. stv090x_cut20_val = stv0900_cut20_val;
  3811. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3812. } else if (state->device == STV0903) {
  3813. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3814. stv090x_initval = stv0903_initval;
  3815. t1_size = ARRAY_SIZE(stv0903_initval);
  3816. stv090x_cut20_val = stv0903_cut20_val;
  3817. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3818. }
  3819. /* STV090x init */
  3820. /* Stop Demod */
  3821. if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
  3822. goto err;
  3823. if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
  3824. goto err;
  3825. msleep(5);
  3826. /* Set No Tuner Mode */
  3827. if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
  3828. goto err;
  3829. if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
  3830. goto err;
  3831. /* I2C repeater OFF */
  3832. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3833. if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
  3834. goto err;
  3835. if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
  3836. goto err;
  3837. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3838. goto err;
  3839. msleep(5);
  3840. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3841. goto err;
  3842. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3843. goto err;
  3844. msleep(5);
  3845. /* write initval */
  3846. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3847. for (i = 0; i < t1_size; i++) {
  3848. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3849. goto err;
  3850. }
  3851. state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3852. if (state->internal->dev_ver >= 0x20) {
  3853. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3854. goto err;
  3855. /* write cut20_val*/
  3856. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3857. for (i = 0; i < t2_size; i++) {
  3858. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3859. goto err;
  3860. }
  3861. } else if (state->internal->dev_ver < 0x20) {
  3862. dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
  3863. state->internal->dev_ver);
  3864. goto err;
  3865. } else if (state->internal->dev_ver > 0x30) {
  3866. /* we shouldn't bail out from here */
  3867. dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
  3868. state->internal->dev_ver);
  3869. }
  3870. /* ADC1 range */
  3871. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3872. STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
  3873. (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3874. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3875. goto err;
  3876. /* ADC2 range */
  3877. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3878. STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
  3879. (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3880. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  3881. goto err;
  3882. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3883. goto err;
  3884. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3885. goto err;
  3886. return 0;
  3887. err:
  3888. dprintk(FE_ERROR, 1, "I/O error");
  3889. return -1;
  3890. }
  3891. static struct dvb_frontend_ops stv090x_ops = {
  3892. .info = {
  3893. .name = "STV090x Multistandard",
  3894. .type = FE_QPSK,
  3895. .frequency_min = 950000,
  3896. .frequency_max = 2150000,
  3897. .frequency_stepsize = 0,
  3898. .frequency_tolerance = 0,
  3899. .symbol_rate_min = 1000000,
  3900. .symbol_rate_max = 45000000,
  3901. .caps = FE_CAN_INVERSION_AUTO |
  3902. FE_CAN_FEC_AUTO |
  3903. FE_CAN_QPSK |
  3904. FE_CAN_2G_MODULATION
  3905. },
  3906. .release = stv090x_release,
  3907. .init = stv090x_init,
  3908. .sleep = stv090x_sleep,
  3909. .get_frontend_algo = stv090x_frontend_algo,
  3910. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3911. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3912. .diseqc_send_burst = stv090x_send_diseqc_burst,
  3913. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3914. .set_tone = stv090x_set_tone,
  3915. .search = stv090x_search,
  3916. .read_status = stv090x_read_status,
  3917. .read_ber = stv090x_read_per,
  3918. .read_signal_strength = stv090x_read_signal_strength,
  3919. .read_snr = stv090x_read_cnr
  3920. };
  3921. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3922. struct i2c_adapter *i2c,
  3923. enum stv090x_demodulator demod)
  3924. {
  3925. struct stv090x_state *state = NULL;
  3926. struct stv090x_dev *temp_int;
  3927. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3928. if (state == NULL)
  3929. goto error;
  3930. state->verbose = &verbose;
  3931. state->config = config;
  3932. state->i2c = i2c;
  3933. state->frontend.ops = stv090x_ops;
  3934. state->frontend.demodulator_priv = state;
  3935. state->demod = demod;
  3936. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3937. state->device = config->device;
  3938. state->rolloff = STV090x_RO_35; /* default */
  3939. temp_int = find_dev(state->i2c,
  3940. state->config->address);
  3941. if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
  3942. state->internal = temp_int->internal;
  3943. state->internal->num_used++;
  3944. dprintk(FE_INFO, 1, "Found Internal Structure!");
  3945. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3946. state->device == STV0900 ? "STV0900" : "STV0903",
  3947. demod,
  3948. state->internal->dev_ver);
  3949. return &state->frontend;
  3950. } else {
  3951. state->internal = kmalloc(sizeof(struct stv090x_internal),
  3952. GFP_KERNEL);
  3953. temp_int = append_internal(state->internal);
  3954. state->internal->num_used = 1;
  3955. state->internal->mclk = 0;
  3956. state->internal->dev_ver = 0;
  3957. state->internal->i2c_adap = state->i2c;
  3958. state->internal->i2c_addr = state->config->address;
  3959. dprintk(FE_INFO, 1, "Create New Internal Structure!");
  3960. }
  3961. mutex_init(&state->internal->demod_lock);
  3962. mutex_init(&state->internal->tuner_lock);
  3963. if (stv090x_sleep(&state->frontend) < 0) {
  3964. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3965. goto error;
  3966. }
  3967. if (stv090x_setup(&state->frontend) < 0) {
  3968. dprintk(FE_ERROR, 1, "Error setting up device");
  3969. goto error;
  3970. }
  3971. if (stv090x_wakeup(&state->frontend) < 0) {
  3972. dprintk(FE_ERROR, 1, "Error waking device");
  3973. goto error;
  3974. }
  3975. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3976. state->device == STV0900 ? "STV0900" : "STV0903",
  3977. demod,
  3978. state->internal->dev_ver);
  3979. return &state->frontend;
  3980. error:
  3981. kfree(state);
  3982. return NULL;
  3983. }
  3984. EXPORT_SYMBOL(stv090x_attach);
  3985. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3986. MODULE_AUTHOR("Manu Abraham");
  3987. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3988. MODULE_LICENSE("GPL");