qeth_core_main.c 129 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  247. static int qeth_issue_next_read(struct qeth_card *card)
  248. {
  249. int rc;
  250. struct qeth_cmd_buffer *iob;
  251. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  252. if (card->read.state != CH_STATE_UP)
  253. return -EIO;
  254. iob = qeth_get_buffer(&card->read);
  255. if (!iob) {
  256. dev_warn(&card->gdev->dev, "The qeth device driver "
  257. "failed to recover an error on the device\n");
  258. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  259. "available\n", dev_name(&card->gdev->dev));
  260. return -ENOMEM;
  261. }
  262. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  263. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  264. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  265. (addr_t) iob, 0, 0);
  266. if (rc) {
  267. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  268. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  269. atomic_set(&card->read.irq_pending, 0);
  270. qeth_schedule_recovery(card);
  271. wake_up(&card->wait_q);
  272. }
  273. return rc;
  274. }
  275. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  276. {
  277. struct qeth_reply *reply;
  278. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  279. if (reply) {
  280. atomic_set(&reply->refcnt, 1);
  281. atomic_set(&reply->received, 0);
  282. reply->card = card;
  283. };
  284. return reply;
  285. }
  286. static void qeth_get_reply(struct qeth_reply *reply)
  287. {
  288. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  289. atomic_inc(&reply->refcnt);
  290. }
  291. static void qeth_put_reply(struct qeth_reply *reply)
  292. {
  293. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  294. if (atomic_dec_and_test(&reply->refcnt))
  295. kfree(reply);
  296. }
  297. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  298. struct qeth_card *card)
  299. {
  300. char *ipa_name;
  301. int com = cmd->hdr.command;
  302. ipa_name = qeth_get_ipa_cmd_name(com);
  303. if (rc)
  304. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  305. ipa_name, com, QETH_CARD_IFNAME(card),
  306. rc, qeth_get_ipa_msg(rc));
  307. else
  308. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  309. ipa_name, com, QETH_CARD_IFNAME(card));
  310. }
  311. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  312. struct qeth_cmd_buffer *iob)
  313. {
  314. struct qeth_ipa_cmd *cmd = NULL;
  315. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  316. if (IS_IPA(iob->data)) {
  317. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  318. if (IS_IPA_REPLY(cmd)) {
  319. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  320. cmd->hdr.command != IPA_CMD_DELCCID &&
  321. cmd->hdr.command != IPA_CMD_MODCCID &&
  322. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  323. qeth_issue_ipa_msg(cmd,
  324. cmd->hdr.return_code, card);
  325. return cmd;
  326. } else {
  327. switch (cmd->hdr.command) {
  328. case IPA_CMD_STOPLAN:
  329. dev_warn(&card->gdev->dev,
  330. "The link for interface %s on CHPID"
  331. " 0x%X failed\n",
  332. QETH_CARD_IFNAME(card),
  333. card->info.chpid);
  334. card->lan_online = 0;
  335. if (card->dev && netif_carrier_ok(card->dev))
  336. netif_carrier_off(card->dev);
  337. return NULL;
  338. case IPA_CMD_STARTLAN:
  339. dev_info(&card->gdev->dev,
  340. "The link for %s on CHPID 0x%X has"
  341. " been restored\n",
  342. QETH_CARD_IFNAME(card),
  343. card->info.chpid);
  344. netif_carrier_on(card->dev);
  345. card->lan_online = 1;
  346. qeth_schedule_recovery(card);
  347. return NULL;
  348. case IPA_CMD_MODCCID:
  349. return cmd;
  350. case IPA_CMD_REGISTER_LOCAL_ADDR:
  351. QETH_DBF_TEXT(TRACE, 3, "irla");
  352. break;
  353. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  354. QETH_DBF_TEXT(TRACE, 3, "urla");
  355. break;
  356. default:
  357. QETH_DBF_MESSAGE(2, "Received data is IPA "
  358. "but not a reply!\n");
  359. break;
  360. }
  361. }
  362. }
  363. return cmd;
  364. }
  365. void qeth_clear_ipacmd_list(struct qeth_card *card)
  366. {
  367. struct qeth_reply *reply, *r;
  368. unsigned long flags;
  369. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  370. spin_lock_irqsave(&card->lock, flags);
  371. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  372. qeth_get_reply(reply);
  373. reply->rc = -EIO;
  374. atomic_inc(&reply->received);
  375. list_del_init(&reply->list);
  376. wake_up(&reply->wait_q);
  377. qeth_put_reply(reply);
  378. }
  379. spin_unlock_irqrestore(&card->lock, flags);
  380. }
  381. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  382. static int qeth_check_idx_response(unsigned char *buffer)
  383. {
  384. if (!buffer)
  385. return 0;
  386. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  387. if ((buffer[2] & 0xc0) == 0xc0) {
  388. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  389. "with cause code 0x%02x%s\n",
  390. buffer[4],
  391. ((buffer[4] == 0x22) ?
  392. " -- try another portname" : ""));
  393. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  394. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  395. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  396. return -EIO;
  397. }
  398. return 0;
  399. }
  400. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  401. __u32 len)
  402. {
  403. struct qeth_card *card;
  404. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  405. card = CARD_FROM_CDEV(channel->ccwdev);
  406. if (channel == &card->read)
  407. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  408. else
  409. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  410. channel->ccw.count = len;
  411. channel->ccw.cda = (__u32) __pa(iob);
  412. }
  413. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  414. {
  415. __u8 index;
  416. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  417. index = channel->io_buf_no;
  418. do {
  419. if (channel->iob[index].state == BUF_STATE_FREE) {
  420. channel->iob[index].state = BUF_STATE_LOCKED;
  421. channel->io_buf_no = (channel->io_buf_no + 1) %
  422. QETH_CMD_BUFFER_NO;
  423. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  424. return channel->iob + index;
  425. }
  426. index = (index + 1) % QETH_CMD_BUFFER_NO;
  427. } while (index != channel->io_buf_no);
  428. return NULL;
  429. }
  430. void qeth_release_buffer(struct qeth_channel *channel,
  431. struct qeth_cmd_buffer *iob)
  432. {
  433. unsigned long flags;
  434. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  435. spin_lock_irqsave(&channel->iob_lock, flags);
  436. memset(iob->data, 0, QETH_BUFSIZE);
  437. iob->state = BUF_STATE_FREE;
  438. iob->callback = qeth_send_control_data_cb;
  439. iob->rc = 0;
  440. spin_unlock_irqrestore(&channel->iob_lock, flags);
  441. }
  442. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  443. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. struct qeth_cmd_buffer *buffer = NULL;
  446. unsigned long flags;
  447. spin_lock_irqsave(&channel->iob_lock, flags);
  448. buffer = __qeth_get_buffer(channel);
  449. spin_unlock_irqrestore(&channel->iob_lock, flags);
  450. return buffer;
  451. }
  452. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  453. {
  454. struct qeth_cmd_buffer *buffer;
  455. wait_event(channel->wait_q,
  456. ((buffer = qeth_get_buffer(channel)) != NULL));
  457. return buffer;
  458. }
  459. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  460. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  461. {
  462. int cnt;
  463. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  464. qeth_release_buffer(channel, &channel->iob[cnt]);
  465. channel->buf_no = 0;
  466. channel->io_buf_no = 0;
  467. }
  468. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  469. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  470. struct qeth_cmd_buffer *iob)
  471. {
  472. struct qeth_card *card;
  473. struct qeth_reply *reply, *r;
  474. struct qeth_ipa_cmd *cmd;
  475. unsigned long flags;
  476. int keep_reply;
  477. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  478. card = CARD_FROM_CDEV(channel->ccwdev);
  479. if (qeth_check_idx_response(iob->data)) {
  480. qeth_clear_ipacmd_list(card);
  481. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  482. dev_err(&card->gdev->dev,
  483. "The qeth device is not configured "
  484. "for the OSI layer required by z/VM\n");
  485. else
  486. qeth_schedule_recovery(card);
  487. goto out;
  488. }
  489. cmd = qeth_check_ipa_data(card, iob);
  490. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  491. goto out;
  492. /*in case of OSN : check if cmd is set */
  493. if (card->info.type == QETH_CARD_TYPE_OSN &&
  494. cmd &&
  495. cmd->hdr.command != IPA_CMD_STARTLAN &&
  496. card->osn_info.assist_cb != NULL) {
  497. card->osn_info.assist_cb(card->dev, cmd);
  498. goto out;
  499. }
  500. spin_lock_irqsave(&card->lock, flags);
  501. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  502. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  503. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  504. qeth_get_reply(reply);
  505. list_del_init(&reply->list);
  506. spin_unlock_irqrestore(&card->lock, flags);
  507. keep_reply = 0;
  508. if (reply->callback != NULL) {
  509. if (cmd) {
  510. reply->offset = (__u16)((char *)cmd -
  511. (char *)iob->data);
  512. keep_reply = reply->callback(card,
  513. reply,
  514. (unsigned long)cmd);
  515. } else
  516. keep_reply = reply->callback(card,
  517. reply,
  518. (unsigned long)iob);
  519. }
  520. if (cmd)
  521. reply->rc = (u16) cmd->hdr.return_code;
  522. else if (iob->rc)
  523. reply->rc = iob->rc;
  524. if (keep_reply) {
  525. spin_lock_irqsave(&card->lock, flags);
  526. list_add_tail(&reply->list,
  527. &card->cmd_waiter_list);
  528. spin_unlock_irqrestore(&card->lock, flags);
  529. } else {
  530. atomic_inc(&reply->received);
  531. wake_up(&reply->wait_q);
  532. }
  533. qeth_put_reply(reply);
  534. goto out;
  535. }
  536. }
  537. spin_unlock_irqrestore(&card->lock, flags);
  538. out:
  539. memcpy(&card->seqno.pdu_hdr_ack,
  540. QETH_PDU_HEADER_SEQ_NO(iob->data),
  541. QETH_SEQ_NO_LENGTH);
  542. qeth_release_buffer(channel, iob);
  543. }
  544. static int qeth_setup_channel(struct qeth_channel *channel)
  545. {
  546. int cnt;
  547. QETH_DBF_TEXT(SETUP, 2, "setupch");
  548. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  549. channel->iob[cnt].data = (char *)
  550. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  551. if (channel->iob[cnt].data == NULL)
  552. break;
  553. channel->iob[cnt].state = BUF_STATE_FREE;
  554. channel->iob[cnt].channel = channel;
  555. channel->iob[cnt].callback = qeth_send_control_data_cb;
  556. channel->iob[cnt].rc = 0;
  557. }
  558. if (cnt < QETH_CMD_BUFFER_NO) {
  559. while (cnt-- > 0)
  560. kfree(channel->iob[cnt].data);
  561. return -ENOMEM;
  562. }
  563. channel->buf_no = 0;
  564. channel->io_buf_no = 0;
  565. atomic_set(&channel->irq_pending, 0);
  566. spin_lock_init(&channel->iob_lock);
  567. init_waitqueue_head(&channel->wait_q);
  568. return 0;
  569. }
  570. static int qeth_set_thread_start_bit(struct qeth_card *card,
  571. unsigned long thread)
  572. {
  573. unsigned long flags;
  574. spin_lock_irqsave(&card->thread_mask_lock, flags);
  575. if (!(card->thread_allowed_mask & thread) ||
  576. (card->thread_start_mask & thread)) {
  577. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  578. return -EPERM;
  579. }
  580. card->thread_start_mask |= thread;
  581. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  582. return 0;
  583. }
  584. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  585. {
  586. unsigned long flags;
  587. spin_lock_irqsave(&card->thread_mask_lock, flags);
  588. card->thread_start_mask &= ~thread;
  589. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  590. wake_up(&card->wait_q);
  591. }
  592. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  593. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  594. {
  595. unsigned long flags;
  596. spin_lock_irqsave(&card->thread_mask_lock, flags);
  597. card->thread_running_mask &= ~thread;
  598. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  599. wake_up(&card->wait_q);
  600. }
  601. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  602. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  603. {
  604. unsigned long flags;
  605. int rc = 0;
  606. spin_lock_irqsave(&card->thread_mask_lock, flags);
  607. if (card->thread_start_mask & thread) {
  608. if ((card->thread_allowed_mask & thread) &&
  609. !(card->thread_running_mask & thread)) {
  610. rc = 1;
  611. card->thread_start_mask &= ~thread;
  612. card->thread_running_mask |= thread;
  613. } else
  614. rc = -EPERM;
  615. }
  616. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  617. return rc;
  618. }
  619. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  620. {
  621. int rc = 0;
  622. wait_event(card->wait_q,
  623. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  624. return rc;
  625. }
  626. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  627. void qeth_schedule_recovery(struct qeth_card *card)
  628. {
  629. QETH_DBF_TEXT(TRACE, 2, "startrec");
  630. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  631. schedule_work(&card->kernel_thread_starter);
  632. }
  633. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  634. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  635. {
  636. int dstat, cstat;
  637. char *sense;
  638. sense = (char *) irb->ecw;
  639. cstat = irb->scsw.cmd.cstat;
  640. dstat = irb->scsw.cmd.dstat;
  641. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  642. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  643. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  644. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  645. dev_warn(&cdev->dev, "The qeth device driver "
  646. "failed to recover an error on the device\n");
  647. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  648. dev_name(&cdev->dev), dstat, cstat);
  649. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  650. 16, 1, irb, 64, 1);
  651. return 1;
  652. }
  653. if (dstat & DEV_STAT_UNIT_CHECK) {
  654. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  655. SENSE_RESETTING_EVENT_FLAG) {
  656. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  657. return 1;
  658. }
  659. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  660. SENSE_COMMAND_REJECT_FLAG) {
  661. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  662. return 1;
  663. }
  664. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  665. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  666. return 1;
  667. }
  668. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  669. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  670. return 0;
  671. }
  672. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  673. return 1;
  674. }
  675. return 0;
  676. }
  677. static long __qeth_check_irb_error(struct ccw_device *cdev,
  678. unsigned long intparm, struct irb *irb)
  679. {
  680. if (!IS_ERR(irb))
  681. return 0;
  682. switch (PTR_ERR(irb)) {
  683. case -EIO:
  684. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  685. dev_name(&cdev->dev));
  686. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  687. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  688. break;
  689. case -ETIMEDOUT:
  690. dev_warn(&cdev->dev, "A hardware operation timed out"
  691. " on the device\n");
  692. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  693. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  694. if (intparm == QETH_RCD_PARM) {
  695. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  696. if (card && (card->data.ccwdev == cdev)) {
  697. card->data.state = CH_STATE_DOWN;
  698. wake_up(&card->wait_q);
  699. }
  700. }
  701. break;
  702. default:
  703. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  704. dev_name(&cdev->dev), PTR_ERR(irb));
  705. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  706. QETH_DBF_TEXT(TRACE, 2, " rc???");
  707. }
  708. return PTR_ERR(irb);
  709. }
  710. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  711. struct irb *irb)
  712. {
  713. int rc;
  714. int cstat, dstat;
  715. struct qeth_cmd_buffer *buffer;
  716. struct qeth_channel *channel;
  717. struct qeth_card *card;
  718. struct qeth_cmd_buffer *iob;
  719. __u8 index;
  720. QETH_DBF_TEXT(TRACE, 5, "irq");
  721. if (__qeth_check_irb_error(cdev, intparm, irb))
  722. return;
  723. cstat = irb->scsw.cmd.cstat;
  724. dstat = irb->scsw.cmd.dstat;
  725. card = CARD_FROM_CDEV(cdev);
  726. if (!card)
  727. return;
  728. if (card->read.ccwdev == cdev) {
  729. channel = &card->read;
  730. QETH_DBF_TEXT(TRACE, 5, "read");
  731. } else if (card->write.ccwdev == cdev) {
  732. channel = &card->write;
  733. QETH_DBF_TEXT(TRACE, 5, "write");
  734. } else {
  735. channel = &card->data;
  736. QETH_DBF_TEXT(TRACE, 5, "data");
  737. }
  738. atomic_set(&channel->irq_pending, 0);
  739. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  740. channel->state = CH_STATE_STOPPED;
  741. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  742. channel->state = CH_STATE_HALTED;
  743. /*let's wake up immediately on data channel*/
  744. if ((channel == &card->data) && (intparm != 0) &&
  745. (intparm != QETH_RCD_PARM))
  746. goto out;
  747. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  748. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  749. /* we don't have to handle this further */
  750. intparm = 0;
  751. }
  752. if (intparm == QETH_HALT_CHANNEL_PARM) {
  753. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  754. /* we don't have to handle this further */
  755. intparm = 0;
  756. }
  757. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  758. (dstat & DEV_STAT_UNIT_CHECK) ||
  759. (cstat)) {
  760. if (irb->esw.esw0.erw.cons) {
  761. dev_warn(&channel->ccwdev->dev,
  762. "The qeth device driver failed to recover "
  763. "an error on the device\n");
  764. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  765. "0x%X dstat 0x%X\n",
  766. dev_name(&channel->ccwdev->dev), cstat, dstat);
  767. print_hex_dump(KERN_WARNING, "qeth: irb ",
  768. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  769. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  770. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  771. }
  772. if (intparm == QETH_RCD_PARM) {
  773. channel->state = CH_STATE_DOWN;
  774. goto out;
  775. }
  776. rc = qeth_get_problem(cdev, irb);
  777. if (rc) {
  778. qeth_clear_ipacmd_list(card);
  779. qeth_schedule_recovery(card);
  780. goto out;
  781. }
  782. }
  783. if (intparm == QETH_RCD_PARM) {
  784. channel->state = CH_STATE_RCD_DONE;
  785. goto out;
  786. }
  787. if (intparm) {
  788. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  789. buffer->state = BUF_STATE_PROCESSED;
  790. }
  791. if (channel == &card->data)
  792. return;
  793. if (channel == &card->read &&
  794. channel->state == CH_STATE_UP)
  795. qeth_issue_next_read(card);
  796. iob = channel->iob;
  797. index = channel->buf_no;
  798. while (iob[index].state == BUF_STATE_PROCESSED) {
  799. if (iob[index].callback != NULL)
  800. iob[index].callback(channel, iob + index);
  801. index = (index + 1) % QETH_CMD_BUFFER_NO;
  802. }
  803. channel->buf_no = index;
  804. out:
  805. wake_up(&card->wait_q);
  806. return;
  807. }
  808. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  809. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  810. {
  811. int i;
  812. struct sk_buff *skb;
  813. /* is PCI flag set on buffer? */
  814. if (buf->buffer->element[0].flags & 0x40)
  815. atomic_dec(&queue->set_pci_flags_count);
  816. if (!qeth_skip_skb) {
  817. skb = skb_dequeue(&buf->skb_list);
  818. while (skb) {
  819. atomic_dec(&skb->users);
  820. dev_kfree_skb_any(skb);
  821. skb = skb_dequeue(&buf->skb_list);
  822. }
  823. }
  824. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  825. if (buf->buffer->element[i].addr && buf->is_header[i])
  826. kmem_cache_free(qeth_core_header_cache,
  827. buf->buffer->element[i].addr);
  828. buf->is_header[i] = 0;
  829. buf->buffer->element[i].length = 0;
  830. buf->buffer->element[i].addr = NULL;
  831. buf->buffer->element[i].flags = 0;
  832. }
  833. buf->buffer->element[15].flags = 0;
  834. buf->next_element_to_fill = 0;
  835. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  836. }
  837. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  838. struct qeth_qdio_out_buffer *buf)
  839. {
  840. __qeth_clear_output_buffer(queue, buf, 0);
  841. }
  842. void qeth_clear_qdio_buffers(struct qeth_card *card)
  843. {
  844. int i, j;
  845. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  846. /* clear outbound buffers to free skbs */
  847. for (i = 0; i < card->qdio.no_out_queues; ++i)
  848. if (card->qdio.out_qs[i]) {
  849. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  850. qeth_clear_output_buffer(card->qdio.out_qs[i],
  851. &card->qdio.out_qs[i]->bufs[j]);
  852. }
  853. }
  854. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  855. static void qeth_free_buffer_pool(struct qeth_card *card)
  856. {
  857. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  858. int i = 0;
  859. QETH_DBF_TEXT(TRACE, 5, "freepool");
  860. list_for_each_entry_safe(pool_entry, tmp,
  861. &card->qdio.init_pool.entry_list, init_list){
  862. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  863. free_page((unsigned long)pool_entry->elements[i]);
  864. list_del(&pool_entry->init_list);
  865. kfree(pool_entry);
  866. }
  867. }
  868. static void qeth_free_qdio_buffers(struct qeth_card *card)
  869. {
  870. int i, j;
  871. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  872. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  873. QETH_QDIO_UNINITIALIZED)
  874. return;
  875. kfree(card->qdio.in_q);
  876. card->qdio.in_q = NULL;
  877. /* inbound buffer pool */
  878. qeth_free_buffer_pool(card);
  879. /* free outbound qdio_qs */
  880. if (card->qdio.out_qs) {
  881. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  882. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  883. qeth_clear_output_buffer(card->qdio.out_qs[i],
  884. &card->qdio.out_qs[i]->bufs[j]);
  885. kfree(card->qdio.out_qs[i]);
  886. }
  887. kfree(card->qdio.out_qs);
  888. card->qdio.out_qs = NULL;
  889. }
  890. }
  891. static void qeth_clean_channel(struct qeth_channel *channel)
  892. {
  893. int cnt;
  894. QETH_DBF_TEXT(SETUP, 2, "freech");
  895. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  896. kfree(channel->iob[cnt].data);
  897. }
  898. static int qeth_is_1920_device(struct qeth_card *card)
  899. {
  900. int single_queue = 0;
  901. struct ccw_device *ccwdev;
  902. struct channelPath_dsc {
  903. u8 flags;
  904. u8 lsn;
  905. u8 desc;
  906. u8 chpid;
  907. u8 swla;
  908. u8 zeroes;
  909. u8 chla;
  910. u8 chpp;
  911. } *chp_dsc;
  912. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  913. ccwdev = card->data.ccwdev;
  914. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  915. if (chp_dsc != NULL) {
  916. /* CHPP field bit 6 == 1 -> single queue */
  917. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  918. kfree(chp_dsc);
  919. }
  920. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  921. return single_queue;
  922. }
  923. static void qeth_init_qdio_info(struct qeth_card *card)
  924. {
  925. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  926. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  927. /* inbound */
  928. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  929. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  930. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  931. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  932. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  933. }
  934. static void qeth_set_intial_options(struct qeth_card *card)
  935. {
  936. card->options.route4.type = NO_ROUTER;
  937. card->options.route6.type = NO_ROUTER;
  938. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  939. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  940. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  941. card->options.fake_broadcast = 0;
  942. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  943. card->options.performance_stats = 0;
  944. card->options.rx_sg_cb = QETH_RX_SG_CB;
  945. card->options.isolation = ISOLATION_MODE_NONE;
  946. }
  947. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  948. {
  949. unsigned long flags;
  950. int rc = 0;
  951. spin_lock_irqsave(&card->thread_mask_lock, flags);
  952. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  953. (u8) card->thread_start_mask,
  954. (u8) card->thread_allowed_mask,
  955. (u8) card->thread_running_mask);
  956. rc = (card->thread_start_mask & thread);
  957. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  958. return rc;
  959. }
  960. static void qeth_start_kernel_thread(struct work_struct *work)
  961. {
  962. struct qeth_card *card = container_of(work, struct qeth_card,
  963. kernel_thread_starter);
  964. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  965. if (card->read.state != CH_STATE_UP &&
  966. card->write.state != CH_STATE_UP)
  967. return;
  968. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  969. kthread_run(card->discipline.recover, (void *) card,
  970. "qeth_recover");
  971. }
  972. static int qeth_setup_card(struct qeth_card *card)
  973. {
  974. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  975. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  976. card->read.state = CH_STATE_DOWN;
  977. card->write.state = CH_STATE_DOWN;
  978. card->data.state = CH_STATE_DOWN;
  979. card->state = CARD_STATE_DOWN;
  980. card->lan_online = 0;
  981. card->use_hard_stop = 0;
  982. card->dev = NULL;
  983. spin_lock_init(&card->vlanlock);
  984. spin_lock_init(&card->mclock);
  985. card->vlangrp = NULL;
  986. spin_lock_init(&card->lock);
  987. spin_lock_init(&card->ip_lock);
  988. spin_lock_init(&card->thread_mask_lock);
  989. card->thread_start_mask = 0;
  990. card->thread_allowed_mask = 0;
  991. card->thread_running_mask = 0;
  992. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  993. INIT_LIST_HEAD(&card->ip_list);
  994. INIT_LIST_HEAD(card->ip_tbd_list);
  995. INIT_LIST_HEAD(&card->cmd_waiter_list);
  996. init_waitqueue_head(&card->wait_q);
  997. /* intial options */
  998. qeth_set_intial_options(card);
  999. /* IP address takeover */
  1000. INIT_LIST_HEAD(&card->ipato.entries);
  1001. card->ipato.enabled = 0;
  1002. card->ipato.invert4 = 0;
  1003. card->ipato.invert6 = 0;
  1004. /* init QDIO stuff */
  1005. qeth_init_qdio_info(card);
  1006. return 0;
  1007. }
  1008. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1009. {
  1010. struct qeth_card *card = container_of(slr, struct qeth_card,
  1011. qeth_service_level);
  1012. if (card->info.mcl_level[0])
  1013. seq_printf(m, "qeth: %s firmware level %s\n",
  1014. CARD_BUS_ID(card), card->info.mcl_level);
  1015. }
  1016. static struct qeth_card *qeth_alloc_card(void)
  1017. {
  1018. struct qeth_card *card;
  1019. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1020. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1021. if (!card)
  1022. goto out;
  1023. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1024. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1025. if (!card->ip_tbd_list) {
  1026. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1027. goto out_card;
  1028. }
  1029. if (qeth_setup_channel(&card->read))
  1030. goto out_ip;
  1031. if (qeth_setup_channel(&card->write))
  1032. goto out_channel;
  1033. card->options.layer2 = -1;
  1034. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1035. register_service_level(&card->qeth_service_level);
  1036. return card;
  1037. out_channel:
  1038. qeth_clean_channel(&card->read);
  1039. out_ip:
  1040. kfree(card->ip_tbd_list);
  1041. out_card:
  1042. kfree(card);
  1043. out:
  1044. return NULL;
  1045. }
  1046. static int qeth_determine_card_type(struct qeth_card *card)
  1047. {
  1048. int i = 0;
  1049. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1050. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1051. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1052. while (known_devices[i][4]) {
  1053. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1054. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1055. card->info.type = known_devices[i][4];
  1056. card->qdio.no_out_queues = known_devices[i][8];
  1057. card->info.is_multicast_different = known_devices[i][9];
  1058. if (qeth_is_1920_device(card)) {
  1059. dev_info(&card->gdev->dev,
  1060. "Priority Queueing not supported\n");
  1061. card->qdio.no_out_queues = 1;
  1062. card->qdio.default_out_queue = 0;
  1063. }
  1064. return 0;
  1065. }
  1066. i++;
  1067. }
  1068. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1069. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1070. "unknown type\n");
  1071. return -ENOENT;
  1072. }
  1073. static int qeth_clear_channel(struct qeth_channel *channel)
  1074. {
  1075. unsigned long flags;
  1076. struct qeth_card *card;
  1077. int rc;
  1078. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1079. card = CARD_FROM_CDEV(channel->ccwdev);
  1080. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1081. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1082. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1083. if (rc)
  1084. return rc;
  1085. rc = wait_event_interruptible_timeout(card->wait_q,
  1086. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1087. if (rc == -ERESTARTSYS)
  1088. return rc;
  1089. if (channel->state != CH_STATE_STOPPED)
  1090. return -ETIME;
  1091. channel->state = CH_STATE_DOWN;
  1092. return 0;
  1093. }
  1094. static int qeth_halt_channel(struct qeth_channel *channel)
  1095. {
  1096. unsigned long flags;
  1097. struct qeth_card *card;
  1098. int rc;
  1099. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1100. card = CARD_FROM_CDEV(channel->ccwdev);
  1101. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1102. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1103. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1104. if (rc)
  1105. return rc;
  1106. rc = wait_event_interruptible_timeout(card->wait_q,
  1107. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1108. if (rc == -ERESTARTSYS)
  1109. return rc;
  1110. if (channel->state != CH_STATE_HALTED)
  1111. return -ETIME;
  1112. return 0;
  1113. }
  1114. static int qeth_halt_channels(struct qeth_card *card)
  1115. {
  1116. int rc1 = 0, rc2 = 0, rc3 = 0;
  1117. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1118. rc1 = qeth_halt_channel(&card->read);
  1119. rc2 = qeth_halt_channel(&card->write);
  1120. rc3 = qeth_halt_channel(&card->data);
  1121. if (rc1)
  1122. return rc1;
  1123. if (rc2)
  1124. return rc2;
  1125. return rc3;
  1126. }
  1127. static int qeth_clear_channels(struct qeth_card *card)
  1128. {
  1129. int rc1 = 0, rc2 = 0, rc3 = 0;
  1130. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1131. rc1 = qeth_clear_channel(&card->read);
  1132. rc2 = qeth_clear_channel(&card->write);
  1133. rc3 = qeth_clear_channel(&card->data);
  1134. if (rc1)
  1135. return rc1;
  1136. if (rc2)
  1137. return rc2;
  1138. return rc3;
  1139. }
  1140. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1141. {
  1142. int rc = 0;
  1143. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1144. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1145. if (halt)
  1146. rc = qeth_halt_channels(card);
  1147. if (rc)
  1148. return rc;
  1149. return qeth_clear_channels(card);
  1150. }
  1151. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1152. {
  1153. int rc = 0;
  1154. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1155. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1156. QETH_QDIO_CLEANING)) {
  1157. case QETH_QDIO_ESTABLISHED:
  1158. if (card->info.type == QETH_CARD_TYPE_IQD)
  1159. rc = qdio_cleanup(CARD_DDEV(card),
  1160. QDIO_FLAG_CLEANUP_USING_HALT);
  1161. else
  1162. rc = qdio_cleanup(CARD_DDEV(card),
  1163. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1164. if (rc)
  1165. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1166. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1167. break;
  1168. case QETH_QDIO_CLEANING:
  1169. return rc;
  1170. default:
  1171. break;
  1172. }
  1173. rc = qeth_clear_halt_card(card, use_halt);
  1174. if (rc)
  1175. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1176. card->state = CARD_STATE_DOWN;
  1177. return rc;
  1178. }
  1179. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1180. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1181. int *length)
  1182. {
  1183. struct ciw *ciw;
  1184. char *rcd_buf;
  1185. int ret;
  1186. struct qeth_channel *channel = &card->data;
  1187. unsigned long flags;
  1188. /*
  1189. * scan for RCD command in extended SenseID data
  1190. */
  1191. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1192. if (!ciw || ciw->cmd == 0)
  1193. return -EOPNOTSUPP;
  1194. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1195. if (!rcd_buf)
  1196. return -ENOMEM;
  1197. channel->ccw.cmd_code = ciw->cmd;
  1198. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1199. channel->ccw.count = ciw->count;
  1200. channel->ccw.flags = CCW_FLAG_SLI;
  1201. channel->state = CH_STATE_RCD;
  1202. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1203. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1204. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1205. QETH_RCD_TIMEOUT);
  1206. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1207. if (!ret)
  1208. wait_event(card->wait_q,
  1209. (channel->state == CH_STATE_RCD_DONE ||
  1210. channel->state == CH_STATE_DOWN));
  1211. if (channel->state == CH_STATE_DOWN)
  1212. ret = -EIO;
  1213. else
  1214. channel->state = CH_STATE_DOWN;
  1215. if (ret) {
  1216. kfree(rcd_buf);
  1217. *buffer = NULL;
  1218. *length = 0;
  1219. } else {
  1220. *length = ciw->count;
  1221. *buffer = rcd_buf;
  1222. }
  1223. return ret;
  1224. }
  1225. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1226. {
  1227. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1228. card->info.chpid = prcd[30];
  1229. card->info.unit_addr2 = prcd[31];
  1230. card->info.cula = prcd[63];
  1231. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1232. (prcd[0x11] == _ascebc['M']));
  1233. }
  1234. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1235. {
  1236. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1237. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1238. card->info.blkt.time_total = 250;
  1239. card->info.blkt.inter_packet = 5;
  1240. card->info.blkt.inter_packet_jumbo = 15;
  1241. } else {
  1242. card->info.blkt.time_total = 0;
  1243. card->info.blkt.inter_packet = 0;
  1244. card->info.blkt.inter_packet_jumbo = 0;
  1245. }
  1246. }
  1247. static void qeth_init_tokens(struct qeth_card *card)
  1248. {
  1249. card->token.issuer_rm_w = 0x00010103UL;
  1250. card->token.cm_filter_w = 0x00010108UL;
  1251. card->token.cm_connection_w = 0x0001010aUL;
  1252. card->token.ulp_filter_w = 0x0001010bUL;
  1253. card->token.ulp_connection_w = 0x0001010dUL;
  1254. }
  1255. static void qeth_init_func_level(struct qeth_card *card)
  1256. {
  1257. if (card->ipato.enabled) {
  1258. if (card->info.type == QETH_CARD_TYPE_IQD)
  1259. card->info.func_level =
  1260. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1261. else
  1262. card->info.func_level =
  1263. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1264. } else {
  1265. if (card->info.type == QETH_CARD_TYPE_IQD)
  1266. /*FIXME:why do we have same values for dis and ena for
  1267. osae??? */
  1268. card->info.func_level =
  1269. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1270. else
  1271. card->info.func_level =
  1272. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1273. }
  1274. }
  1275. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1276. void (*idx_reply_cb)(struct qeth_channel *,
  1277. struct qeth_cmd_buffer *))
  1278. {
  1279. struct qeth_cmd_buffer *iob;
  1280. unsigned long flags;
  1281. int rc;
  1282. struct qeth_card *card;
  1283. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1284. card = CARD_FROM_CDEV(channel->ccwdev);
  1285. iob = qeth_get_buffer(channel);
  1286. iob->callback = idx_reply_cb;
  1287. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1288. channel->ccw.count = QETH_BUFSIZE;
  1289. channel->ccw.cda = (__u32) __pa(iob->data);
  1290. wait_event(card->wait_q,
  1291. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1292. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1293. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1294. rc = ccw_device_start(channel->ccwdev,
  1295. &channel->ccw, (addr_t) iob, 0, 0);
  1296. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1297. if (rc) {
  1298. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1299. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1300. atomic_set(&channel->irq_pending, 0);
  1301. wake_up(&card->wait_q);
  1302. return rc;
  1303. }
  1304. rc = wait_event_interruptible_timeout(card->wait_q,
  1305. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1306. if (rc == -ERESTARTSYS)
  1307. return rc;
  1308. if (channel->state != CH_STATE_UP) {
  1309. rc = -ETIME;
  1310. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1311. qeth_clear_cmd_buffers(channel);
  1312. } else
  1313. rc = 0;
  1314. return rc;
  1315. }
  1316. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1317. void (*idx_reply_cb)(struct qeth_channel *,
  1318. struct qeth_cmd_buffer *))
  1319. {
  1320. struct qeth_card *card;
  1321. struct qeth_cmd_buffer *iob;
  1322. unsigned long flags;
  1323. __u16 temp;
  1324. __u8 tmp;
  1325. int rc;
  1326. struct ccw_dev_id temp_devid;
  1327. card = CARD_FROM_CDEV(channel->ccwdev);
  1328. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1329. iob = qeth_get_buffer(channel);
  1330. iob->callback = idx_reply_cb;
  1331. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1332. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1333. channel->ccw.cda = (__u32) __pa(iob->data);
  1334. if (channel == &card->write) {
  1335. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1336. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1337. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1338. card->seqno.trans_hdr++;
  1339. } else {
  1340. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1341. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1342. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1343. }
  1344. tmp = ((__u8)card->info.portno) | 0x80;
  1345. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1346. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1347. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1348. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1349. &card->info.func_level, sizeof(__u16));
  1350. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1351. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1352. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1353. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1354. wait_event(card->wait_q,
  1355. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1356. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1357. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1358. rc = ccw_device_start(channel->ccwdev,
  1359. &channel->ccw, (addr_t) iob, 0, 0);
  1360. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1361. if (rc) {
  1362. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1363. rc);
  1364. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1365. atomic_set(&channel->irq_pending, 0);
  1366. wake_up(&card->wait_q);
  1367. return rc;
  1368. }
  1369. rc = wait_event_interruptible_timeout(card->wait_q,
  1370. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1371. if (rc == -ERESTARTSYS)
  1372. return rc;
  1373. if (channel->state != CH_STATE_ACTIVATING) {
  1374. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1375. " failed to recover an error on the device\n");
  1376. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1377. dev_name(&channel->ccwdev->dev));
  1378. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1379. qeth_clear_cmd_buffers(channel);
  1380. return -ETIME;
  1381. }
  1382. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1383. }
  1384. static int qeth_peer_func_level(int level)
  1385. {
  1386. if ((level & 0xff) == 8)
  1387. return (level & 0xff) + 0x400;
  1388. if (((level >> 8) & 3) == 1)
  1389. return (level & 0xff) + 0x200;
  1390. return level;
  1391. }
  1392. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1393. struct qeth_cmd_buffer *iob)
  1394. {
  1395. struct qeth_card *card;
  1396. __u16 temp;
  1397. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1398. if (channel->state == CH_STATE_DOWN) {
  1399. channel->state = CH_STATE_ACTIVATING;
  1400. goto out;
  1401. }
  1402. card = CARD_FROM_CDEV(channel->ccwdev);
  1403. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1404. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1405. dev_err(&card->write.ccwdev->dev,
  1406. "The adapter is used exclusively by another "
  1407. "host\n");
  1408. else
  1409. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1410. " negative reply\n",
  1411. dev_name(&card->write.ccwdev->dev));
  1412. goto out;
  1413. }
  1414. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1415. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1416. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1417. "function level mismatch (sent: 0x%x, received: "
  1418. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1419. card->info.func_level, temp);
  1420. goto out;
  1421. }
  1422. channel->state = CH_STATE_UP;
  1423. out:
  1424. qeth_release_buffer(channel, iob);
  1425. }
  1426. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1427. struct qeth_cmd_buffer *iob)
  1428. {
  1429. struct qeth_card *card;
  1430. __u16 temp;
  1431. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1432. if (channel->state == CH_STATE_DOWN) {
  1433. channel->state = CH_STATE_ACTIVATING;
  1434. goto out;
  1435. }
  1436. card = CARD_FROM_CDEV(channel->ccwdev);
  1437. if (qeth_check_idx_response(iob->data))
  1438. goto out;
  1439. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1440. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1441. dev_err(&card->write.ccwdev->dev,
  1442. "The adapter is used exclusively by another "
  1443. "host\n");
  1444. else
  1445. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1446. " negative reply\n",
  1447. dev_name(&card->read.ccwdev->dev));
  1448. goto out;
  1449. }
  1450. /**
  1451. * temporary fix for microcode bug
  1452. * to revert it,replace OR by AND
  1453. */
  1454. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1455. (card->info.type == QETH_CARD_TYPE_OSAE))
  1456. card->info.portname_required = 1;
  1457. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1458. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1459. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1460. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1461. dev_name(&card->read.ccwdev->dev),
  1462. card->info.func_level, temp);
  1463. goto out;
  1464. }
  1465. memcpy(&card->token.issuer_rm_r,
  1466. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1467. QETH_MPC_TOKEN_LENGTH);
  1468. memcpy(&card->info.mcl_level[0],
  1469. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1470. channel->state = CH_STATE_UP;
  1471. out:
  1472. qeth_release_buffer(channel, iob);
  1473. }
  1474. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1475. struct qeth_cmd_buffer *iob)
  1476. {
  1477. qeth_setup_ccw(&card->write, iob->data, len);
  1478. iob->callback = qeth_release_buffer;
  1479. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1480. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1481. card->seqno.trans_hdr++;
  1482. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1483. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1484. card->seqno.pdu_hdr++;
  1485. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1486. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1487. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1488. }
  1489. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1490. int qeth_send_control_data(struct qeth_card *card, int len,
  1491. struct qeth_cmd_buffer *iob,
  1492. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1493. unsigned long),
  1494. void *reply_param)
  1495. {
  1496. int rc;
  1497. unsigned long flags;
  1498. struct qeth_reply *reply = NULL;
  1499. unsigned long timeout, event_timeout;
  1500. struct qeth_ipa_cmd *cmd;
  1501. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1502. reply = qeth_alloc_reply(card);
  1503. if (!reply) {
  1504. return -ENOMEM;
  1505. }
  1506. reply->callback = reply_cb;
  1507. reply->param = reply_param;
  1508. if (card->state == CARD_STATE_DOWN)
  1509. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1510. else
  1511. reply->seqno = card->seqno.ipa++;
  1512. init_waitqueue_head(&reply->wait_q);
  1513. spin_lock_irqsave(&card->lock, flags);
  1514. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1515. spin_unlock_irqrestore(&card->lock, flags);
  1516. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1517. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1518. qeth_prepare_control_data(card, len, iob);
  1519. if (IS_IPA(iob->data))
  1520. event_timeout = QETH_IPA_TIMEOUT;
  1521. else
  1522. event_timeout = QETH_TIMEOUT;
  1523. timeout = jiffies + event_timeout;
  1524. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1525. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1526. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1527. (addr_t) iob, 0, 0);
  1528. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1529. if (rc) {
  1530. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1531. "ccw_device_start rc = %i\n",
  1532. dev_name(&card->write.ccwdev->dev), rc);
  1533. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1534. spin_lock_irqsave(&card->lock, flags);
  1535. list_del_init(&reply->list);
  1536. qeth_put_reply(reply);
  1537. spin_unlock_irqrestore(&card->lock, flags);
  1538. qeth_release_buffer(iob->channel, iob);
  1539. atomic_set(&card->write.irq_pending, 0);
  1540. wake_up(&card->wait_q);
  1541. return rc;
  1542. }
  1543. /* we have only one long running ipassist, since we can ensure
  1544. process context of this command we can sleep */
  1545. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1546. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1547. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1548. if (!wait_event_timeout(reply->wait_q,
  1549. atomic_read(&reply->received), event_timeout))
  1550. goto time_err;
  1551. } else {
  1552. while (!atomic_read(&reply->received)) {
  1553. if (time_after(jiffies, timeout))
  1554. goto time_err;
  1555. cpu_relax();
  1556. };
  1557. }
  1558. rc = reply->rc;
  1559. qeth_put_reply(reply);
  1560. return rc;
  1561. time_err:
  1562. spin_lock_irqsave(&reply->card->lock, flags);
  1563. list_del_init(&reply->list);
  1564. spin_unlock_irqrestore(&reply->card->lock, flags);
  1565. reply->rc = -ETIME;
  1566. atomic_inc(&reply->received);
  1567. wake_up(&reply->wait_q);
  1568. rc = reply->rc;
  1569. qeth_put_reply(reply);
  1570. return rc;
  1571. }
  1572. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1573. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1574. unsigned long data)
  1575. {
  1576. struct qeth_cmd_buffer *iob;
  1577. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1578. iob = (struct qeth_cmd_buffer *) data;
  1579. memcpy(&card->token.cm_filter_r,
  1580. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1581. QETH_MPC_TOKEN_LENGTH);
  1582. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1583. return 0;
  1584. }
  1585. static int qeth_cm_enable(struct qeth_card *card)
  1586. {
  1587. int rc;
  1588. struct qeth_cmd_buffer *iob;
  1589. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1590. iob = qeth_wait_for_buffer(&card->write);
  1591. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1592. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1593. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1594. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1595. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1596. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1597. qeth_cm_enable_cb, NULL);
  1598. return rc;
  1599. }
  1600. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1601. unsigned long data)
  1602. {
  1603. struct qeth_cmd_buffer *iob;
  1604. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1605. iob = (struct qeth_cmd_buffer *) data;
  1606. memcpy(&card->token.cm_connection_r,
  1607. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1608. QETH_MPC_TOKEN_LENGTH);
  1609. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1610. return 0;
  1611. }
  1612. static int qeth_cm_setup(struct qeth_card *card)
  1613. {
  1614. int rc;
  1615. struct qeth_cmd_buffer *iob;
  1616. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1617. iob = qeth_wait_for_buffer(&card->write);
  1618. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1619. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1620. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1621. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1622. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1623. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1624. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1625. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1626. qeth_cm_setup_cb, NULL);
  1627. return rc;
  1628. }
  1629. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1630. {
  1631. switch (card->info.type) {
  1632. case QETH_CARD_TYPE_UNKNOWN:
  1633. return 1500;
  1634. case QETH_CARD_TYPE_IQD:
  1635. return card->info.max_mtu;
  1636. case QETH_CARD_TYPE_OSAE:
  1637. switch (card->info.link_type) {
  1638. case QETH_LINK_TYPE_HSTR:
  1639. case QETH_LINK_TYPE_LANE_TR:
  1640. return 2000;
  1641. default:
  1642. return 1492;
  1643. }
  1644. default:
  1645. return 1500;
  1646. }
  1647. }
  1648. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1649. {
  1650. switch (cardtype) {
  1651. case QETH_CARD_TYPE_UNKNOWN:
  1652. case QETH_CARD_TYPE_OSAE:
  1653. case QETH_CARD_TYPE_OSN:
  1654. return 61440;
  1655. case QETH_CARD_TYPE_IQD:
  1656. return 57344;
  1657. default:
  1658. return 1500;
  1659. }
  1660. }
  1661. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1662. {
  1663. switch (cardtype) {
  1664. case QETH_CARD_TYPE_IQD:
  1665. return 1;
  1666. default:
  1667. return 0;
  1668. }
  1669. }
  1670. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1671. {
  1672. switch (framesize) {
  1673. case 0x4000:
  1674. return 8192;
  1675. case 0x6000:
  1676. return 16384;
  1677. case 0xa000:
  1678. return 32768;
  1679. case 0xffff:
  1680. return 57344;
  1681. default:
  1682. return 0;
  1683. }
  1684. }
  1685. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1686. {
  1687. switch (card->info.type) {
  1688. case QETH_CARD_TYPE_OSAE:
  1689. return ((mtu >= 576) && (mtu <= 61440));
  1690. case QETH_CARD_TYPE_IQD:
  1691. return ((mtu >= 576) &&
  1692. (mtu <= card->info.max_mtu + 4096 - 32));
  1693. case QETH_CARD_TYPE_OSN:
  1694. case QETH_CARD_TYPE_UNKNOWN:
  1695. default:
  1696. return 1;
  1697. }
  1698. }
  1699. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1700. unsigned long data)
  1701. {
  1702. __u16 mtu, framesize;
  1703. __u16 len;
  1704. __u8 link_type;
  1705. struct qeth_cmd_buffer *iob;
  1706. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1707. iob = (struct qeth_cmd_buffer *) data;
  1708. memcpy(&card->token.ulp_filter_r,
  1709. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1710. QETH_MPC_TOKEN_LENGTH);
  1711. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1712. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1713. mtu = qeth_get_mtu_outof_framesize(framesize);
  1714. if (!mtu) {
  1715. iob->rc = -EINVAL;
  1716. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1717. return 0;
  1718. }
  1719. card->info.max_mtu = mtu;
  1720. card->info.initial_mtu = mtu;
  1721. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1722. } else {
  1723. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1724. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1725. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1726. }
  1727. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1728. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1729. memcpy(&link_type,
  1730. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1731. card->info.link_type = link_type;
  1732. } else
  1733. card->info.link_type = 0;
  1734. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1735. return 0;
  1736. }
  1737. static int qeth_ulp_enable(struct qeth_card *card)
  1738. {
  1739. int rc;
  1740. char prot_type;
  1741. struct qeth_cmd_buffer *iob;
  1742. /*FIXME: trace view callbacks*/
  1743. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1744. iob = qeth_wait_for_buffer(&card->write);
  1745. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1746. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1747. (__u8) card->info.portno;
  1748. if (card->options.layer2)
  1749. if (card->info.type == QETH_CARD_TYPE_OSN)
  1750. prot_type = QETH_PROT_OSN2;
  1751. else
  1752. prot_type = QETH_PROT_LAYER2;
  1753. else
  1754. prot_type = QETH_PROT_TCPIP;
  1755. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1756. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1757. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1758. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1759. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1760. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1761. card->info.portname, 9);
  1762. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1763. qeth_ulp_enable_cb, NULL);
  1764. return rc;
  1765. }
  1766. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1767. unsigned long data)
  1768. {
  1769. struct qeth_cmd_buffer *iob;
  1770. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1771. iob = (struct qeth_cmd_buffer *) data;
  1772. memcpy(&card->token.ulp_connection_r,
  1773. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1774. QETH_MPC_TOKEN_LENGTH);
  1775. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1776. return 0;
  1777. }
  1778. static int qeth_ulp_setup(struct qeth_card *card)
  1779. {
  1780. int rc;
  1781. __u16 temp;
  1782. struct qeth_cmd_buffer *iob;
  1783. struct ccw_dev_id dev_id;
  1784. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1785. iob = qeth_wait_for_buffer(&card->write);
  1786. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1787. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1788. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1789. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1790. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1791. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1792. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1793. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1794. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1795. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1796. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1797. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1798. qeth_ulp_setup_cb, NULL);
  1799. return rc;
  1800. }
  1801. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1802. {
  1803. int i, j;
  1804. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1805. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1806. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1807. return 0;
  1808. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1809. GFP_KERNEL);
  1810. if (!card->qdio.in_q)
  1811. goto out_nomem;
  1812. QETH_DBF_TEXT(SETUP, 2, "inq");
  1813. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1814. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1815. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1816. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1817. card->qdio.in_q->bufs[i].buffer =
  1818. &card->qdio.in_q->qdio_bufs[i];
  1819. /* inbound buffer pool */
  1820. if (qeth_alloc_buffer_pool(card))
  1821. goto out_freeinq;
  1822. /* outbound */
  1823. card->qdio.out_qs =
  1824. kmalloc(card->qdio.no_out_queues *
  1825. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1826. if (!card->qdio.out_qs)
  1827. goto out_freepool;
  1828. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1829. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1830. GFP_KERNEL);
  1831. if (!card->qdio.out_qs[i])
  1832. goto out_freeoutq;
  1833. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1834. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1835. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1836. card->qdio.out_qs[i]->queue_no = i;
  1837. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1838. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1839. card->qdio.out_qs[i]->bufs[j].buffer =
  1840. &card->qdio.out_qs[i]->qdio_bufs[j];
  1841. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1842. skb_list);
  1843. lockdep_set_class(
  1844. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1845. &qdio_out_skb_queue_key);
  1846. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1847. }
  1848. }
  1849. return 0;
  1850. out_freeoutq:
  1851. while (i > 0)
  1852. kfree(card->qdio.out_qs[--i]);
  1853. kfree(card->qdio.out_qs);
  1854. card->qdio.out_qs = NULL;
  1855. out_freepool:
  1856. qeth_free_buffer_pool(card);
  1857. out_freeinq:
  1858. kfree(card->qdio.in_q);
  1859. card->qdio.in_q = NULL;
  1860. out_nomem:
  1861. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1862. return -ENOMEM;
  1863. }
  1864. static void qeth_create_qib_param_field(struct qeth_card *card,
  1865. char *param_field)
  1866. {
  1867. param_field[0] = _ascebc['P'];
  1868. param_field[1] = _ascebc['C'];
  1869. param_field[2] = _ascebc['I'];
  1870. param_field[3] = _ascebc['T'];
  1871. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1872. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1873. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1874. }
  1875. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1876. char *param_field)
  1877. {
  1878. param_field[16] = _ascebc['B'];
  1879. param_field[17] = _ascebc['L'];
  1880. param_field[18] = _ascebc['K'];
  1881. param_field[19] = _ascebc['T'];
  1882. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1883. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1884. *((unsigned int *) (&param_field[28])) =
  1885. card->info.blkt.inter_packet_jumbo;
  1886. }
  1887. static int qeth_qdio_activate(struct qeth_card *card)
  1888. {
  1889. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1890. return qdio_activate(CARD_DDEV(card));
  1891. }
  1892. static int qeth_dm_act(struct qeth_card *card)
  1893. {
  1894. int rc;
  1895. struct qeth_cmd_buffer *iob;
  1896. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1897. iob = qeth_wait_for_buffer(&card->write);
  1898. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1899. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1900. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1901. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1902. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1903. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1904. return rc;
  1905. }
  1906. static int qeth_mpc_initialize(struct qeth_card *card)
  1907. {
  1908. int rc;
  1909. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1910. rc = qeth_issue_next_read(card);
  1911. if (rc) {
  1912. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1913. return rc;
  1914. }
  1915. rc = qeth_cm_enable(card);
  1916. if (rc) {
  1917. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1918. goto out_qdio;
  1919. }
  1920. rc = qeth_cm_setup(card);
  1921. if (rc) {
  1922. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1923. goto out_qdio;
  1924. }
  1925. rc = qeth_ulp_enable(card);
  1926. if (rc) {
  1927. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1928. goto out_qdio;
  1929. }
  1930. rc = qeth_ulp_setup(card);
  1931. if (rc) {
  1932. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1933. goto out_qdio;
  1934. }
  1935. rc = qeth_alloc_qdio_buffers(card);
  1936. if (rc) {
  1937. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1938. goto out_qdio;
  1939. }
  1940. rc = qeth_qdio_establish(card);
  1941. if (rc) {
  1942. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1943. qeth_free_qdio_buffers(card);
  1944. goto out_qdio;
  1945. }
  1946. rc = qeth_qdio_activate(card);
  1947. if (rc) {
  1948. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1949. goto out_qdio;
  1950. }
  1951. rc = qeth_dm_act(card);
  1952. if (rc) {
  1953. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1954. goto out_qdio;
  1955. }
  1956. return 0;
  1957. out_qdio:
  1958. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1959. return rc;
  1960. }
  1961. static void qeth_print_status_with_portname(struct qeth_card *card)
  1962. {
  1963. char dbf_text[15];
  1964. int i;
  1965. sprintf(dbf_text, "%s", card->info.portname + 1);
  1966. for (i = 0; i < 8; i++)
  1967. dbf_text[i] =
  1968. (char) _ebcasc[(__u8) dbf_text[i]];
  1969. dbf_text[8] = 0;
  1970. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1971. "with link type %s (portname: %s)\n",
  1972. qeth_get_cardname(card),
  1973. (card->info.mcl_level[0]) ? " (level: " : "",
  1974. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1975. (card->info.mcl_level[0]) ? ")" : "",
  1976. qeth_get_cardname_short(card),
  1977. dbf_text);
  1978. }
  1979. static void qeth_print_status_no_portname(struct qeth_card *card)
  1980. {
  1981. if (card->info.portname[0])
  1982. dev_info(&card->gdev->dev, "Device is a%s "
  1983. "card%s%s%s\nwith link type %s "
  1984. "(no portname needed by interface).\n",
  1985. qeth_get_cardname(card),
  1986. (card->info.mcl_level[0]) ? " (level: " : "",
  1987. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1988. (card->info.mcl_level[0]) ? ")" : "",
  1989. qeth_get_cardname_short(card));
  1990. else
  1991. dev_info(&card->gdev->dev, "Device is a%s "
  1992. "card%s%s%s\nwith link type %s.\n",
  1993. qeth_get_cardname(card),
  1994. (card->info.mcl_level[0]) ? " (level: " : "",
  1995. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1996. (card->info.mcl_level[0]) ? ")" : "",
  1997. qeth_get_cardname_short(card));
  1998. }
  1999. void qeth_print_status_message(struct qeth_card *card)
  2000. {
  2001. switch (card->info.type) {
  2002. case QETH_CARD_TYPE_OSAE:
  2003. /* VM will use a non-zero first character
  2004. * to indicate a HiperSockets like reporting
  2005. * of the level OSA sets the first character to zero
  2006. * */
  2007. if (!card->info.mcl_level[0]) {
  2008. sprintf(card->info.mcl_level, "%02x%02x",
  2009. card->info.mcl_level[2],
  2010. card->info.mcl_level[3]);
  2011. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2012. break;
  2013. }
  2014. /* fallthrough */
  2015. case QETH_CARD_TYPE_IQD:
  2016. if ((card->info.guestlan) ||
  2017. (card->info.mcl_level[0] & 0x80)) {
  2018. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2019. card->info.mcl_level[0]];
  2020. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2021. card->info.mcl_level[1]];
  2022. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2023. card->info.mcl_level[2]];
  2024. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2025. card->info.mcl_level[3]];
  2026. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2027. }
  2028. break;
  2029. default:
  2030. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2031. }
  2032. if (card->info.portname_required)
  2033. qeth_print_status_with_portname(card);
  2034. else
  2035. qeth_print_status_no_portname(card);
  2036. }
  2037. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2038. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2039. {
  2040. struct qeth_buffer_pool_entry *entry;
  2041. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2042. list_for_each_entry(entry,
  2043. &card->qdio.init_pool.entry_list, init_list) {
  2044. qeth_put_buffer_pool_entry(card, entry);
  2045. }
  2046. }
  2047. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2048. struct qeth_card *card)
  2049. {
  2050. struct list_head *plh;
  2051. struct qeth_buffer_pool_entry *entry;
  2052. int i, free;
  2053. struct page *page;
  2054. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2055. return NULL;
  2056. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2057. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2058. free = 1;
  2059. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2060. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2061. free = 0;
  2062. break;
  2063. }
  2064. }
  2065. if (free) {
  2066. list_del_init(&entry->list);
  2067. return entry;
  2068. }
  2069. }
  2070. /* no free buffer in pool so take first one and swap pages */
  2071. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2072. struct qeth_buffer_pool_entry, list);
  2073. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2074. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2075. page = alloc_page(GFP_ATOMIC);
  2076. if (!page) {
  2077. return NULL;
  2078. } else {
  2079. free_page((unsigned long)entry->elements[i]);
  2080. entry->elements[i] = page_address(page);
  2081. if (card->options.performance_stats)
  2082. card->perf_stats.sg_alloc_page_rx++;
  2083. }
  2084. }
  2085. }
  2086. list_del_init(&entry->list);
  2087. return entry;
  2088. }
  2089. static int qeth_init_input_buffer(struct qeth_card *card,
  2090. struct qeth_qdio_buffer *buf)
  2091. {
  2092. struct qeth_buffer_pool_entry *pool_entry;
  2093. int i;
  2094. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2095. if (!pool_entry)
  2096. return 1;
  2097. /*
  2098. * since the buffer is accessed only from the input_tasklet
  2099. * there shouldn't be a need to synchronize; also, since we use
  2100. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2101. * buffers
  2102. */
  2103. buf->pool_entry = pool_entry;
  2104. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2105. buf->buffer->element[i].length = PAGE_SIZE;
  2106. buf->buffer->element[i].addr = pool_entry->elements[i];
  2107. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2108. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2109. else
  2110. buf->buffer->element[i].flags = 0;
  2111. }
  2112. return 0;
  2113. }
  2114. int qeth_init_qdio_queues(struct qeth_card *card)
  2115. {
  2116. int i, j;
  2117. int rc;
  2118. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2119. /* inbound queue */
  2120. memset(card->qdio.in_q->qdio_bufs, 0,
  2121. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2122. qeth_initialize_working_pool_list(card);
  2123. /*give only as many buffers to hardware as we have buffer pool entries*/
  2124. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2125. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2126. card->qdio.in_q->next_buf_to_init =
  2127. card->qdio.in_buf_pool.buf_count - 1;
  2128. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2129. card->qdio.in_buf_pool.buf_count - 1);
  2130. if (rc) {
  2131. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2132. return rc;
  2133. }
  2134. /* outbound queue */
  2135. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2136. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2137. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2138. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2139. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2140. &card->qdio.out_qs[i]->bufs[j]);
  2141. }
  2142. card->qdio.out_qs[i]->card = card;
  2143. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2144. card->qdio.out_qs[i]->do_pack = 0;
  2145. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2146. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2147. atomic_set(&card->qdio.out_qs[i]->state,
  2148. QETH_OUT_Q_UNLOCKED);
  2149. }
  2150. return 0;
  2151. }
  2152. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2153. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2154. {
  2155. switch (link_type) {
  2156. case QETH_LINK_TYPE_HSTR:
  2157. return 2;
  2158. default:
  2159. return 1;
  2160. }
  2161. }
  2162. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2163. struct qeth_ipa_cmd *cmd, __u8 command,
  2164. enum qeth_prot_versions prot)
  2165. {
  2166. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2167. cmd->hdr.command = command;
  2168. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2169. cmd->hdr.seqno = card->seqno.ipa;
  2170. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2171. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2172. if (card->options.layer2)
  2173. cmd->hdr.prim_version_no = 2;
  2174. else
  2175. cmd->hdr.prim_version_no = 1;
  2176. cmd->hdr.param_count = 1;
  2177. cmd->hdr.prot_version = prot;
  2178. cmd->hdr.ipa_supported = 0;
  2179. cmd->hdr.ipa_enabled = 0;
  2180. }
  2181. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2182. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2183. {
  2184. struct qeth_cmd_buffer *iob;
  2185. struct qeth_ipa_cmd *cmd;
  2186. iob = qeth_wait_for_buffer(&card->write);
  2187. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2188. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2189. return iob;
  2190. }
  2191. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2192. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2193. char prot_type)
  2194. {
  2195. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2196. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2197. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2198. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2199. }
  2200. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2201. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2202. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2203. unsigned long),
  2204. void *reply_param)
  2205. {
  2206. int rc;
  2207. char prot_type;
  2208. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2209. if (card->options.layer2)
  2210. if (card->info.type == QETH_CARD_TYPE_OSN)
  2211. prot_type = QETH_PROT_OSN2;
  2212. else
  2213. prot_type = QETH_PROT_LAYER2;
  2214. else
  2215. prot_type = QETH_PROT_TCPIP;
  2216. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2217. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2218. iob, reply_cb, reply_param);
  2219. return rc;
  2220. }
  2221. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2222. static int qeth_send_startstoplan(struct qeth_card *card,
  2223. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2224. {
  2225. int rc;
  2226. struct qeth_cmd_buffer *iob;
  2227. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2228. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2229. return rc;
  2230. }
  2231. int qeth_send_startlan(struct qeth_card *card)
  2232. {
  2233. int rc;
  2234. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2235. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2236. return rc;
  2237. }
  2238. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2239. int qeth_send_stoplan(struct qeth_card *card)
  2240. {
  2241. int rc = 0;
  2242. /*
  2243. * TODO: according to the IPA format document page 14,
  2244. * TCP/IP (we!) never issue a STOPLAN
  2245. * is this right ?!?
  2246. */
  2247. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2248. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2249. return rc;
  2250. }
  2251. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2252. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2253. struct qeth_reply *reply, unsigned long data)
  2254. {
  2255. struct qeth_ipa_cmd *cmd;
  2256. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2257. cmd = (struct qeth_ipa_cmd *) data;
  2258. if (cmd->hdr.return_code == 0)
  2259. cmd->hdr.return_code =
  2260. cmd->data.setadapterparms.hdr.return_code;
  2261. return 0;
  2262. }
  2263. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2264. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2265. struct qeth_reply *reply, unsigned long data)
  2266. {
  2267. struct qeth_ipa_cmd *cmd;
  2268. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2269. cmd = (struct qeth_ipa_cmd *) data;
  2270. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2271. card->info.link_type =
  2272. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2273. card->options.adp.supported_funcs =
  2274. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2275. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2276. }
  2277. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2278. __u32 command, __u32 cmdlen)
  2279. {
  2280. struct qeth_cmd_buffer *iob;
  2281. struct qeth_ipa_cmd *cmd;
  2282. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2283. QETH_PROT_IPV4);
  2284. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2285. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2286. cmd->data.setadapterparms.hdr.command_code = command;
  2287. cmd->data.setadapterparms.hdr.used_total = 1;
  2288. cmd->data.setadapterparms.hdr.seq_no = 1;
  2289. return iob;
  2290. }
  2291. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2292. int qeth_query_setadapterparms(struct qeth_card *card)
  2293. {
  2294. int rc;
  2295. struct qeth_cmd_buffer *iob;
  2296. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2297. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2298. sizeof(struct qeth_ipacmd_setadpparms));
  2299. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2300. return rc;
  2301. }
  2302. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2303. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2304. unsigned int qdio_error, const char *dbftext)
  2305. {
  2306. if (qdio_error) {
  2307. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2308. QETH_DBF_TEXT(QERR, 2, dbftext);
  2309. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2310. buf->element[15].flags & 0xff);
  2311. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2312. buf->element[14].flags & 0xff);
  2313. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2314. if ((buf->element[15].flags & 0xff) == 0x12) {
  2315. card->stats.rx_dropped++;
  2316. return 0;
  2317. } else
  2318. return 1;
  2319. }
  2320. return 0;
  2321. }
  2322. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2323. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2324. {
  2325. struct qeth_qdio_q *queue = card->qdio.in_q;
  2326. int count;
  2327. int i;
  2328. int rc;
  2329. int newcount = 0;
  2330. count = (index < queue->next_buf_to_init)?
  2331. card->qdio.in_buf_pool.buf_count -
  2332. (queue->next_buf_to_init - index) :
  2333. card->qdio.in_buf_pool.buf_count -
  2334. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2335. /* only requeue at a certain threshold to avoid SIGAs */
  2336. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2337. for (i = queue->next_buf_to_init;
  2338. i < queue->next_buf_to_init + count; ++i) {
  2339. if (qeth_init_input_buffer(card,
  2340. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2341. break;
  2342. } else {
  2343. newcount++;
  2344. }
  2345. }
  2346. if (newcount < count) {
  2347. /* we are in memory shortage so we switch back to
  2348. traditional skb allocation and drop packages */
  2349. atomic_set(&card->force_alloc_skb, 3);
  2350. count = newcount;
  2351. } else {
  2352. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2353. }
  2354. /*
  2355. * according to old code it should be avoided to requeue all
  2356. * 128 buffers in order to benefit from PCI avoidance.
  2357. * this function keeps at least one buffer (the buffer at
  2358. * 'index') un-requeued -> this buffer is the first buffer that
  2359. * will be requeued the next time
  2360. */
  2361. if (card->options.performance_stats) {
  2362. card->perf_stats.inbound_do_qdio_cnt++;
  2363. card->perf_stats.inbound_do_qdio_start_time =
  2364. qeth_get_micros();
  2365. }
  2366. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2367. queue->next_buf_to_init, count);
  2368. if (card->options.performance_stats)
  2369. card->perf_stats.inbound_do_qdio_time +=
  2370. qeth_get_micros() -
  2371. card->perf_stats.inbound_do_qdio_start_time;
  2372. if (rc) {
  2373. dev_warn(&card->gdev->dev,
  2374. "QDIO reported an error, rc=%i\n", rc);
  2375. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2376. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2377. }
  2378. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2379. QDIO_MAX_BUFFERS_PER_Q;
  2380. }
  2381. }
  2382. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2383. static int qeth_handle_send_error(struct qeth_card *card,
  2384. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2385. {
  2386. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2387. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2388. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2389. if (sbalf15 == 0) {
  2390. qdio_err = 0;
  2391. } else {
  2392. qdio_err = 1;
  2393. }
  2394. }
  2395. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2396. if (!qdio_err)
  2397. return QETH_SEND_ERROR_NONE;
  2398. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2399. return QETH_SEND_ERROR_RETRY;
  2400. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2401. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2402. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2403. (u16)qdio_err, (u8)sbalf15);
  2404. return QETH_SEND_ERROR_LINK_FAILURE;
  2405. }
  2406. /*
  2407. * Switched to packing state if the number of used buffers on a queue
  2408. * reaches a certain limit.
  2409. */
  2410. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2411. {
  2412. if (!queue->do_pack) {
  2413. if (atomic_read(&queue->used_buffers)
  2414. >= QETH_HIGH_WATERMARK_PACK){
  2415. /* switch non-PACKING -> PACKING */
  2416. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2417. if (queue->card->options.performance_stats)
  2418. queue->card->perf_stats.sc_dp_p++;
  2419. queue->do_pack = 1;
  2420. }
  2421. }
  2422. }
  2423. /*
  2424. * Switches from packing to non-packing mode. If there is a packing
  2425. * buffer on the queue this buffer will be prepared to be flushed.
  2426. * In that case 1 is returned to inform the caller. If no buffer
  2427. * has to be flushed, zero is returned.
  2428. */
  2429. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2430. {
  2431. struct qeth_qdio_out_buffer *buffer;
  2432. int flush_count = 0;
  2433. if (queue->do_pack) {
  2434. if (atomic_read(&queue->used_buffers)
  2435. <= QETH_LOW_WATERMARK_PACK) {
  2436. /* switch PACKING -> non-PACKING */
  2437. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2438. if (queue->card->options.performance_stats)
  2439. queue->card->perf_stats.sc_p_dp++;
  2440. queue->do_pack = 0;
  2441. /* flush packing buffers */
  2442. buffer = &queue->bufs[queue->next_buf_to_fill];
  2443. if ((atomic_read(&buffer->state) ==
  2444. QETH_QDIO_BUF_EMPTY) &&
  2445. (buffer->next_element_to_fill > 0)) {
  2446. atomic_set(&buffer->state,
  2447. QETH_QDIO_BUF_PRIMED);
  2448. flush_count++;
  2449. queue->next_buf_to_fill =
  2450. (queue->next_buf_to_fill + 1) %
  2451. QDIO_MAX_BUFFERS_PER_Q;
  2452. }
  2453. }
  2454. }
  2455. return flush_count;
  2456. }
  2457. /*
  2458. * Called to flush a packing buffer if no more pci flags are on the queue.
  2459. * Checks if there is a packing buffer and prepares it to be flushed.
  2460. * In that case returns 1, otherwise zero.
  2461. */
  2462. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2463. {
  2464. struct qeth_qdio_out_buffer *buffer;
  2465. buffer = &queue->bufs[queue->next_buf_to_fill];
  2466. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2467. (buffer->next_element_to_fill > 0)) {
  2468. /* it's a packing buffer */
  2469. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2470. queue->next_buf_to_fill =
  2471. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2472. return 1;
  2473. }
  2474. return 0;
  2475. }
  2476. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2477. int count)
  2478. {
  2479. struct qeth_qdio_out_buffer *buf;
  2480. int rc;
  2481. int i;
  2482. unsigned int qdio_flags;
  2483. for (i = index; i < index + count; ++i) {
  2484. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2485. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2486. SBAL_FLAGS_LAST_ENTRY;
  2487. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2488. continue;
  2489. if (!queue->do_pack) {
  2490. if ((atomic_read(&queue->used_buffers) >=
  2491. (QETH_HIGH_WATERMARK_PACK -
  2492. QETH_WATERMARK_PACK_FUZZ)) &&
  2493. !atomic_read(&queue->set_pci_flags_count)) {
  2494. /* it's likely that we'll go to packing
  2495. * mode soon */
  2496. atomic_inc(&queue->set_pci_flags_count);
  2497. buf->buffer->element[0].flags |= 0x40;
  2498. }
  2499. } else {
  2500. if (!atomic_read(&queue->set_pci_flags_count)) {
  2501. /*
  2502. * there's no outstanding PCI any more, so we
  2503. * have to request a PCI to be sure the the PCI
  2504. * will wake at some time in the future then we
  2505. * can flush packed buffers that might still be
  2506. * hanging around, which can happen if no
  2507. * further send was requested by the stack
  2508. */
  2509. atomic_inc(&queue->set_pci_flags_count);
  2510. buf->buffer->element[0].flags |= 0x40;
  2511. }
  2512. }
  2513. }
  2514. queue->sync_iqdio_error = 0;
  2515. queue->card->dev->trans_start = jiffies;
  2516. if (queue->card->options.performance_stats) {
  2517. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2518. queue->card->perf_stats.outbound_do_qdio_start_time =
  2519. qeth_get_micros();
  2520. }
  2521. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2522. if (atomic_read(&queue->set_pci_flags_count))
  2523. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2524. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2525. queue->queue_no, index, count);
  2526. if (queue->card->options.performance_stats)
  2527. queue->card->perf_stats.outbound_do_qdio_time +=
  2528. qeth_get_micros() -
  2529. queue->card->perf_stats.outbound_do_qdio_start_time;
  2530. if (rc > 0) {
  2531. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2532. queue->sync_iqdio_error = rc & 3;
  2533. }
  2534. if (rc) {
  2535. queue->card->stats.tx_errors += count;
  2536. /* ignore temporary SIGA errors without busy condition */
  2537. if (rc == QDIO_ERROR_SIGA_TARGET)
  2538. return;
  2539. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2540. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2541. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2542. /* this must not happen under normal circumstances. if it
  2543. * happens something is really wrong -> recover */
  2544. qeth_schedule_recovery(queue->card);
  2545. return;
  2546. }
  2547. atomic_add(count, &queue->used_buffers);
  2548. if (queue->card->options.performance_stats)
  2549. queue->card->perf_stats.bufs_sent += count;
  2550. }
  2551. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2552. {
  2553. int index;
  2554. int flush_cnt = 0;
  2555. int q_was_packing = 0;
  2556. /*
  2557. * check if weed have to switch to non-packing mode or if
  2558. * we have to get a pci flag out on the queue
  2559. */
  2560. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2561. !atomic_read(&queue->set_pci_flags_count)) {
  2562. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2563. QETH_OUT_Q_UNLOCKED) {
  2564. /*
  2565. * If we get in here, there was no action in
  2566. * do_send_packet. So, we check if there is a
  2567. * packing buffer to be flushed here.
  2568. */
  2569. netif_stop_queue(queue->card->dev);
  2570. index = queue->next_buf_to_fill;
  2571. q_was_packing = queue->do_pack;
  2572. /* queue->do_pack may change */
  2573. barrier();
  2574. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2575. if (!flush_cnt &&
  2576. !atomic_read(&queue->set_pci_flags_count))
  2577. flush_cnt +=
  2578. qeth_flush_buffers_on_no_pci(queue);
  2579. if (queue->card->options.performance_stats &&
  2580. q_was_packing)
  2581. queue->card->perf_stats.bufs_sent_pack +=
  2582. flush_cnt;
  2583. if (flush_cnt)
  2584. qeth_flush_buffers(queue, index, flush_cnt);
  2585. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2586. }
  2587. }
  2588. }
  2589. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2590. unsigned int qdio_error, int __queue, int first_element,
  2591. int count, unsigned long card_ptr)
  2592. {
  2593. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2594. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2595. struct qeth_qdio_out_buffer *buffer;
  2596. int i;
  2597. unsigned qeth_send_err;
  2598. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2599. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2600. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2601. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2602. netif_stop_queue(card->dev);
  2603. qeth_schedule_recovery(card);
  2604. return;
  2605. }
  2606. if (card->options.performance_stats) {
  2607. card->perf_stats.outbound_handler_cnt++;
  2608. card->perf_stats.outbound_handler_start_time =
  2609. qeth_get_micros();
  2610. }
  2611. for (i = first_element; i < (first_element + count); ++i) {
  2612. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2613. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2614. __qeth_clear_output_buffer(queue, buffer,
  2615. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2616. }
  2617. atomic_sub(count, &queue->used_buffers);
  2618. /* check if we need to do something on this outbound queue */
  2619. if (card->info.type != QETH_CARD_TYPE_IQD)
  2620. qeth_check_outbound_queue(queue);
  2621. netif_wake_queue(queue->card->dev);
  2622. if (card->options.performance_stats)
  2623. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2624. card->perf_stats.outbound_handler_start_time;
  2625. }
  2626. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2627. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2628. int ipv, int cast_type)
  2629. {
  2630. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2631. return card->qdio.default_out_queue;
  2632. switch (card->qdio.no_out_queues) {
  2633. case 4:
  2634. if (cast_type && card->info.is_multicast_different)
  2635. return card->info.is_multicast_different &
  2636. (card->qdio.no_out_queues - 1);
  2637. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2638. const u8 tos = ip_hdr(skb)->tos;
  2639. if (card->qdio.do_prio_queueing ==
  2640. QETH_PRIO_Q_ING_TOS) {
  2641. if (tos & IP_TOS_NOTIMPORTANT)
  2642. return 3;
  2643. if (tos & IP_TOS_HIGHRELIABILITY)
  2644. return 2;
  2645. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2646. return 1;
  2647. if (tos & IP_TOS_LOWDELAY)
  2648. return 0;
  2649. }
  2650. if (card->qdio.do_prio_queueing ==
  2651. QETH_PRIO_Q_ING_PREC)
  2652. return 3 - (tos >> 6);
  2653. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2654. /* TODO: IPv6!!! */
  2655. }
  2656. return card->qdio.default_out_queue;
  2657. case 1: /* fallthrough for single-out-queue 1920-device */
  2658. default:
  2659. return card->qdio.default_out_queue;
  2660. }
  2661. }
  2662. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2663. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2664. struct sk_buff *skb, int elems)
  2665. {
  2666. int elements_needed = 0;
  2667. if (skb_shinfo(skb)->nr_frags > 0)
  2668. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2669. if (elements_needed == 0)
  2670. elements_needed = 1 + (((((unsigned long) skb->data) %
  2671. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2672. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2673. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2674. "(Number=%d / Length=%d). Discarded.\n",
  2675. (elements_needed+elems), skb->len);
  2676. return 0;
  2677. }
  2678. return elements_needed;
  2679. }
  2680. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2681. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2682. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2683. int offset)
  2684. {
  2685. int length = skb->len;
  2686. int length_here;
  2687. int element;
  2688. char *data;
  2689. int first_lap ;
  2690. element = *next_element_to_fill;
  2691. data = skb->data;
  2692. first_lap = (is_tso == 0 ? 1 : 0);
  2693. if (offset >= 0) {
  2694. data = skb->data + offset;
  2695. length -= offset;
  2696. first_lap = 0;
  2697. }
  2698. while (length > 0) {
  2699. /* length_here is the remaining amount of data in this page */
  2700. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2701. if (length < length_here)
  2702. length_here = length;
  2703. buffer->element[element].addr = data;
  2704. buffer->element[element].length = length_here;
  2705. length -= length_here;
  2706. if (!length) {
  2707. if (first_lap)
  2708. buffer->element[element].flags = 0;
  2709. else
  2710. buffer->element[element].flags =
  2711. SBAL_FLAGS_LAST_FRAG;
  2712. } else {
  2713. if (first_lap)
  2714. buffer->element[element].flags =
  2715. SBAL_FLAGS_FIRST_FRAG;
  2716. else
  2717. buffer->element[element].flags =
  2718. SBAL_FLAGS_MIDDLE_FRAG;
  2719. }
  2720. data += length_here;
  2721. element++;
  2722. first_lap = 0;
  2723. }
  2724. *next_element_to_fill = element;
  2725. }
  2726. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2727. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2728. struct qeth_hdr *hdr, int offset, int hd_len)
  2729. {
  2730. struct qdio_buffer *buffer;
  2731. int flush_cnt = 0, hdr_len, large_send = 0;
  2732. buffer = buf->buffer;
  2733. atomic_inc(&skb->users);
  2734. skb_queue_tail(&buf->skb_list, skb);
  2735. /*check first on TSO ....*/
  2736. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2737. int element = buf->next_element_to_fill;
  2738. hdr_len = sizeof(struct qeth_hdr_tso) +
  2739. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2740. /*fill first buffer entry only with header information */
  2741. buffer->element[element].addr = skb->data;
  2742. buffer->element[element].length = hdr_len;
  2743. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2744. buf->next_element_to_fill++;
  2745. skb->data += hdr_len;
  2746. skb->len -= hdr_len;
  2747. large_send = 1;
  2748. }
  2749. if (offset >= 0) {
  2750. int element = buf->next_element_to_fill;
  2751. buffer->element[element].addr = hdr;
  2752. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2753. hd_len;
  2754. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2755. buf->is_header[element] = 1;
  2756. buf->next_element_to_fill++;
  2757. }
  2758. if (skb_shinfo(skb)->nr_frags == 0)
  2759. __qeth_fill_buffer(skb, buffer, large_send,
  2760. (int *)&buf->next_element_to_fill, offset);
  2761. else
  2762. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2763. (int *)&buf->next_element_to_fill);
  2764. if (!queue->do_pack) {
  2765. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2766. /* set state to PRIMED -> will be flushed */
  2767. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2768. flush_cnt = 1;
  2769. } else {
  2770. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2771. if (queue->card->options.performance_stats)
  2772. queue->card->perf_stats.skbs_sent_pack++;
  2773. if (buf->next_element_to_fill >=
  2774. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2775. /*
  2776. * packed buffer if full -> set state PRIMED
  2777. * -> will be flushed
  2778. */
  2779. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2780. flush_cnt = 1;
  2781. }
  2782. }
  2783. return flush_cnt;
  2784. }
  2785. int qeth_do_send_packet_fast(struct qeth_card *card,
  2786. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2787. struct qeth_hdr *hdr, int elements_needed,
  2788. int offset, int hd_len)
  2789. {
  2790. struct qeth_qdio_out_buffer *buffer;
  2791. struct sk_buff *skb1;
  2792. struct qeth_skb_data *retry_ctrl;
  2793. int index;
  2794. int rc;
  2795. /* spin until we get the queue ... */
  2796. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2797. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2798. /* ... now we've got the queue */
  2799. index = queue->next_buf_to_fill;
  2800. buffer = &queue->bufs[queue->next_buf_to_fill];
  2801. /*
  2802. * check if buffer is empty to make sure that we do not 'overtake'
  2803. * ourselves and try to fill a buffer that is already primed
  2804. */
  2805. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2806. goto out;
  2807. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2808. QDIO_MAX_BUFFERS_PER_Q;
  2809. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2810. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2811. qeth_flush_buffers(queue, index, 1);
  2812. if (queue->sync_iqdio_error == 2) {
  2813. skb1 = skb_dequeue(&buffer->skb_list);
  2814. while (skb1) {
  2815. atomic_dec(&skb1->users);
  2816. skb1 = skb_dequeue(&buffer->skb_list);
  2817. }
  2818. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2819. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2820. retry_ctrl->magic = QETH_SKB_MAGIC;
  2821. retry_ctrl->count = 0;
  2822. }
  2823. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2824. retry_ctrl->count++;
  2825. rc = dev_queue_xmit(skb);
  2826. } else {
  2827. dev_kfree_skb_any(skb);
  2828. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2829. }
  2830. }
  2831. return 0;
  2832. out:
  2833. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2834. return -EBUSY;
  2835. }
  2836. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2837. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2838. struct sk_buff *skb, struct qeth_hdr *hdr,
  2839. int elements_needed)
  2840. {
  2841. struct qeth_qdio_out_buffer *buffer;
  2842. int start_index;
  2843. int flush_count = 0;
  2844. int do_pack = 0;
  2845. int tmp;
  2846. int rc = 0;
  2847. /* spin until we get the queue ... */
  2848. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2849. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2850. start_index = queue->next_buf_to_fill;
  2851. buffer = &queue->bufs[queue->next_buf_to_fill];
  2852. /*
  2853. * check if buffer is empty to make sure that we do not 'overtake'
  2854. * ourselves and try to fill a buffer that is already primed
  2855. */
  2856. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2857. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2858. return -EBUSY;
  2859. }
  2860. /* check if we need to switch packing state of this queue */
  2861. qeth_switch_to_packing_if_needed(queue);
  2862. if (queue->do_pack) {
  2863. do_pack = 1;
  2864. /* does packet fit in current buffer? */
  2865. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2866. buffer->next_element_to_fill) < elements_needed) {
  2867. /* ... no -> set state PRIMED */
  2868. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2869. flush_count++;
  2870. queue->next_buf_to_fill =
  2871. (queue->next_buf_to_fill + 1) %
  2872. QDIO_MAX_BUFFERS_PER_Q;
  2873. buffer = &queue->bufs[queue->next_buf_to_fill];
  2874. /* we did a step forward, so check buffer state
  2875. * again */
  2876. if (atomic_read(&buffer->state) !=
  2877. QETH_QDIO_BUF_EMPTY) {
  2878. qeth_flush_buffers(queue, start_index,
  2879. flush_count);
  2880. atomic_set(&queue->state,
  2881. QETH_OUT_Q_UNLOCKED);
  2882. return -EBUSY;
  2883. }
  2884. }
  2885. }
  2886. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2887. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2888. QDIO_MAX_BUFFERS_PER_Q;
  2889. flush_count += tmp;
  2890. if (flush_count)
  2891. qeth_flush_buffers(queue, start_index, flush_count);
  2892. else if (!atomic_read(&queue->set_pci_flags_count))
  2893. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2894. /*
  2895. * queue->state will go from LOCKED -> UNLOCKED or from
  2896. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2897. * (switch packing state or flush buffer to get another pci flag out).
  2898. * In that case we will enter this loop
  2899. */
  2900. while (atomic_dec_return(&queue->state)) {
  2901. flush_count = 0;
  2902. start_index = queue->next_buf_to_fill;
  2903. /* check if we can go back to non-packing state */
  2904. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2905. /*
  2906. * check if we need to flush a packing buffer to get a pci
  2907. * flag out on the queue
  2908. */
  2909. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2910. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2911. if (flush_count)
  2912. qeth_flush_buffers(queue, start_index, flush_count);
  2913. }
  2914. /* at this point the queue is UNLOCKED again */
  2915. if (queue->card->options.performance_stats && do_pack)
  2916. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2917. return rc;
  2918. }
  2919. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2920. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2921. struct qeth_reply *reply, unsigned long data)
  2922. {
  2923. struct qeth_ipa_cmd *cmd;
  2924. struct qeth_ipacmd_setadpparms *setparms;
  2925. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2926. cmd = (struct qeth_ipa_cmd *) data;
  2927. setparms = &(cmd->data.setadapterparms);
  2928. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2929. if (cmd->hdr.return_code) {
  2930. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2931. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2932. }
  2933. card->info.promisc_mode = setparms->data.mode;
  2934. return 0;
  2935. }
  2936. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2937. {
  2938. enum qeth_ipa_promisc_modes mode;
  2939. struct net_device *dev = card->dev;
  2940. struct qeth_cmd_buffer *iob;
  2941. struct qeth_ipa_cmd *cmd;
  2942. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2943. if (((dev->flags & IFF_PROMISC) &&
  2944. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2945. (!(dev->flags & IFF_PROMISC) &&
  2946. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2947. return;
  2948. mode = SET_PROMISC_MODE_OFF;
  2949. if (dev->flags & IFF_PROMISC)
  2950. mode = SET_PROMISC_MODE_ON;
  2951. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2952. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2953. sizeof(struct qeth_ipacmd_setadpparms));
  2954. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2955. cmd->data.setadapterparms.data.mode = mode;
  2956. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2957. }
  2958. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2959. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2960. {
  2961. struct qeth_card *card;
  2962. char dbf_text[15];
  2963. card = dev->ml_priv;
  2964. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2965. sprintf(dbf_text, "%8x", new_mtu);
  2966. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2967. if (new_mtu < 64)
  2968. return -EINVAL;
  2969. if (new_mtu > 65535)
  2970. return -EINVAL;
  2971. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2972. (!qeth_mtu_is_valid(card, new_mtu)))
  2973. return -EINVAL;
  2974. dev->mtu = new_mtu;
  2975. return 0;
  2976. }
  2977. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2978. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2979. {
  2980. struct qeth_card *card;
  2981. card = dev->ml_priv;
  2982. QETH_DBF_TEXT(TRACE, 5, "getstat");
  2983. return &card->stats;
  2984. }
  2985. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2986. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2987. struct qeth_reply *reply, unsigned long data)
  2988. {
  2989. struct qeth_ipa_cmd *cmd;
  2990. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  2991. cmd = (struct qeth_ipa_cmd *) data;
  2992. if (!card->options.layer2 ||
  2993. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  2994. memcpy(card->dev->dev_addr,
  2995. &cmd->data.setadapterparms.data.change_addr.addr,
  2996. OSA_ADDR_LEN);
  2997. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  2998. }
  2999. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3000. return 0;
  3001. }
  3002. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3003. {
  3004. int rc;
  3005. struct qeth_cmd_buffer *iob;
  3006. struct qeth_ipa_cmd *cmd;
  3007. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3008. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3009. sizeof(struct qeth_ipacmd_setadpparms));
  3010. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3011. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3012. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3013. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3014. card->dev->dev_addr, OSA_ADDR_LEN);
  3015. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3016. NULL);
  3017. return rc;
  3018. }
  3019. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3020. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3021. struct qeth_reply *reply, unsigned long data)
  3022. {
  3023. struct qeth_ipa_cmd *cmd;
  3024. struct qeth_set_access_ctrl *access_ctrl_req;
  3025. int rc;
  3026. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3027. cmd = (struct qeth_ipa_cmd *) data;
  3028. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3029. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3030. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3031. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3032. cmd->data.setadapterparms.hdr.return_code);
  3033. switch (cmd->data.setadapterparms.hdr.return_code) {
  3034. case SET_ACCESS_CTRL_RC_SUCCESS:
  3035. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3036. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3037. {
  3038. card->options.isolation = access_ctrl_req->subcmd_code;
  3039. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3040. dev_info(&card->gdev->dev,
  3041. "QDIO data connection isolation is deactivated\n");
  3042. } else {
  3043. dev_info(&card->gdev->dev,
  3044. "QDIO data connection isolation is activated\n");
  3045. }
  3046. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3047. card->gdev->dev.kobj.name,
  3048. access_ctrl_req->subcmd_code,
  3049. cmd->data.setadapterparms.hdr.return_code);
  3050. rc = 0;
  3051. break;
  3052. }
  3053. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3054. {
  3055. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3056. card->gdev->dev.kobj.name,
  3057. access_ctrl_req->subcmd_code,
  3058. cmd->data.setadapterparms.hdr.return_code);
  3059. dev_err(&card->gdev->dev, "Adapter does not "
  3060. "support QDIO data connection isolation\n");
  3061. /* ensure isolation mode is "none" */
  3062. card->options.isolation = ISOLATION_MODE_NONE;
  3063. rc = -EOPNOTSUPP;
  3064. break;
  3065. }
  3066. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3067. {
  3068. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3069. card->gdev->dev.kobj.name,
  3070. access_ctrl_req->subcmd_code,
  3071. cmd->data.setadapterparms.hdr.return_code);
  3072. dev_err(&card->gdev->dev,
  3073. "Adapter is dedicated. "
  3074. "QDIO data connection isolation not supported\n");
  3075. /* ensure isolation mode is "none" */
  3076. card->options.isolation = ISOLATION_MODE_NONE;
  3077. rc = -EOPNOTSUPP;
  3078. break;
  3079. }
  3080. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3081. {
  3082. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3083. card->gdev->dev.kobj.name,
  3084. access_ctrl_req->subcmd_code,
  3085. cmd->data.setadapterparms.hdr.return_code);
  3086. dev_err(&card->gdev->dev,
  3087. "TSO does not permit QDIO data connection isolation\n");
  3088. /* ensure isolation mode is "none" */
  3089. card->options.isolation = ISOLATION_MODE_NONE;
  3090. rc = -EPERM;
  3091. break;
  3092. }
  3093. default:
  3094. {
  3095. /* this should never happen */
  3096. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3097. "==UNKNOWN\n",
  3098. card->gdev->dev.kobj.name,
  3099. access_ctrl_req->subcmd_code,
  3100. cmd->data.setadapterparms.hdr.return_code);
  3101. /* ensure isolation mode is "none" */
  3102. card->options.isolation = ISOLATION_MODE_NONE;
  3103. rc = 0;
  3104. break;
  3105. }
  3106. }
  3107. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3108. return rc;
  3109. }
  3110. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3111. enum qeth_ipa_isolation_modes isolation)
  3112. {
  3113. int rc;
  3114. struct qeth_cmd_buffer *iob;
  3115. struct qeth_ipa_cmd *cmd;
  3116. struct qeth_set_access_ctrl *access_ctrl_req;
  3117. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3118. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3119. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3120. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3121. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3122. sizeof(struct qeth_set_access_ctrl));
  3123. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3124. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3125. access_ctrl_req->subcmd_code = isolation;
  3126. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3127. NULL);
  3128. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3129. return rc;
  3130. }
  3131. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3132. {
  3133. int rc = 0;
  3134. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3135. if (card->info.type == QETH_CARD_TYPE_OSAE &&
  3136. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3137. rc = qeth_setadpparms_set_access_ctrl(card,
  3138. card->options.isolation);
  3139. if (rc) {
  3140. QETH_DBF_MESSAGE(3,
  3141. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed",
  3142. card->gdev->dev.kobj.name,
  3143. rc);
  3144. }
  3145. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3146. card->options.isolation = ISOLATION_MODE_NONE;
  3147. dev_err(&card->gdev->dev, "Adapter does not "
  3148. "support QDIO data connection isolation\n");
  3149. rc = -EOPNOTSUPP;
  3150. }
  3151. return rc;
  3152. }
  3153. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3154. void qeth_tx_timeout(struct net_device *dev)
  3155. {
  3156. struct qeth_card *card;
  3157. QETH_DBF_TEXT(TRACE, 4, "txtimeo");
  3158. card = dev->ml_priv;
  3159. card->stats.tx_errors++;
  3160. qeth_schedule_recovery(card);
  3161. }
  3162. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3163. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3164. {
  3165. struct qeth_card *card = dev->ml_priv;
  3166. int rc = 0;
  3167. switch (regnum) {
  3168. case MII_BMCR: /* Basic mode control register */
  3169. rc = BMCR_FULLDPLX;
  3170. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3171. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3172. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3173. rc |= BMCR_SPEED100;
  3174. break;
  3175. case MII_BMSR: /* Basic mode status register */
  3176. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3177. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3178. BMSR_100BASE4;
  3179. break;
  3180. case MII_PHYSID1: /* PHYS ID 1 */
  3181. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3182. dev->dev_addr[2];
  3183. rc = (rc >> 5) & 0xFFFF;
  3184. break;
  3185. case MII_PHYSID2: /* PHYS ID 2 */
  3186. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3187. break;
  3188. case MII_ADVERTISE: /* Advertisement control reg */
  3189. rc = ADVERTISE_ALL;
  3190. break;
  3191. case MII_LPA: /* Link partner ability reg */
  3192. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3193. LPA_100BASE4 | LPA_LPACK;
  3194. break;
  3195. case MII_EXPANSION: /* Expansion register */
  3196. break;
  3197. case MII_DCOUNTER: /* disconnect counter */
  3198. break;
  3199. case MII_FCSCOUNTER: /* false carrier counter */
  3200. break;
  3201. case MII_NWAYTEST: /* N-way auto-neg test register */
  3202. break;
  3203. case MII_RERRCOUNTER: /* rx error counter */
  3204. rc = card->stats.rx_errors;
  3205. break;
  3206. case MII_SREVISION: /* silicon revision */
  3207. break;
  3208. case MII_RESV1: /* reserved 1 */
  3209. break;
  3210. case MII_LBRERROR: /* loopback, rx, bypass error */
  3211. break;
  3212. case MII_PHYADDR: /* physical address */
  3213. break;
  3214. case MII_RESV2: /* reserved 2 */
  3215. break;
  3216. case MII_TPISTATUS: /* TPI status for 10mbps */
  3217. break;
  3218. case MII_NCONFIG: /* network interface config */
  3219. break;
  3220. default:
  3221. break;
  3222. }
  3223. return rc;
  3224. }
  3225. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3226. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3227. struct qeth_cmd_buffer *iob, int len,
  3228. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3229. unsigned long),
  3230. void *reply_param)
  3231. {
  3232. u16 s1, s2;
  3233. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3234. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3235. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3236. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3237. /* adjust PDU length fields in IPA_PDU_HEADER */
  3238. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3239. s2 = (u32) len;
  3240. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3241. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3242. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3243. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3244. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3245. reply_cb, reply_param);
  3246. }
  3247. static int qeth_snmp_command_cb(struct qeth_card *card,
  3248. struct qeth_reply *reply, unsigned long sdata)
  3249. {
  3250. struct qeth_ipa_cmd *cmd;
  3251. struct qeth_arp_query_info *qinfo;
  3252. struct qeth_snmp_cmd *snmp;
  3253. unsigned char *data;
  3254. __u16 data_len;
  3255. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3256. cmd = (struct qeth_ipa_cmd *) sdata;
  3257. data = (unsigned char *)((char *)cmd - reply->offset);
  3258. qinfo = (struct qeth_arp_query_info *) reply->param;
  3259. snmp = &cmd->data.setadapterparms.data.snmp;
  3260. if (cmd->hdr.return_code) {
  3261. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3262. return 0;
  3263. }
  3264. if (cmd->data.setadapterparms.hdr.return_code) {
  3265. cmd->hdr.return_code =
  3266. cmd->data.setadapterparms.hdr.return_code;
  3267. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3268. return 0;
  3269. }
  3270. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3271. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3272. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3273. else
  3274. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3275. /* check if there is enough room in userspace */
  3276. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3277. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3278. cmd->hdr.return_code = -ENOMEM;
  3279. return 0;
  3280. }
  3281. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3282. cmd->data.setadapterparms.hdr.used_total);
  3283. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3284. cmd->data.setadapterparms.hdr.seq_no);
  3285. /*copy entries to user buffer*/
  3286. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3287. memcpy(qinfo->udata + qinfo->udata_offset,
  3288. (char *)snmp,
  3289. data_len + offsetof(struct qeth_snmp_cmd, data));
  3290. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3291. } else {
  3292. memcpy(qinfo->udata + qinfo->udata_offset,
  3293. (char *)&snmp->request, data_len);
  3294. }
  3295. qinfo->udata_offset += data_len;
  3296. /* check if all replies received ... */
  3297. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3298. cmd->data.setadapterparms.hdr.used_total);
  3299. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3300. cmd->data.setadapterparms.hdr.seq_no);
  3301. if (cmd->data.setadapterparms.hdr.seq_no <
  3302. cmd->data.setadapterparms.hdr.used_total)
  3303. return 1;
  3304. return 0;
  3305. }
  3306. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3307. {
  3308. struct qeth_cmd_buffer *iob;
  3309. struct qeth_ipa_cmd *cmd;
  3310. struct qeth_snmp_ureq *ureq;
  3311. int req_len;
  3312. struct qeth_arp_query_info qinfo = {0, };
  3313. int rc = 0;
  3314. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3315. if (card->info.guestlan)
  3316. return -EOPNOTSUPP;
  3317. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3318. (!card->options.layer2)) {
  3319. return -EOPNOTSUPP;
  3320. }
  3321. /* skip 4 bytes (data_len struct member) to get req_len */
  3322. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3323. return -EFAULT;
  3324. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3325. if (!ureq) {
  3326. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3327. return -ENOMEM;
  3328. }
  3329. if (copy_from_user(ureq, udata,
  3330. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3331. kfree(ureq);
  3332. return -EFAULT;
  3333. }
  3334. qinfo.udata_len = ureq->hdr.data_len;
  3335. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3336. if (!qinfo.udata) {
  3337. kfree(ureq);
  3338. return -ENOMEM;
  3339. }
  3340. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3341. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3342. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3343. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3344. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3345. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3346. qeth_snmp_command_cb, (void *)&qinfo);
  3347. if (rc)
  3348. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3349. QETH_CARD_IFNAME(card), rc);
  3350. else {
  3351. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3352. rc = -EFAULT;
  3353. }
  3354. kfree(ureq);
  3355. kfree(qinfo.udata);
  3356. return rc;
  3357. }
  3358. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3359. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3360. {
  3361. switch (card->info.type) {
  3362. case QETH_CARD_TYPE_IQD:
  3363. return 2;
  3364. default:
  3365. return 0;
  3366. }
  3367. }
  3368. static int qeth_qdio_establish(struct qeth_card *card)
  3369. {
  3370. struct qdio_initialize init_data;
  3371. char *qib_param_field;
  3372. struct qdio_buffer **in_sbal_ptrs;
  3373. struct qdio_buffer **out_sbal_ptrs;
  3374. int i, j, k;
  3375. int rc = 0;
  3376. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3377. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3378. GFP_KERNEL);
  3379. if (!qib_param_field)
  3380. return -ENOMEM;
  3381. qeth_create_qib_param_field(card, qib_param_field);
  3382. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3383. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3384. GFP_KERNEL);
  3385. if (!in_sbal_ptrs) {
  3386. kfree(qib_param_field);
  3387. return -ENOMEM;
  3388. }
  3389. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3390. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3391. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3392. out_sbal_ptrs =
  3393. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3394. sizeof(void *), GFP_KERNEL);
  3395. if (!out_sbal_ptrs) {
  3396. kfree(in_sbal_ptrs);
  3397. kfree(qib_param_field);
  3398. return -ENOMEM;
  3399. }
  3400. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3401. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3402. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3403. card->qdio.out_qs[i]->bufs[j].buffer);
  3404. }
  3405. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3406. init_data.cdev = CARD_DDEV(card);
  3407. init_data.q_format = qeth_get_qdio_q_format(card);
  3408. init_data.qib_param_field_format = 0;
  3409. init_data.qib_param_field = qib_param_field;
  3410. init_data.no_input_qs = 1;
  3411. init_data.no_output_qs = card->qdio.no_out_queues;
  3412. init_data.input_handler = card->discipline.input_handler;
  3413. init_data.output_handler = card->discipline.output_handler;
  3414. init_data.int_parm = (unsigned long) card;
  3415. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3416. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3417. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3418. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3419. rc = qdio_initialize(&init_data);
  3420. if (rc)
  3421. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3422. }
  3423. kfree(out_sbal_ptrs);
  3424. kfree(in_sbal_ptrs);
  3425. kfree(qib_param_field);
  3426. return rc;
  3427. }
  3428. static void qeth_core_free_card(struct qeth_card *card)
  3429. {
  3430. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3431. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3432. qeth_clean_channel(&card->read);
  3433. qeth_clean_channel(&card->write);
  3434. if (card->dev)
  3435. free_netdev(card->dev);
  3436. kfree(card->ip_tbd_list);
  3437. qeth_free_qdio_buffers(card);
  3438. unregister_service_level(&card->qeth_service_level);
  3439. kfree(card);
  3440. }
  3441. static struct ccw_device_id qeth_ids[] = {
  3442. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3443. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3444. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3445. {},
  3446. };
  3447. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3448. static struct ccw_driver qeth_ccw_driver = {
  3449. .name = "qeth",
  3450. .ids = qeth_ids,
  3451. .probe = ccwgroup_probe_ccwdev,
  3452. .remove = ccwgroup_remove_ccwdev,
  3453. };
  3454. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3455. unsigned long driver_id)
  3456. {
  3457. return ccwgroup_create_from_string(root_dev, driver_id,
  3458. &qeth_ccw_driver, 3, buf);
  3459. }
  3460. int qeth_core_hardsetup_card(struct qeth_card *card)
  3461. {
  3462. int retries = 0;
  3463. int rc;
  3464. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3465. atomic_set(&card->force_alloc_skb, 0);
  3466. retry:
  3467. if (retries)
  3468. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3469. dev_name(&card->gdev->dev));
  3470. ccw_device_set_offline(CARD_DDEV(card));
  3471. ccw_device_set_offline(CARD_WDEV(card));
  3472. ccw_device_set_offline(CARD_RDEV(card));
  3473. rc = ccw_device_set_online(CARD_RDEV(card));
  3474. if (rc)
  3475. goto retriable;
  3476. rc = ccw_device_set_online(CARD_WDEV(card));
  3477. if (rc)
  3478. goto retriable;
  3479. rc = ccw_device_set_online(CARD_DDEV(card));
  3480. if (rc)
  3481. goto retriable;
  3482. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3483. retriable:
  3484. if (rc == -ERESTARTSYS) {
  3485. QETH_DBF_TEXT(SETUP, 2, "break1");
  3486. return rc;
  3487. } else if (rc) {
  3488. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3489. if (++retries > 3)
  3490. goto out;
  3491. else
  3492. goto retry;
  3493. }
  3494. qeth_init_tokens(card);
  3495. qeth_init_func_level(card);
  3496. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3497. if (rc == -ERESTARTSYS) {
  3498. QETH_DBF_TEXT(SETUP, 2, "break2");
  3499. return rc;
  3500. } else if (rc) {
  3501. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3502. if (--retries < 0)
  3503. goto out;
  3504. else
  3505. goto retry;
  3506. }
  3507. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3508. if (rc == -ERESTARTSYS) {
  3509. QETH_DBF_TEXT(SETUP, 2, "break3");
  3510. return rc;
  3511. } else if (rc) {
  3512. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3513. if (--retries < 0)
  3514. goto out;
  3515. else
  3516. goto retry;
  3517. }
  3518. rc = qeth_mpc_initialize(card);
  3519. if (rc) {
  3520. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3521. goto out;
  3522. }
  3523. return 0;
  3524. out:
  3525. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3526. "an error on the device\n");
  3527. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3528. dev_name(&card->gdev->dev), rc);
  3529. return rc;
  3530. }
  3531. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3532. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3533. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3534. {
  3535. struct page *page = virt_to_page(element->addr);
  3536. if (*pskb == NULL) {
  3537. /* the upper protocol layers assume that there is data in the
  3538. * skb itself. Copy a small amount (64 bytes) to make them
  3539. * happy. */
  3540. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3541. if (!(*pskb))
  3542. return -ENOMEM;
  3543. skb_reserve(*pskb, ETH_HLEN);
  3544. if (data_len <= 64) {
  3545. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3546. data_len);
  3547. } else {
  3548. get_page(page);
  3549. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3550. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3551. data_len - 64);
  3552. (*pskb)->data_len += data_len - 64;
  3553. (*pskb)->len += data_len - 64;
  3554. (*pskb)->truesize += data_len - 64;
  3555. (*pfrag)++;
  3556. }
  3557. } else {
  3558. get_page(page);
  3559. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3560. (*pskb)->data_len += data_len;
  3561. (*pskb)->len += data_len;
  3562. (*pskb)->truesize += data_len;
  3563. (*pfrag)++;
  3564. }
  3565. return 0;
  3566. }
  3567. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3568. struct qdio_buffer *buffer,
  3569. struct qdio_buffer_element **__element, int *__offset,
  3570. struct qeth_hdr **hdr)
  3571. {
  3572. struct qdio_buffer_element *element = *__element;
  3573. int offset = *__offset;
  3574. struct sk_buff *skb = NULL;
  3575. int skb_len = 0;
  3576. void *data_ptr;
  3577. int data_len;
  3578. int headroom = 0;
  3579. int use_rx_sg = 0;
  3580. int frag = 0;
  3581. /* qeth_hdr must not cross element boundaries */
  3582. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3583. if (qeth_is_last_sbale(element))
  3584. return NULL;
  3585. element++;
  3586. offset = 0;
  3587. if (element->length < sizeof(struct qeth_hdr))
  3588. return NULL;
  3589. }
  3590. *hdr = element->addr + offset;
  3591. offset += sizeof(struct qeth_hdr);
  3592. switch ((*hdr)->hdr.l2.id) {
  3593. case QETH_HEADER_TYPE_LAYER2:
  3594. skb_len = (*hdr)->hdr.l2.pkt_length;
  3595. break;
  3596. case QETH_HEADER_TYPE_LAYER3:
  3597. skb_len = (*hdr)->hdr.l3.length;
  3598. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3599. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3600. headroom = TR_HLEN;
  3601. else
  3602. headroom = ETH_HLEN;
  3603. break;
  3604. case QETH_HEADER_TYPE_OSN:
  3605. skb_len = (*hdr)->hdr.osn.pdu_length;
  3606. headroom = sizeof(struct qeth_hdr);
  3607. break;
  3608. default:
  3609. break;
  3610. }
  3611. if (!skb_len)
  3612. return NULL;
  3613. if ((skb_len >= card->options.rx_sg_cb) &&
  3614. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3615. (!atomic_read(&card->force_alloc_skb))) {
  3616. use_rx_sg = 1;
  3617. } else {
  3618. skb = dev_alloc_skb(skb_len + headroom);
  3619. if (!skb)
  3620. goto no_mem;
  3621. if (headroom)
  3622. skb_reserve(skb, headroom);
  3623. }
  3624. data_ptr = element->addr + offset;
  3625. while (skb_len) {
  3626. data_len = min(skb_len, (int)(element->length - offset));
  3627. if (data_len) {
  3628. if (use_rx_sg) {
  3629. if (qeth_create_skb_frag(element, &skb, offset,
  3630. &frag, data_len))
  3631. goto no_mem;
  3632. } else {
  3633. memcpy(skb_put(skb, data_len), data_ptr,
  3634. data_len);
  3635. }
  3636. }
  3637. skb_len -= data_len;
  3638. if (skb_len) {
  3639. if (qeth_is_last_sbale(element)) {
  3640. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3641. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3642. CARD_BUS_ID(card));
  3643. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3644. QETH_DBF_TEXT_(QERR, 2, "%s",
  3645. CARD_BUS_ID(card));
  3646. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3647. dev_kfree_skb_any(skb);
  3648. card->stats.rx_errors++;
  3649. return NULL;
  3650. }
  3651. element++;
  3652. offset = 0;
  3653. data_ptr = element->addr;
  3654. } else {
  3655. offset += data_len;
  3656. }
  3657. }
  3658. *__element = element;
  3659. *__offset = offset;
  3660. if (use_rx_sg && card->options.performance_stats) {
  3661. card->perf_stats.sg_skbs_rx++;
  3662. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3663. }
  3664. return skb;
  3665. no_mem:
  3666. if (net_ratelimit()) {
  3667. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3668. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3669. }
  3670. card->stats.rx_dropped++;
  3671. return NULL;
  3672. }
  3673. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3674. static void qeth_unregister_dbf_views(void)
  3675. {
  3676. int x;
  3677. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3678. debug_unregister(qeth_dbf[x].id);
  3679. qeth_dbf[x].id = NULL;
  3680. }
  3681. }
  3682. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3683. {
  3684. char dbf_txt_buf[32];
  3685. va_list args;
  3686. if (level > (qeth_dbf[dbf_nix].id)->level)
  3687. return;
  3688. va_start(args, fmt);
  3689. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3690. va_end(args);
  3691. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3692. }
  3693. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3694. static int qeth_register_dbf_views(void)
  3695. {
  3696. int ret;
  3697. int x;
  3698. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3699. /* register the areas */
  3700. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3701. qeth_dbf[x].pages,
  3702. qeth_dbf[x].areas,
  3703. qeth_dbf[x].len);
  3704. if (qeth_dbf[x].id == NULL) {
  3705. qeth_unregister_dbf_views();
  3706. return -ENOMEM;
  3707. }
  3708. /* register a view */
  3709. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3710. if (ret) {
  3711. qeth_unregister_dbf_views();
  3712. return ret;
  3713. }
  3714. /* set a passing level */
  3715. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3716. }
  3717. return 0;
  3718. }
  3719. int qeth_core_load_discipline(struct qeth_card *card,
  3720. enum qeth_discipline_id discipline)
  3721. {
  3722. int rc = 0;
  3723. switch (discipline) {
  3724. case QETH_DISCIPLINE_LAYER3:
  3725. card->discipline.ccwgdriver = try_then_request_module(
  3726. symbol_get(qeth_l3_ccwgroup_driver),
  3727. "qeth_l3");
  3728. break;
  3729. case QETH_DISCIPLINE_LAYER2:
  3730. card->discipline.ccwgdriver = try_then_request_module(
  3731. symbol_get(qeth_l2_ccwgroup_driver),
  3732. "qeth_l2");
  3733. break;
  3734. }
  3735. if (!card->discipline.ccwgdriver) {
  3736. dev_err(&card->gdev->dev, "There is no kernel module to "
  3737. "support discipline %d\n", discipline);
  3738. rc = -EINVAL;
  3739. }
  3740. return rc;
  3741. }
  3742. void qeth_core_free_discipline(struct qeth_card *card)
  3743. {
  3744. if (card->options.layer2)
  3745. symbol_put(qeth_l2_ccwgroup_driver);
  3746. else
  3747. symbol_put(qeth_l3_ccwgroup_driver);
  3748. card->discipline.ccwgdriver = NULL;
  3749. }
  3750. static void qeth_determine_capabilities(struct qeth_card *card)
  3751. {
  3752. int rc;
  3753. int length;
  3754. char *prcd;
  3755. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3756. rc = ccw_device_set_online(CARD_DDEV(card));
  3757. if (rc) {
  3758. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3759. goto out;
  3760. }
  3761. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3762. if (rc) {
  3763. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3764. dev_name(&card->gdev->dev), rc);
  3765. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3766. goto out_offline;
  3767. }
  3768. qeth_configure_unitaddr(card, prcd);
  3769. qeth_configure_blkt_default(card, prcd);
  3770. kfree(prcd);
  3771. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3772. if (rc)
  3773. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3774. out_offline:
  3775. ccw_device_set_offline(CARD_DDEV(card));
  3776. out:
  3777. return;
  3778. }
  3779. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3780. {
  3781. struct qeth_card *card;
  3782. struct device *dev;
  3783. int rc;
  3784. unsigned long flags;
  3785. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3786. dev = &gdev->dev;
  3787. if (!get_device(dev))
  3788. return -ENODEV;
  3789. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3790. card = qeth_alloc_card();
  3791. if (!card) {
  3792. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3793. rc = -ENOMEM;
  3794. goto err_dev;
  3795. }
  3796. card->read.ccwdev = gdev->cdev[0];
  3797. card->write.ccwdev = gdev->cdev[1];
  3798. card->data.ccwdev = gdev->cdev[2];
  3799. dev_set_drvdata(&gdev->dev, card);
  3800. card->gdev = gdev;
  3801. gdev->cdev[0]->handler = qeth_irq;
  3802. gdev->cdev[1]->handler = qeth_irq;
  3803. gdev->cdev[2]->handler = qeth_irq;
  3804. rc = qeth_determine_card_type(card);
  3805. if (rc) {
  3806. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3807. goto err_card;
  3808. }
  3809. rc = qeth_setup_card(card);
  3810. if (rc) {
  3811. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3812. goto err_card;
  3813. }
  3814. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3815. rc = qeth_core_create_osn_attributes(dev);
  3816. if (rc)
  3817. goto err_card;
  3818. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3819. if (rc) {
  3820. qeth_core_remove_osn_attributes(dev);
  3821. goto err_card;
  3822. }
  3823. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3824. if (rc) {
  3825. qeth_core_free_discipline(card);
  3826. qeth_core_remove_osn_attributes(dev);
  3827. goto err_card;
  3828. }
  3829. } else {
  3830. rc = qeth_core_create_device_attributes(dev);
  3831. if (rc)
  3832. goto err_card;
  3833. }
  3834. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3835. list_add_tail(&card->list, &qeth_core_card_list.list);
  3836. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3837. qeth_determine_capabilities(card);
  3838. return 0;
  3839. err_card:
  3840. qeth_core_free_card(card);
  3841. err_dev:
  3842. put_device(dev);
  3843. return rc;
  3844. }
  3845. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3846. {
  3847. unsigned long flags;
  3848. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3849. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3850. if (card->discipline.ccwgdriver) {
  3851. card->discipline.ccwgdriver->remove(gdev);
  3852. qeth_core_free_discipline(card);
  3853. }
  3854. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3855. qeth_core_remove_osn_attributes(&gdev->dev);
  3856. } else {
  3857. qeth_core_remove_device_attributes(&gdev->dev);
  3858. }
  3859. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3860. list_del(&card->list);
  3861. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3862. qeth_core_free_card(card);
  3863. dev_set_drvdata(&gdev->dev, NULL);
  3864. put_device(&gdev->dev);
  3865. return;
  3866. }
  3867. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3868. {
  3869. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3870. int rc = 0;
  3871. int def_discipline;
  3872. if (!card->discipline.ccwgdriver) {
  3873. if (card->info.type == QETH_CARD_TYPE_IQD)
  3874. def_discipline = QETH_DISCIPLINE_LAYER3;
  3875. else
  3876. def_discipline = QETH_DISCIPLINE_LAYER2;
  3877. rc = qeth_core_load_discipline(card, def_discipline);
  3878. if (rc)
  3879. goto err;
  3880. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3881. if (rc)
  3882. goto err;
  3883. }
  3884. rc = card->discipline.ccwgdriver->set_online(gdev);
  3885. err:
  3886. return rc;
  3887. }
  3888. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3889. {
  3890. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3891. return card->discipline.ccwgdriver->set_offline(gdev);
  3892. }
  3893. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3894. {
  3895. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3896. if (card->discipline.ccwgdriver &&
  3897. card->discipline.ccwgdriver->shutdown)
  3898. card->discipline.ccwgdriver->shutdown(gdev);
  3899. }
  3900. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3901. {
  3902. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3903. if (card->discipline.ccwgdriver &&
  3904. card->discipline.ccwgdriver->prepare)
  3905. return card->discipline.ccwgdriver->prepare(gdev);
  3906. return 0;
  3907. }
  3908. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3909. {
  3910. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3911. if (card->discipline.ccwgdriver &&
  3912. card->discipline.ccwgdriver->complete)
  3913. card->discipline.ccwgdriver->complete(gdev);
  3914. }
  3915. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3916. {
  3917. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3918. if (card->discipline.ccwgdriver &&
  3919. card->discipline.ccwgdriver->freeze)
  3920. return card->discipline.ccwgdriver->freeze(gdev);
  3921. return 0;
  3922. }
  3923. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3924. {
  3925. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3926. if (card->discipline.ccwgdriver &&
  3927. card->discipline.ccwgdriver->thaw)
  3928. return card->discipline.ccwgdriver->thaw(gdev);
  3929. return 0;
  3930. }
  3931. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3932. {
  3933. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3934. if (card->discipline.ccwgdriver &&
  3935. card->discipline.ccwgdriver->restore)
  3936. return card->discipline.ccwgdriver->restore(gdev);
  3937. return 0;
  3938. }
  3939. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3940. .owner = THIS_MODULE,
  3941. .name = "qeth",
  3942. .driver_id = 0xD8C5E3C8,
  3943. .probe = qeth_core_probe_device,
  3944. .remove = qeth_core_remove_device,
  3945. .set_online = qeth_core_set_online,
  3946. .set_offline = qeth_core_set_offline,
  3947. .shutdown = qeth_core_shutdown,
  3948. .prepare = qeth_core_prepare,
  3949. .complete = qeth_core_complete,
  3950. .freeze = qeth_core_freeze,
  3951. .thaw = qeth_core_thaw,
  3952. .restore = qeth_core_restore,
  3953. };
  3954. static ssize_t
  3955. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3956. size_t count)
  3957. {
  3958. int err;
  3959. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3960. qeth_core_ccwgroup_driver.driver_id);
  3961. if (err)
  3962. return err;
  3963. else
  3964. return count;
  3965. }
  3966. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3967. static struct {
  3968. const char str[ETH_GSTRING_LEN];
  3969. } qeth_ethtool_stats_keys[] = {
  3970. /* 0 */{"rx skbs"},
  3971. {"rx buffers"},
  3972. {"tx skbs"},
  3973. {"tx buffers"},
  3974. {"tx skbs no packing"},
  3975. {"tx buffers no packing"},
  3976. {"tx skbs packing"},
  3977. {"tx buffers packing"},
  3978. {"tx sg skbs"},
  3979. {"tx sg frags"},
  3980. /* 10 */{"rx sg skbs"},
  3981. {"rx sg frags"},
  3982. {"rx sg page allocs"},
  3983. {"tx large kbytes"},
  3984. {"tx large count"},
  3985. {"tx pk state ch n->p"},
  3986. {"tx pk state ch p->n"},
  3987. {"tx pk watermark low"},
  3988. {"tx pk watermark high"},
  3989. {"queue 0 buffer usage"},
  3990. /* 20 */{"queue 1 buffer usage"},
  3991. {"queue 2 buffer usage"},
  3992. {"queue 3 buffer usage"},
  3993. {"rx handler time"},
  3994. {"rx handler count"},
  3995. {"rx do_QDIO time"},
  3996. {"rx do_QDIO count"},
  3997. {"tx handler time"},
  3998. {"tx handler count"},
  3999. {"tx time"},
  4000. /* 30 */{"tx count"},
  4001. {"tx do_QDIO time"},
  4002. {"tx do_QDIO count"},
  4003. {"tx csum"},
  4004. {"tx lin"},
  4005. };
  4006. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4007. {
  4008. switch (stringset) {
  4009. case ETH_SS_STATS:
  4010. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4011. default:
  4012. return -EINVAL;
  4013. }
  4014. }
  4015. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4016. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4017. struct ethtool_stats *stats, u64 *data)
  4018. {
  4019. struct qeth_card *card = dev->ml_priv;
  4020. data[0] = card->stats.rx_packets -
  4021. card->perf_stats.initial_rx_packets;
  4022. data[1] = card->perf_stats.bufs_rec;
  4023. data[2] = card->stats.tx_packets -
  4024. card->perf_stats.initial_tx_packets;
  4025. data[3] = card->perf_stats.bufs_sent;
  4026. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4027. - card->perf_stats.skbs_sent_pack;
  4028. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4029. data[6] = card->perf_stats.skbs_sent_pack;
  4030. data[7] = card->perf_stats.bufs_sent_pack;
  4031. data[8] = card->perf_stats.sg_skbs_sent;
  4032. data[9] = card->perf_stats.sg_frags_sent;
  4033. data[10] = card->perf_stats.sg_skbs_rx;
  4034. data[11] = card->perf_stats.sg_frags_rx;
  4035. data[12] = card->perf_stats.sg_alloc_page_rx;
  4036. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4037. data[14] = card->perf_stats.large_send_cnt;
  4038. data[15] = card->perf_stats.sc_dp_p;
  4039. data[16] = card->perf_stats.sc_p_dp;
  4040. data[17] = QETH_LOW_WATERMARK_PACK;
  4041. data[18] = QETH_HIGH_WATERMARK_PACK;
  4042. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4043. data[20] = (card->qdio.no_out_queues > 1) ?
  4044. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4045. data[21] = (card->qdio.no_out_queues > 2) ?
  4046. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4047. data[22] = (card->qdio.no_out_queues > 3) ?
  4048. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4049. data[23] = card->perf_stats.inbound_time;
  4050. data[24] = card->perf_stats.inbound_cnt;
  4051. data[25] = card->perf_stats.inbound_do_qdio_time;
  4052. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4053. data[27] = card->perf_stats.outbound_handler_time;
  4054. data[28] = card->perf_stats.outbound_handler_cnt;
  4055. data[29] = card->perf_stats.outbound_time;
  4056. data[30] = card->perf_stats.outbound_cnt;
  4057. data[31] = card->perf_stats.outbound_do_qdio_time;
  4058. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4059. data[33] = card->perf_stats.tx_csum;
  4060. data[34] = card->perf_stats.tx_lin;
  4061. }
  4062. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4063. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4064. {
  4065. switch (stringset) {
  4066. case ETH_SS_STATS:
  4067. memcpy(data, &qeth_ethtool_stats_keys,
  4068. sizeof(qeth_ethtool_stats_keys));
  4069. break;
  4070. default:
  4071. WARN_ON(1);
  4072. break;
  4073. }
  4074. }
  4075. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4076. void qeth_core_get_drvinfo(struct net_device *dev,
  4077. struct ethtool_drvinfo *info)
  4078. {
  4079. struct qeth_card *card = dev->ml_priv;
  4080. if (card->options.layer2)
  4081. strcpy(info->driver, "qeth_l2");
  4082. else
  4083. strcpy(info->driver, "qeth_l3");
  4084. strcpy(info->version, "1.0");
  4085. strcpy(info->fw_version, card->info.mcl_level);
  4086. sprintf(info->bus_info, "%s/%s/%s",
  4087. CARD_RDEV_ID(card),
  4088. CARD_WDEV_ID(card),
  4089. CARD_DDEV_ID(card));
  4090. }
  4091. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4092. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4093. struct ethtool_cmd *ecmd)
  4094. {
  4095. struct qeth_card *card = netdev->ml_priv;
  4096. enum qeth_link_types link_type;
  4097. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4098. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4099. else
  4100. link_type = card->info.link_type;
  4101. ecmd->transceiver = XCVR_INTERNAL;
  4102. ecmd->supported = SUPPORTED_Autoneg;
  4103. ecmd->advertising = ADVERTISED_Autoneg;
  4104. ecmd->duplex = DUPLEX_FULL;
  4105. ecmd->autoneg = AUTONEG_ENABLE;
  4106. switch (link_type) {
  4107. case QETH_LINK_TYPE_FAST_ETH:
  4108. case QETH_LINK_TYPE_LANE_ETH100:
  4109. ecmd->supported |= SUPPORTED_10baseT_Half |
  4110. SUPPORTED_10baseT_Full |
  4111. SUPPORTED_100baseT_Half |
  4112. SUPPORTED_100baseT_Full |
  4113. SUPPORTED_TP;
  4114. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4115. ADVERTISED_10baseT_Full |
  4116. ADVERTISED_100baseT_Half |
  4117. ADVERTISED_100baseT_Full |
  4118. ADVERTISED_TP;
  4119. ecmd->speed = SPEED_100;
  4120. ecmd->port = PORT_TP;
  4121. break;
  4122. case QETH_LINK_TYPE_GBIT_ETH:
  4123. case QETH_LINK_TYPE_LANE_ETH1000:
  4124. ecmd->supported |= SUPPORTED_10baseT_Half |
  4125. SUPPORTED_10baseT_Full |
  4126. SUPPORTED_100baseT_Half |
  4127. SUPPORTED_100baseT_Full |
  4128. SUPPORTED_1000baseT_Half |
  4129. SUPPORTED_1000baseT_Full |
  4130. SUPPORTED_FIBRE;
  4131. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4132. ADVERTISED_10baseT_Full |
  4133. ADVERTISED_100baseT_Half |
  4134. ADVERTISED_100baseT_Full |
  4135. ADVERTISED_1000baseT_Half |
  4136. ADVERTISED_1000baseT_Full |
  4137. ADVERTISED_FIBRE;
  4138. ecmd->speed = SPEED_1000;
  4139. ecmd->port = PORT_FIBRE;
  4140. break;
  4141. case QETH_LINK_TYPE_10GBIT_ETH:
  4142. ecmd->supported |= SUPPORTED_10baseT_Half |
  4143. SUPPORTED_10baseT_Full |
  4144. SUPPORTED_100baseT_Half |
  4145. SUPPORTED_100baseT_Full |
  4146. SUPPORTED_1000baseT_Half |
  4147. SUPPORTED_1000baseT_Full |
  4148. SUPPORTED_10000baseT_Full |
  4149. SUPPORTED_FIBRE;
  4150. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4151. ADVERTISED_10baseT_Full |
  4152. ADVERTISED_100baseT_Half |
  4153. ADVERTISED_100baseT_Full |
  4154. ADVERTISED_1000baseT_Half |
  4155. ADVERTISED_1000baseT_Full |
  4156. ADVERTISED_10000baseT_Full |
  4157. ADVERTISED_FIBRE;
  4158. ecmd->speed = SPEED_10000;
  4159. ecmd->port = PORT_FIBRE;
  4160. break;
  4161. default:
  4162. ecmd->supported |= SUPPORTED_10baseT_Half |
  4163. SUPPORTED_10baseT_Full |
  4164. SUPPORTED_TP;
  4165. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4166. ADVERTISED_10baseT_Full |
  4167. ADVERTISED_TP;
  4168. ecmd->speed = SPEED_10;
  4169. ecmd->port = PORT_TP;
  4170. }
  4171. return 0;
  4172. }
  4173. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4174. static int __init qeth_core_init(void)
  4175. {
  4176. int rc;
  4177. pr_info("loading core functions\n");
  4178. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4179. rwlock_init(&qeth_core_card_list.rwlock);
  4180. rc = qeth_register_dbf_views();
  4181. if (rc)
  4182. goto out_err;
  4183. rc = ccw_driver_register(&qeth_ccw_driver);
  4184. if (rc)
  4185. goto ccw_err;
  4186. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4187. if (rc)
  4188. goto ccwgroup_err;
  4189. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4190. &driver_attr_group);
  4191. if (rc)
  4192. goto driver_err;
  4193. qeth_core_root_dev = root_device_register("qeth");
  4194. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4195. if (rc)
  4196. goto register_err;
  4197. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4198. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4199. if (!qeth_core_header_cache) {
  4200. rc = -ENOMEM;
  4201. goto slab_err;
  4202. }
  4203. return 0;
  4204. slab_err:
  4205. root_device_unregister(qeth_core_root_dev);
  4206. register_err:
  4207. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4208. &driver_attr_group);
  4209. driver_err:
  4210. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4211. ccwgroup_err:
  4212. ccw_driver_unregister(&qeth_ccw_driver);
  4213. ccw_err:
  4214. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4215. qeth_unregister_dbf_views();
  4216. out_err:
  4217. pr_err("Initializing the qeth device driver failed\n");
  4218. return rc;
  4219. }
  4220. static void __exit qeth_core_exit(void)
  4221. {
  4222. root_device_unregister(qeth_core_root_dev);
  4223. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4224. &driver_attr_group);
  4225. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4226. ccw_driver_unregister(&qeth_ccw_driver);
  4227. kmem_cache_destroy(qeth_core_header_cache);
  4228. qeth_unregister_dbf_views();
  4229. pr_info("core functions removed\n");
  4230. }
  4231. module_init(qeth_core_init);
  4232. module_exit(qeth_core_exit);
  4233. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4234. MODULE_DESCRIPTION("qeth core functions");
  4235. MODULE_LICENSE("GPL");