twl4030.c 23 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x93, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x24, /* REG_ANAMICL (0x5) */
  47. 0x04, /* REG_ANAMICR (0x6) */
  48. 0x0a, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. return cache[reg];
  124. }
  125. /*
  126. * write twl4030 register cache
  127. */
  128. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  129. u8 reg, u8 value)
  130. {
  131. u8 *cache = codec->reg_cache;
  132. if (reg >= TWL4030_CACHEREGNUM)
  133. return;
  134. cache[reg] = value;
  135. }
  136. /*
  137. * write to the twl4030 register space
  138. */
  139. static int twl4030_write(struct snd_soc_codec *codec,
  140. unsigned int reg, unsigned int value)
  141. {
  142. twl4030_write_reg_cache(codec, reg, value);
  143. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  144. }
  145. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  146. {
  147. u8 mode;
  148. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  149. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  150. mode & ~TWL4030_CODECPDZ);
  151. /* REVISIT: this delay is present in TI sample drivers */
  152. /* but there seems to be no TRM requirement for it */
  153. udelay(10);
  154. }
  155. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  156. {
  157. u8 mode;
  158. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  159. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  160. mode | TWL4030_CODECPDZ);
  161. /* REVISIT: this delay is present in TI sample drivers */
  162. /* but there seems to be no TRM requirement for it */
  163. udelay(10);
  164. }
  165. static void twl4030_init_chip(struct snd_soc_codec *codec)
  166. {
  167. int i;
  168. /* clear CODECPDZ prior to setting register defaults */
  169. twl4030_clear_codecpdz(codec);
  170. /* set all audio section registers to reasonable defaults */
  171. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  172. twl4030_write(codec, i, twl4030_reg[i]);
  173. }
  174. /*
  175. * Some of the gain controls in TWL (mostly those which are associated with
  176. * the outputs) are implemented in an interesting way:
  177. * 0x0 : Power down (mute)
  178. * 0x1 : 6dB
  179. * 0x2 : 0 dB
  180. * 0x3 : -6 dB
  181. * Inverting not going to help with these.
  182. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  183. */
  184. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  185. xinvert, tlv_array) \
  186. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  187. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  188. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  189. .tlv.p = (tlv_array), \
  190. .info = snd_soc_info_volsw, \
  191. .get = snd_soc_get_volsw_twl4030, \
  192. .put = snd_soc_put_volsw_twl4030, \
  193. .private_value = (unsigned long)&(struct soc_mixer_control) \
  194. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  195. .max = xmax, .invert = xinvert} }
  196. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  197. xinvert, tlv_array) \
  198. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  199. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  200. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  201. .tlv.p = (tlv_array), \
  202. .info = snd_soc_info_volsw_2r, \
  203. .get = snd_soc_get_volsw_r2_twl4030,\
  204. .put = snd_soc_put_volsw_r2_twl4030, \
  205. .private_value = (unsigned long)&(struct soc_mixer_control) \
  206. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  207. .max = xmax, .invert = xinvert} }
  208. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  209. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  210. xinvert, tlv_array)
  211. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  212. struct snd_ctl_elem_value *ucontrol)
  213. {
  214. struct soc_mixer_control *mc =
  215. (struct soc_mixer_control *)kcontrol->private_value;
  216. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  217. unsigned int reg = mc->reg;
  218. unsigned int shift = mc->shift;
  219. unsigned int rshift = mc->rshift;
  220. int max = mc->max;
  221. int mask = (1 << fls(max)) - 1;
  222. ucontrol->value.integer.value[0] =
  223. (snd_soc_read(codec, reg) >> shift) & mask;
  224. if (ucontrol->value.integer.value[0])
  225. ucontrol->value.integer.value[0] =
  226. max + 1 - ucontrol->value.integer.value[0];
  227. if (shift != rshift) {
  228. ucontrol->value.integer.value[1] =
  229. (snd_soc_read(codec, reg) >> rshift) & mask;
  230. if (ucontrol->value.integer.value[1])
  231. ucontrol->value.integer.value[1] =
  232. max + 1 - ucontrol->value.integer.value[1];
  233. }
  234. return 0;
  235. }
  236. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  237. struct snd_ctl_elem_value *ucontrol)
  238. {
  239. struct soc_mixer_control *mc =
  240. (struct soc_mixer_control *)kcontrol->private_value;
  241. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  242. unsigned int reg = mc->reg;
  243. unsigned int shift = mc->shift;
  244. unsigned int rshift = mc->rshift;
  245. int max = mc->max;
  246. int mask = (1 << fls(max)) - 1;
  247. unsigned short val, val2, val_mask;
  248. val = (ucontrol->value.integer.value[0] & mask);
  249. val_mask = mask << shift;
  250. if (val)
  251. val = max + 1 - val;
  252. val = val << shift;
  253. if (shift != rshift) {
  254. val2 = (ucontrol->value.integer.value[1] & mask);
  255. val_mask |= mask << rshift;
  256. if (val2)
  257. val2 = max + 1 - val2;
  258. val |= val2 << rshift;
  259. }
  260. return snd_soc_update_bits(codec, reg, val_mask, val);
  261. }
  262. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  263. struct snd_ctl_elem_value *ucontrol)
  264. {
  265. struct soc_mixer_control *mc =
  266. (struct soc_mixer_control *)kcontrol->private_value;
  267. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  268. unsigned int reg = mc->reg;
  269. unsigned int reg2 = mc->rreg;
  270. unsigned int shift = mc->shift;
  271. int max = mc->max;
  272. int mask = (1<<fls(max))-1;
  273. ucontrol->value.integer.value[0] =
  274. (snd_soc_read(codec, reg) >> shift) & mask;
  275. ucontrol->value.integer.value[1] =
  276. (snd_soc_read(codec, reg2) >> shift) & mask;
  277. if (ucontrol->value.integer.value[0])
  278. ucontrol->value.integer.value[0] =
  279. max + 1 - ucontrol->value.integer.value[0];
  280. if (ucontrol->value.integer.value[1])
  281. ucontrol->value.integer.value[1] =
  282. max + 1 - ucontrol->value.integer.value[1];
  283. return 0;
  284. }
  285. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  286. struct snd_ctl_elem_value *ucontrol)
  287. {
  288. struct soc_mixer_control *mc =
  289. (struct soc_mixer_control *)kcontrol->private_value;
  290. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  291. unsigned int reg = mc->reg;
  292. unsigned int reg2 = mc->rreg;
  293. unsigned int shift = mc->shift;
  294. int max = mc->max;
  295. int mask = (1 << fls(max)) - 1;
  296. int err;
  297. unsigned short val, val2, val_mask;
  298. val_mask = mask << shift;
  299. val = (ucontrol->value.integer.value[0] & mask);
  300. val2 = (ucontrol->value.integer.value[1] & mask);
  301. if (val)
  302. val = max + 1 - val;
  303. if (val2)
  304. val2 = max + 1 - val2;
  305. val = val << shift;
  306. val2 = val2 << shift;
  307. err = snd_soc_update_bits(codec, reg, val_mask, val);
  308. if (err < 0)
  309. return err;
  310. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  311. return err;
  312. }
  313. /*
  314. * FGAIN volume control:
  315. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  316. */
  317. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  318. /*
  319. * CGAIN volume control:
  320. * 0 dB to 12 dB in 6 dB steps
  321. * value 2 and 3 means 12 dB
  322. */
  323. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  324. /*
  325. * Analog playback gain
  326. * -24 dB to 12 dB in 2 dB steps
  327. */
  328. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  329. /*
  330. * Capture gain after the ADCs
  331. * from 0 dB to 31 dB in 1 dB steps
  332. */
  333. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  334. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  335. /* Common playback gain controls */
  336. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  337. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  338. 0, 0x3f, 0, digital_fine_tlv),
  339. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  340. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  341. 0, 0x3f, 0, digital_fine_tlv),
  342. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  343. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  344. 6, 0x2, 0, digital_coarse_tlv),
  345. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  346. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  347. 6, 0x2, 0, digital_coarse_tlv),
  348. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  349. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  350. 3, 0x12, 1, analog_tlv),
  351. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  352. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  353. 3, 0x12, 1, analog_tlv),
  354. /* Common capture gain controls */
  355. SOC_DOUBLE_R_TLV("Capture Volume",
  356. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  357. 0, 0x1f, 0, digital_capture_tlv),
  358. };
  359. /* add non dapm controls */
  360. static int twl4030_add_controls(struct snd_soc_codec *codec)
  361. {
  362. int err, i;
  363. for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
  364. err = snd_ctl_add(codec->card,
  365. snd_soc_cnew(&twl4030_snd_controls[i],
  366. codec, NULL));
  367. if (err < 0)
  368. return err;
  369. }
  370. return 0;
  371. }
  372. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  373. SND_SOC_DAPM_INPUT("INL"),
  374. SND_SOC_DAPM_INPUT("INR"),
  375. SND_SOC_DAPM_OUTPUT("OUTL"),
  376. SND_SOC_DAPM_OUTPUT("OUTR"),
  377. SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
  378. SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
  379. SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
  380. SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
  381. };
  382. static const struct snd_soc_dapm_route intercon[] = {
  383. /* outputs */
  384. {"OUTL", NULL, "DACL"},
  385. {"OUTR", NULL, "DACR"},
  386. /* inputs */
  387. {"ADCL", NULL, "INL"},
  388. {"ADCR", NULL, "INR"},
  389. };
  390. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  391. {
  392. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  393. ARRAY_SIZE(twl4030_dapm_widgets));
  394. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  395. snd_soc_dapm_new_widgets(codec);
  396. return 0;
  397. }
  398. static void twl4030_power_up(struct snd_soc_codec *codec)
  399. {
  400. u8 anamicl, regmisc1, byte, popn, hsgain;
  401. int i = 0;
  402. /* set CODECPDZ to turn on codec */
  403. twl4030_set_codecpdz(codec);
  404. /* initiate offset cancellation */
  405. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  406. twl4030_write(codec, TWL4030_REG_ANAMICL,
  407. anamicl | TWL4030_CNCL_OFFSET_START);
  408. /* wait for offset cancellation to complete */
  409. do {
  410. /* this takes a little while, so don't slam i2c */
  411. udelay(2000);
  412. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  413. TWL4030_REG_ANAMICL);
  414. } while ((i++ < 100) &&
  415. ((byte & TWL4030_CNCL_OFFSET_START) ==
  416. TWL4030_CNCL_OFFSET_START));
  417. /* anti-pop when changing analog gain */
  418. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  419. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  420. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  421. /* toggle CODECPDZ as per TRM */
  422. twl4030_clear_codecpdz(codec);
  423. twl4030_set_codecpdz(codec);
  424. /* program anti-pop with bias ramp delay */
  425. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  426. popn &= TWL4030_RAMP_DELAY;
  427. popn |= TWL4030_RAMP_DELAY_645MS;
  428. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  429. popn |= TWL4030_VMID_EN;
  430. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  431. /* enable output stage and gain setting */
  432. hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
  433. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  434. /* enable anti-pop ramp */
  435. popn |= TWL4030_RAMP_EN;
  436. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  437. }
  438. static void twl4030_power_down(struct snd_soc_codec *codec)
  439. {
  440. u8 popn, hsgain;
  441. /* disable anti-pop ramp */
  442. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  443. popn &= ~TWL4030_RAMP_EN;
  444. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  445. /* disable output stage and gain setting */
  446. hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
  447. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  448. /* disable bias out */
  449. popn &= ~TWL4030_VMID_EN;
  450. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  451. /* power down */
  452. twl4030_clear_codecpdz(codec);
  453. }
  454. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  455. enum snd_soc_bias_level level)
  456. {
  457. switch (level) {
  458. case SND_SOC_BIAS_ON:
  459. twl4030_power_up(codec);
  460. break;
  461. case SND_SOC_BIAS_PREPARE:
  462. /* TODO: develop a twl4030_prepare function */
  463. break;
  464. case SND_SOC_BIAS_STANDBY:
  465. /* TODO: develop a twl4030_standby function */
  466. twl4030_power_down(codec);
  467. break;
  468. case SND_SOC_BIAS_OFF:
  469. twl4030_power_down(codec);
  470. break;
  471. }
  472. codec->bias_level = level;
  473. return 0;
  474. }
  475. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  476. struct snd_pcm_hw_params *params,
  477. struct snd_soc_dai *dai)
  478. {
  479. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  480. struct snd_soc_device *socdev = rtd->socdev;
  481. struct snd_soc_codec *codec = socdev->codec;
  482. u8 mode, old_mode, format, old_format;
  483. /* bit rate */
  484. old_mode = twl4030_read_reg_cache(codec,
  485. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  486. mode = old_mode & ~TWL4030_APLL_RATE;
  487. switch (params_rate(params)) {
  488. case 8000:
  489. mode |= TWL4030_APLL_RATE_8000;
  490. break;
  491. case 11025:
  492. mode |= TWL4030_APLL_RATE_11025;
  493. break;
  494. case 12000:
  495. mode |= TWL4030_APLL_RATE_12000;
  496. break;
  497. case 16000:
  498. mode |= TWL4030_APLL_RATE_16000;
  499. break;
  500. case 22050:
  501. mode |= TWL4030_APLL_RATE_22050;
  502. break;
  503. case 24000:
  504. mode |= TWL4030_APLL_RATE_24000;
  505. break;
  506. case 32000:
  507. mode |= TWL4030_APLL_RATE_32000;
  508. break;
  509. case 44100:
  510. mode |= TWL4030_APLL_RATE_44100;
  511. break;
  512. case 48000:
  513. mode |= TWL4030_APLL_RATE_48000;
  514. break;
  515. default:
  516. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  517. params_rate(params));
  518. return -EINVAL;
  519. }
  520. if (mode != old_mode) {
  521. /* change rate and set CODECPDZ */
  522. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  523. twl4030_set_codecpdz(codec);
  524. }
  525. /* sample size */
  526. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  527. format = old_format;
  528. format &= ~TWL4030_DATA_WIDTH;
  529. switch (params_format(params)) {
  530. case SNDRV_PCM_FORMAT_S16_LE:
  531. format |= TWL4030_DATA_WIDTH_16S_16W;
  532. break;
  533. case SNDRV_PCM_FORMAT_S24_LE:
  534. format |= TWL4030_DATA_WIDTH_32S_24W;
  535. break;
  536. default:
  537. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  538. params_format(params));
  539. return -EINVAL;
  540. }
  541. if (format != old_format) {
  542. /* clear CODECPDZ before changing format (codec requirement) */
  543. twl4030_clear_codecpdz(codec);
  544. /* change format */
  545. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  546. /* set CODECPDZ afterwards */
  547. twl4030_set_codecpdz(codec);
  548. }
  549. return 0;
  550. }
  551. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  552. int clk_id, unsigned int freq, int dir)
  553. {
  554. struct snd_soc_codec *codec = codec_dai->codec;
  555. u8 infreq;
  556. switch (freq) {
  557. case 19200000:
  558. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  559. break;
  560. case 26000000:
  561. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  562. break;
  563. case 38400000:
  564. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  565. break;
  566. default:
  567. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  568. freq);
  569. return -EINVAL;
  570. }
  571. infreq |= TWL4030_APLL_EN;
  572. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  573. return 0;
  574. }
  575. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  576. unsigned int fmt)
  577. {
  578. struct snd_soc_codec *codec = codec_dai->codec;
  579. u8 old_format, format;
  580. /* get format */
  581. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  582. format = old_format;
  583. /* set master/slave audio interface */
  584. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  585. case SND_SOC_DAIFMT_CBM_CFM:
  586. format &= ~(TWL4030_AIF_SLAVE_EN);
  587. format &= ~(TWL4030_CLK256FS_EN);
  588. break;
  589. case SND_SOC_DAIFMT_CBS_CFS:
  590. format |= TWL4030_AIF_SLAVE_EN;
  591. format |= TWL4030_CLK256FS_EN;
  592. break;
  593. default:
  594. return -EINVAL;
  595. }
  596. /* interface format */
  597. format &= ~TWL4030_AIF_FORMAT;
  598. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  599. case SND_SOC_DAIFMT_I2S:
  600. format |= TWL4030_AIF_FORMAT_CODEC;
  601. break;
  602. default:
  603. return -EINVAL;
  604. }
  605. if (format != old_format) {
  606. /* clear CODECPDZ before changing format (codec requirement) */
  607. twl4030_clear_codecpdz(codec);
  608. /* change format */
  609. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  610. /* set CODECPDZ afterwards */
  611. twl4030_set_codecpdz(codec);
  612. }
  613. return 0;
  614. }
  615. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  616. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  617. struct snd_soc_dai twl4030_dai = {
  618. .name = "twl4030",
  619. .playback = {
  620. .stream_name = "Playback",
  621. .channels_min = 2,
  622. .channels_max = 2,
  623. .rates = TWL4030_RATES,
  624. .formats = TWL4030_FORMATS,},
  625. .capture = {
  626. .stream_name = "Capture",
  627. .channels_min = 2,
  628. .channels_max = 2,
  629. .rates = TWL4030_RATES,
  630. .formats = TWL4030_FORMATS,},
  631. .ops = {
  632. .hw_params = twl4030_hw_params,
  633. .set_sysclk = twl4030_set_dai_sysclk,
  634. .set_fmt = twl4030_set_dai_fmt,
  635. }
  636. };
  637. EXPORT_SYMBOL_GPL(twl4030_dai);
  638. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  639. {
  640. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  641. struct snd_soc_codec *codec = socdev->codec;
  642. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  643. return 0;
  644. }
  645. static int twl4030_resume(struct platform_device *pdev)
  646. {
  647. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  648. struct snd_soc_codec *codec = socdev->codec;
  649. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  650. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  651. return 0;
  652. }
  653. /*
  654. * initialize the driver
  655. * register the mixer and dsp interfaces with the kernel
  656. */
  657. static int twl4030_init(struct snd_soc_device *socdev)
  658. {
  659. struct snd_soc_codec *codec = socdev->codec;
  660. int ret = 0;
  661. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  662. codec->name = "twl4030";
  663. codec->owner = THIS_MODULE;
  664. codec->read = twl4030_read_reg_cache;
  665. codec->write = twl4030_write;
  666. codec->set_bias_level = twl4030_set_bias_level;
  667. codec->dai = &twl4030_dai;
  668. codec->num_dai = 1;
  669. codec->reg_cache_size = sizeof(twl4030_reg);
  670. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  671. GFP_KERNEL);
  672. if (codec->reg_cache == NULL)
  673. return -ENOMEM;
  674. /* register pcms */
  675. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  676. if (ret < 0) {
  677. printk(KERN_ERR "twl4030: failed to create pcms\n");
  678. goto pcm_err;
  679. }
  680. twl4030_init_chip(codec);
  681. /* power on device */
  682. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  683. twl4030_add_controls(codec);
  684. twl4030_add_widgets(codec);
  685. ret = snd_soc_init_card(socdev);
  686. if (ret < 0) {
  687. printk(KERN_ERR "twl4030: failed to register card\n");
  688. goto card_err;
  689. }
  690. return ret;
  691. card_err:
  692. snd_soc_free_pcms(socdev);
  693. snd_soc_dapm_free(socdev);
  694. pcm_err:
  695. kfree(codec->reg_cache);
  696. return ret;
  697. }
  698. static struct snd_soc_device *twl4030_socdev;
  699. static int twl4030_probe(struct platform_device *pdev)
  700. {
  701. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  702. struct snd_soc_codec *codec;
  703. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  704. if (codec == NULL)
  705. return -ENOMEM;
  706. socdev->codec = codec;
  707. mutex_init(&codec->mutex);
  708. INIT_LIST_HEAD(&codec->dapm_widgets);
  709. INIT_LIST_HEAD(&codec->dapm_paths);
  710. twl4030_socdev = socdev;
  711. twl4030_init(socdev);
  712. return 0;
  713. }
  714. static int twl4030_remove(struct platform_device *pdev)
  715. {
  716. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  717. struct snd_soc_codec *codec = socdev->codec;
  718. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  719. kfree(codec);
  720. return 0;
  721. }
  722. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  723. .probe = twl4030_probe,
  724. .remove = twl4030_remove,
  725. .suspend = twl4030_suspend,
  726. .resume = twl4030_resume,
  727. };
  728. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  729. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  730. MODULE_AUTHOR("Steve Sakoman");
  731. MODULE_LICENSE("GPL");