Kconfig 29 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config SYMBOL_PREFIX
  7. string
  8. default "_"
  9. config MMU
  10. def_bool n
  11. config FPU
  12. def_bool n
  13. config RWSEM_GENERIC_SPINLOCK
  14. def_bool y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. def_bool n
  17. config BLACKFIN
  18. def_bool y
  19. select HAVE_FUNCTION_GRAPH_TRACER
  20. select HAVE_FUNCTION_TRACER
  21. select HAVE_IDE
  22. select HAVE_KERNEL_GZIP if RAMKERNEL
  23. select HAVE_KERNEL_BZIP2 if RAMKERNEL
  24. select HAVE_KERNEL_LZMA if RAMKERNEL
  25. select HAVE_OPROFILE
  26. select ARCH_WANT_OPTIONAL_GPIOLIB
  27. config GENERIC_CSUM
  28. def_bool y
  29. config GENERIC_BUG
  30. def_bool y
  31. depends on BUG
  32. config ZONE_DMA
  33. def_bool y
  34. config GENERIC_FIND_NEXT_BIT
  35. def_bool y
  36. config GENERIC_HARDIRQS
  37. def_bool y
  38. config GENERIC_IRQ_PROBE
  39. def_bool y
  40. config GENERIC_HARDIRQS_NO__DO_IRQ
  41. def_bool y
  42. config GENERIC_GPIO
  43. def_bool y
  44. config FORCE_MAX_ZONEORDER
  45. int
  46. default "14"
  47. config GENERIC_CALIBRATE_DELAY
  48. def_bool y
  49. config LOCKDEP_SUPPORT
  50. def_bool y
  51. config STACKTRACE_SUPPORT
  52. def_bool y
  53. config TRACE_IRQFLAGS_SUPPORT
  54. def_bool y
  55. source "init/Kconfig"
  56. source "kernel/Kconfig.preempt"
  57. source "kernel/Kconfig.freezer"
  58. menu "Blackfin Processor Options"
  59. comment "Processor and Board Settings"
  60. choice
  61. prompt "CPU"
  62. default BF533
  63. config BF512
  64. bool "BF512"
  65. help
  66. BF512 Processor Support.
  67. config BF514
  68. bool "BF514"
  69. help
  70. BF514 Processor Support.
  71. config BF516
  72. bool "BF516"
  73. help
  74. BF516 Processor Support.
  75. config BF518
  76. bool "BF518"
  77. help
  78. BF518 Processor Support.
  79. config BF522
  80. bool "BF522"
  81. help
  82. BF522 Processor Support.
  83. config BF523
  84. bool "BF523"
  85. help
  86. BF523 Processor Support.
  87. config BF524
  88. bool "BF524"
  89. help
  90. BF524 Processor Support.
  91. config BF525
  92. bool "BF525"
  93. help
  94. BF525 Processor Support.
  95. config BF526
  96. bool "BF526"
  97. help
  98. BF526 Processor Support.
  99. config BF527
  100. bool "BF527"
  101. help
  102. BF527 Processor Support.
  103. config BF531
  104. bool "BF531"
  105. help
  106. BF531 Processor Support.
  107. config BF532
  108. bool "BF532"
  109. help
  110. BF532 Processor Support.
  111. config BF533
  112. bool "BF533"
  113. help
  114. BF533 Processor Support.
  115. config BF534
  116. bool "BF534"
  117. help
  118. BF534 Processor Support.
  119. config BF536
  120. bool "BF536"
  121. help
  122. BF536 Processor Support.
  123. config BF537
  124. bool "BF537"
  125. help
  126. BF537 Processor Support.
  127. config BF538
  128. bool "BF538"
  129. help
  130. BF538 Processor Support.
  131. config BF539
  132. bool "BF539"
  133. help
  134. BF539 Processor Support.
  135. config BF542_std
  136. bool "BF542"
  137. help
  138. BF542 Processor Support.
  139. config BF542M
  140. bool "BF542m"
  141. help
  142. BF542 Processor Support.
  143. config BF544_std
  144. bool "BF544"
  145. help
  146. BF544 Processor Support.
  147. config BF544M
  148. bool "BF544m"
  149. help
  150. BF544 Processor Support.
  151. config BF547_std
  152. bool "BF547"
  153. help
  154. BF547 Processor Support.
  155. config BF547M
  156. bool "BF547m"
  157. help
  158. BF547 Processor Support.
  159. config BF548_std
  160. bool "BF548"
  161. help
  162. BF548 Processor Support.
  163. config BF548M
  164. bool "BF548m"
  165. help
  166. BF548 Processor Support.
  167. config BF549_std
  168. bool "BF549"
  169. help
  170. BF549 Processor Support.
  171. config BF549M
  172. bool "BF549m"
  173. help
  174. BF549 Processor Support.
  175. config BF561
  176. bool "BF561"
  177. help
  178. BF561 Processor Support.
  179. endchoice
  180. config SMP
  181. depends on BF561
  182. select TICKSOURCE_CORETMR
  183. bool "Symmetric multi-processing support"
  184. ---help---
  185. This enables support for systems with more than one CPU,
  186. like the dual core BF561. If you have a system with only one
  187. CPU, say N. If you have a system with more than one CPU, say Y.
  188. If you don't know what to do here, say N.
  189. config NR_CPUS
  190. int
  191. depends on SMP
  192. default 2 if BF561
  193. config HOTPLUG_CPU
  194. bool "Support for hot-pluggable CPUs"
  195. depends on SMP && HOTPLUG
  196. default y
  197. config IRQ_PER_CPU
  198. bool
  199. depends on SMP
  200. default y
  201. config HAVE_LEGACY_PER_CPU_AREA
  202. def_bool y
  203. depends on SMP
  204. config BF_REV_MIN
  205. int
  206. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  207. default 2 if (BF537 || BF536 || BF534)
  208. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  209. default 4 if (BF538 || BF539)
  210. config BF_REV_MAX
  211. int
  212. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  213. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  214. default 5 if (BF561 || BF538 || BF539)
  215. default 6 if (BF533 || BF532 || BF531)
  216. choice
  217. prompt "Silicon Rev"
  218. default BF_REV_0_0 if (BF51x || BF52x)
  219. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  220. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  221. config BF_REV_0_0
  222. bool "0.0"
  223. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  224. config BF_REV_0_1
  225. bool "0.1"
  226. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  227. config BF_REV_0_2
  228. bool "0.2"
  229. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  230. config BF_REV_0_3
  231. bool "0.3"
  232. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  233. config BF_REV_0_4
  234. bool "0.4"
  235. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  236. config BF_REV_0_5
  237. bool "0.5"
  238. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  239. config BF_REV_0_6
  240. bool "0.6"
  241. depends on (BF533 || BF532 || BF531)
  242. config BF_REV_ANY
  243. bool "any"
  244. config BF_REV_NONE
  245. bool "none"
  246. endchoice
  247. config BF53x
  248. bool
  249. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  250. default y
  251. config MEM_GENERIC_BOARD
  252. bool
  253. depends on GENERIC_BOARD
  254. default y
  255. config MEM_MT48LC64M4A2FB_7E
  256. bool
  257. depends on (BFIN533_STAMP)
  258. default y
  259. config MEM_MT48LC16M16A2TG_75
  260. bool
  261. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  262. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  263. || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  264. || BFIN527_BLUETECHNIX_CM)
  265. default y
  266. config MEM_MT48LC32M8A2_75
  267. bool
  268. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  269. default y
  270. config MEM_MT48LC8M32B2B5_7
  271. bool
  272. depends on (BFIN561_BLUETECHNIX_CM)
  273. default y
  274. config MEM_MT48LC32M16A2TG_75
  275. bool
  276. depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
  277. default y
  278. config MEM_MT48LC32M8A2_75
  279. bool
  280. depends on (BFIN518F_EZBRD)
  281. default y
  282. config MEM_MT48H32M16LFCJ_75
  283. bool
  284. depends on (BFIN526_EZBRD)
  285. default y
  286. source "arch/blackfin/mach-bf518/Kconfig"
  287. source "arch/blackfin/mach-bf527/Kconfig"
  288. source "arch/blackfin/mach-bf533/Kconfig"
  289. source "arch/blackfin/mach-bf561/Kconfig"
  290. source "arch/blackfin/mach-bf537/Kconfig"
  291. source "arch/blackfin/mach-bf538/Kconfig"
  292. source "arch/blackfin/mach-bf548/Kconfig"
  293. menu "Board customizations"
  294. config CMDLINE_BOOL
  295. bool "Default bootloader kernel arguments"
  296. config CMDLINE
  297. string "Initial kernel command string"
  298. depends on CMDLINE_BOOL
  299. default "console=ttyBF0,57600"
  300. help
  301. If you don't have a boot loader capable of passing a command line string
  302. to the kernel, you may specify one here. As a minimum, you should specify
  303. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  304. config BOOT_LOAD
  305. hex "Kernel load address for booting"
  306. default "0x1000"
  307. range 0x1000 0x20000000
  308. help
  309. This option allows you to set the load address of the kernel.
  310. This can be useful if you are on a board which has a small amount
  311. of memory or you wish to reserve some memory at the beginning of
  312. the address space.
  313. Note that you need to keep this value above 4k (0x1000) as this
  314. memory region is used to capture NULL pointer references as well
  315. as some core kernel functions.
  316. config ROM_BASE
  317. hex "Kernel ROM Base"
  318. depends on ROMKERNEL
  319. default "0x20040040"
  320. range 0x20000000 0x20400000 if !(BF54x || BF561)
  321. range 0x20000000 0x30000000 if (BF54x || BF561)
  322. help
  323. Make sure your ROM base does not include any file-header
  324. information that is prepended to the kernel.
  325. For example, the bootable U-Boot format (created with
  326. mkimage) has a 64 byte header (0x40). So while the image
  327. you write to flash might start at say 0x20080000, you have
  328. to add 0x40 to get the kernel's ROM base as it will come
  329. after the header.
  330. comment "Clock/PLL Setup"
  331. config CLKIN_HZ
  332. int "Frequency of the crystal on the board in Hz"
  333. default "10000000" if BFIN532_IP0X
  334. default "11059200" if BFIN533_STAMP
  335. default "24576000" if PNAV10
  336. default "25000000" # most people use this
  337. default "27000000" if BFIN533_EZKIT
  338. default "30000000" if BFIN561_EZKIT
  339. help
  340. The frequency of CLKIN crystal oscillator on the board in Hz.
  341. Warning: This value should match the crystal on the board. Otherwise,
  342. peripherals won't work properly.
  343. config BFIN_KERNEL_CLOCK
  344. bool "Re-program Clocks while Kernel boots?"
  345. default n
  346. help
  347. This option decides if kernel clocks are re-programed from the
  348. bootloader settings. If the clocks are not set, the SDRAM settings
  349. are also not changed, and the Bootloader does 100% of the hardware
  350. configuration.
  351. config PLL_BYPASS
  352. bool "Bypass PLL"
  353. depends on BFIN_KERNEL_CLOCK
  354. default n
  355. config CLKIN_HALF
  356. bool "Half Clock In"
  357. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  358. default n
  359. help
  360. If this is set the clock will be divided by 2, before it goes to the PLL.
  361. config VCO_MULT
  362. int "VCO Multiplier"
  363. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  364. range 1 64
  365. default "22" if BFIN533_EZKIT
  366. default "45" if BFIN533_STAMP
  367. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  368. default "22" if BFIN533_BLUETECHNIX_CM
  369. default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  370. default "20" if BFIN561_EZKIT
  371. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  372. help
  373. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  374. PLL Frequency = (Crystal Frequency) * (this setting)
  375. choice
  376. prompt "Core Clock Divider"
  377. depends on BFIN_KERNEL_CLOCK
  378. default CCLK_DIV_1
  379. help
  380. This sets the frequency of the core. It can be 1, 2, 4 or 8
  381. Core Frequency = (PLL frequency) / (this setting)
  382. config CCLK_DIV_1
  383. bool "1"
  384. config CCLK_DIV_2
  385. bool "2"
  386. config CCLK_DIV_4
  387. bool "4"
  388. config CCLK_DIV_8
  389. bool "8"
  390. endchoice
  391. config SCLK_DIV
  392. int "System Clock Divider"
  393. depends on BFIN_KERNEL_CLOCK
  394. range 1 15
  395. default 5
  396. help
  397. This sets the frequency of the system clock (including SDRAM or DDR).
  398. This can be between 1 and 15
  399. System Clock = (PLL frequency) / (this setting)
  400. choice
  401. prompt "DDR SDRAM Chip Type"
  402. depends on BFIN_KERNEL_CLOCK
  403. depends on BF54x
  404. default MEM_MT46V32M16_5B
  405. config MEM_MT46V32M16_6T
  406. bool "MT46V32M16_6T"
  407. config MEM_MT46V32M16_5B
  408. bool "MT46V32M16_5B"
  409. endchoice
  410. choice
  411. prompt "DDR/SDRAM Timing"
  412. depends on BFIN_KERNEL_CLOCK
  413. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  414. help
  415. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  416. The calculated SDRAM timing parameters may not be 100%
  417. accurate - This option is therefore marked experimental.
  418. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  419. bool "Calculate Timings (EXPERIMENTAL)"
  420. depends on EXPERIMENTAL
  421. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  422. bool "Provide accurate Timings based on target SCLK"
  423. help
  424. Please consult the Blackfin Hardware Reference Manuals as well
  425. as the memory device datasheet.
  426. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  427. endchoice
  428. menu "Memory Init Control"
  429. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  430. config MEM_DDRCTL0
  431. depends on BF54x
  432. hex "DDRCTL0"
  433. default 0x0
  434. config MEM_DDRCTL1
  435. depends on BF54x
  436. hex "DDRCTL1"
  437. default 0x0
  438. config MEM_DDRCTL2
  439. depends on BF54x
  440. hex "DDRCTL2"
  441. default 0x0
  442. config MEM_EBIU_DDRQUE
  443. depends on BF54x
  444. hex "DDRQUE"
  445. default 0x0
  446. config MEM_SDRRC
  447. depends on !BF54x
  448. hex "SDRRC"
  449. default 0x0
  450. config MEM_SDGCTL
  451. depends on !BF54x
  452. hex "SDGCTL"
  453. default 0x0
  454. endmenu
  455. #
  456. # Max & Min Speeds for various Chips
  457. #
  458. config MAX_VCO_HZ
  459. int
  460. default 400000000 if BF512
  461. default 400000000 if BF514
  462. default 400000000 if BF516
  463. default 400000000 if BF518
  464. default 400000000 if BF522
  465. default 600000000 if BF523
  466. default 400000000 if BF524
  467. default 600000000 if BF525
  468. default 400000000 if BF526
  469. default 600000000 if BF527
  470. default 400000000 if BF531
  471. default 400000000 if BF532
  472. default 750000000 if BF533
  473. default 500000000 if BF534
  474. default 400000000 if BF536
  475. default 600000000 if BF537
  476. default 533333333 if BF538
  477. default 533333333 if BF539
  478. default 600000000 if BF542
  479. default 533333333 if BF544
  480. default 600000000 if BF547
  481. default 600000000 if BF548
  482. default 533333333 if BF549
  483. default 600000000 if BF561
  484. config MIN_VCO_HZ
  485. int
  486. default 50000000
  487. config MAX_SCLK_HZ
  488. int
  489. default 133333333
  490. config MIN_SCLK_HZ
  491. int
  492. default 27000000
  493. comment "Kernel Timer/Scheduler"
  494. source kernel/Kconfig.hz
  495. config GENERIC_TIME
  496. def_bool y
  497. config GENERIC_CLOCKEVENTS
  498. bool "Generic clock events"
  499. default y
  500. menu "Clock event device"
  501. depends on GENERIC_CLOCKEVENTS
  502. config TICKSOURCE_GPTMR0
  503. bool "GPTimer0"
  504. depends on !SMP
  505. select BFIN_GPTIMERS
  506. config TICKSOURCE_CORETMR
  507. bool "Core timer"
  508. default y
  509. endmenu
  510. menu "Clock souce"
  511. depends on GENERIC_CLOCKEVENTS
  512. config CYCLES_CLOCKSOURCE
  513. bool "CYCLES"
  514. default y
  515. depends on !BFIN_SCRATCH_REG_CYCLES
  516. depends on !SMP
  517. help
  518. If you say Y here, you will enable support for using the 'cycles'
  519. registers as a clock source. Doing so means you will be unable to
  520. safely write to the 'cycles' register during runtime. You will
  521. still be able to read it (such as for performance monitoring), but
  522. writing the registers will most likely crash the kernel.
  523. config GPTMR0_CLOCKSOURCE
  524. bool "GPTimer0"
  525. select BFIN_GPTIMERS
  526. depends on !TICKSOURCE_GPTMR0
  527. endmenu
  528. config ARCH_USES_GETTIMEOFFSET
  529. depends on !GENERIC_CLOCKEVENTS
  530. def_bool y
  531. source kernel/time/Kconfig
  532. comment "Misc"
  533. choice
  534. prompt "Blackfin Exception Scratch Register"
  535. default BFIN_SCRATCH_REG_RETN
  536. help
  537. Select the resource to reserve for the Exception handler:
  538. - RETN: Non-Maskable Interrupt (NMI)
  539. - RETE: Exception Return (JTAG/ICE)
  540. - CYCLES: Performance counter
  541. If you are unsure, please select "RETN".
  542. config BFIN_SCRATCH_REG_RETN
  543. bool "RETN"
  544. help
  545. Use the RETN register in the Blackfin exception handler
  546. as a stack scratch register. This means you cannot
  547. safely use NMI on the Blackfin while running Linux, but
  548. you can debug the system with a JTAG ICE and use the
  549. CYCLES performance registers.
  550. If you are unsure, please select "RETN".
  551. config BFIN_SCRATCH_REG_RETE
  552. bool "RETE"
  553. help
  554. Use the RETE register in the Blackfin exception handler
  555. as a stack scratch register. This means you cannot
  556. safely use a JTAG ICE while debugging a Blackfin board,
  557. but you can safely use the CYCLES performance registers
  558. and the NMI.
  559. If you are unsure, please select "RETN".
  560. config BFIN_SCRATCH_REG_CYCLES
  561. bool "CYCLES"
  562. help
  563. Use the CYCLES register in the Blackfin exception handler
  564. as a stack scratch register. This means you cannot
  565. safely use the CYCLES performance registers on a Blackfin
  566. board at anytime, but you can debug the system with a JTAG
  567. ICE and use the NMI.
  568. If you are unsure, please select "RETN".
  569. endchoice
  570. endmenu
  571. menu "Blackfin Kernel Optimizations"
  572. depends on !SMP
  573. comment "Memory Optimizations"
  574. config I_ENTRY_L1
  575. bool "Locate interrupt entry code in L1 Memory"
  576. default y
  577. help
  578. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  579. into L1 instruction memory. (less latency)
  580. config EXCPT_IRQ_SYSC_L1
  581. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  582. default y
  583. help
  584. If enabled, the entire ASM lowlevel exception and interrupt entry code
  585. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  586. (less latency)
  587. config DO_IRQ_L1
  588. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  589. default y
  590. help
  591. If enabled, the frequently called do_irq dispatcher function is linked
  592. into L1 instruction memory. (less latency)
  593. config CORE_TIMER_IRQ_L1
  594. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  595. default y
  596. help
  597. If enabled, the frequently called timer_interrupt() function is linked
  598. into L1 instruction memory. (less latency)
  599. config IDLE_L1
  600. bool "Locate frequently idle function in L1 Memory"
  601. default y
  602. help
  603. If enabled, the frequently called idle function is linked
  604. into L1 instruction memory. (less latency)
  605. config SCHEDULE_L1
  606. bool "Locate kernel schedule function in L1 Memory"
  607. default y
  608. help
  609. If enabled, the frequently called kernel schedule is linked
  610. into L1 instruction memory. (less latency)
  611. config ARITHMETIC_OPS_L1
  612. bool "Locate kernel owned arithmetic functions in L1 Memory"
  613. default y
  614. help
  615. If enabled, arithmetic functions are linked
  616. into L1 instruction memory. (less latency)
  617. config ACCESS_OK_L1
  618. bool "Locate access_ok function in L1 Memory"
  619. default y
  620. help
  621. If enabled, the access_ok function is linked
  622. into L1 instruction memory. (less latency)
  623. config MEMSET_L1
  624. bool "Locate memset function in L1 Memory"
  625. default y
  626. help
  627. If enabled, the memset function is linked
  628. into L1 instruction memory. (less latency)
  629. config MEMCPY_L1
  630. bool "Locate memcpy function in L1 Memory"
  631. default y
  632. help
  633. If enabled, the memcpy function is linked
  634. into L1 instruction memory. (less latency)
  635. config SYS_BFIN_SPINLOCK_L1
  636. bool "Locate sys_bfin_spinlock function in L1 Memory"
  637. default y
  638. help
  639. If enabled, sys_bfin_spinlock function is linked
  640. into L1 instruction memory. (less latency)
  641. config IP_CHECKSUM_L1
  642. bool "Locate IP Checksum function in L1 Memory"
  643. default n
  644. help
  645. If enabled, the IP Checksum function is linked
  646. into L1 instruction memory. (less latency)
  647. config CACHELINE_ALIGNED_L1
  648. bool "Locate cacheline_aligned data to L1 Data Memory"
  649. default y if !BF54x
  650. default n if BF54x
  651. depends on !BF531
  652. help
  653. If enabled, cacheline_aligned data is linked
  654. into L1 data memory. (less latency)
  655. config SYSCALL_TAB_L1
  656. bool "Locate Syscall Table L1 Data Memory"
  657. default n
  658. depends on !BF531
  659. help
  660. If enabled, the Syscall LUT is linked
  661. into L1 data memory. (less latency)
  662. config CPLB_SWITCH_TAB_L1
  663. bool "Locate CPLB Switch Tables L1 Data Memory"
  664. default n
  665. depends on !BF531
  666. help
  667. If enabled, the CPLB Switch Tables are linked
  668. into L1 data memory. (less latency)
  669. config APP_STACK_L1
  670. bool "Support locating application stack in L1 Scratch Memory"
  671. default y
  672. help
  673. If enabled the application stack can be located in L1
  674. scratch memory (less latency).
  675. Currently only works with FLAT binaries.
  676. config EXCEPTION_L1_SCRATCH
  677. bool "Locate exception stack in L1 Scratch Memory"
  678. default n
  679. depends on !APP_STACK_L1
  680. help
  681. Whenever an exception occurs, use the L1 Scratch memory for
  682. stack storage. You cannot place the stacks of FLAT binaries
  683. in L1 when using this option.
  684. If you don't use L1 Scratch, then you should say Y here.
  685. comment "Speed Optimizations"
  686. config BFIN_INS_LOWOVERHEAD
  687. bool "ins[bwl] low overhead, higher interrupt latency"
  688. default y
  689. help
  690. Reads on the Blackfin are speculative. In Blackfin terms, this means
  691. they can be interrupted at any time (even after they have been issued
  692. on to the external bus), and re-issued after the interrupt occurs.
  693. For memory - this is not a big deal, since memory does not change if
  694. it sees a read.
  695. If a FIFO is sitting on the end of the read, it will see two reads,
  696. when the core only sees one since the FIFO receives both the read
  697. which is cancelled (and not delivered to the core) and the one which
  698. is re-issued (which is delivered to the core).
  699. To solve this, interrupts are turned off before reads occur to
  700. I/O space. This option controls which the overhead/latency of
  701. controlling interrupts during this time
  702. "n" turns interrupts off every read
  703. (higher overhead, but lower interrupt latency)
  704. "y" turns interrupts off every loop
  705. (low overhead, but longer interrupt latency)
  706. default behavior is to leave this set to on (type "Y"). If you are experiencing
  707. interrupt latency issues, it is safe and OK to turn this off.
  708. endmenu
  709. choice
  710. prompt "Kernel executes from"
  711. help
  712. Choose the memory type that the kernel will be running in.
  713. config RAMKERNEL
  714. bool "RAM"
  715. help
  716. The kernel will be resident in RAM when running.
  717. config ROMKERNEL
  718. bool "ROM"
  719. help
  720. The kernel will be resident in FLASH/ROM when running.
  721. endchoice
  722. source "mm/Kconfig"
  723. config BFIN_GPTIMERS
  724. tristate "Enable Blackfin General Purpose Timers API"
  725. default n
  726. help
  727. Enable support for the General Purpose Timers API. If you
  728. are unsure, say N.
  729. To compile this driver as a module, choose M here: the module
  730. will be called gptimers.
  731. choice
  732. prompt "Uncached DMA region"
  733. default DMA_UNCACHED_1M
  734. config DMA_UNCACHED_4M
  735. bool "Enable 4M DMA region"
  736. config DMA_UNCACHED_2M
  737. bool "Enable 2M DMA region"
  738. config DMA_UNCACHED_1M
  739. bool "Enable 1M DMA region"
  740. config DMA_UNCACHED_512K
  741. bool "Enable 512K DMA region"
  742. config DMA_UNCACHED_256K
  743. bool "Enable 256K DMA region"
  744. config DMA_UNCACHED_128K
  745. bool "Enable 128K DMA region"
  746. config DMA_UNCACHED_NONE
  747. bool "Disable DMA region"
  748. endchoice
  749. comment "Cache Support"
  750. config BFIN_ICACHE
  751. bool "Enable ICACHE"
  752. default y
  753. config BFIN_EXTMEM_ICACHEABLE
  754. bool "Enable ICACHE for external memory"
  755. depends on BFIN_ICACHE
  756. default y
  757. config BFIN_L2_ICACHEABLE
  758. bool "Enable ICACHE for L2 SRAM"
  759. depends on BFIN_ICACHE
  760. depends on BF54x || BF561
  761. default n
  762. config BFIN_DCACHE
  763. bool "Enable DCACHE"
  764. default y
  765. config BFIN_DCACHE_BANKA
  766. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  767. depends on BFIN_DCACHE && !BF531
  768. default n
  769. config BFIN_EXTMEM_DCACHEABLE
  770. bool "Enable DCACHE for external memory"
  771. depends on BFIN_DCACHE
  772. default y
  773. choice
  774. prompt "External memory DCACHE policy"
  775. depends on BFIN_EXTMEM_DCACHEABLE
  776. default BFIN_EXTMEM_WRITEBACK if !SMP
  777. default BFIN_EXTMEM_WRITETHROUGH if SMP
  778. config BFIN_EXTMEM_WRITEBACK
  779. bool "Write back"
  780. depends on !SMP
  781. help
  782. Write Back Policy:
  783. Cached data will be written back to SDRAM only when needed.
  784. This can give a nice increase in performance, but beware of
  785. broken drivers that do not properly invalidate/flush their
  786. cache.
  787. Write Through Policy:
  788. Cached data will always be written back to SDRAM when the
  789. cache is updated. This is a completely safe setting, but
  790. performance is worse than Write Back.
  791. If you are unsure of the options and you want to be safe,
  792. then go with Write Through.
  793. config BFIN_EXTMEM_WRITETHROUGH
  794. bool "Write through"
  795. help
  796. Write Back Policy:
  797. Cached data will be written back to SDRAM only when needed.
  798. This can give a nice increase in performance, but beware of
  799. broken drivers that do not properly invalidate/flush their
  800. cache.
  801. Write Through Policy:
  802. Cached data will always be written back to SDRAM when the
  803. cache is updated. This is a completely safe setting, but
  804. performance is worse than Write Back.
  805. If you are unsure of the options and you want to be safe,
  806. then go with Write Through.
  807. endchoice
  808. config BFIN_L2_DCACHEABLE
  809. bool "Enable DCACHE for L2 SRAM"
  810. depends on BFIN_DCACHE
  811. depends on (BF54x || BF561) && !SMP
  812. default n
  813. choice
  814. prompt "L2 SRAM DCACHE policy"
  815. depends on BFIN_L2_DCACHEABLE
  816. default BFIN_L2_WRITEBACK
  817. config BFIN_L2_WRITEBACK
  818. bool "Write back"
  819. config BFIN_L2_WRITETHROUGH
  820. bool "Write through"
  821. endchoice
  822. comment "Memory Protection Unit"
  823. config MPU
  824. bool "Enable the memory protection unit (EXPERIMENTAL)"
  825. default n
  826. help
  827. Use the processor's MPU to protect applications from accessing
  828. memory they do not own. This comes at a performance penalty
  829. and is recommended only for debugging.
  830. comment "Asynchronous Memory Configuration"
  831. menu "EBIU_AMGCTL Global Control"
  832. config C_AMCKEN
  833. bool "Enable CLKOUT"
  834. default y
  835. config C_CDPRIO
  836. bool "DMA has priority over core for ext. accesses"
  837. default n
  838. config C_B0PEN
  839. depends on BF561
  840. bool "Bank 0 16 bit packing enable"
  841. default y
  842. config C_B1PEN
  843. depends on BF561
  844. bool "Bank 1 16 bit packing enable"
  845. default y
  846. config C_B2PEN
  847. depends on BF561
  848. bool "Bank 2 16 bit packing enable"
  849. default y
  850. config C_B3PEN
  851. depends on BF561
  852. bool "Bank 3 16 bit packing enable"
  853. default n
  854. choice
  855. prompt "Enable Asynchronous Memory Banks"
  856. default C_AMBEN_ALL
  857. config C_AMBEN
  858. bool "Disable All Banks"
  859. config C_AMBEN_B0
  860. bool "Enable Bank 0"
  861. config C_AMBEN_B0_B1
  862. bool "Enable Bank 0 & 1"
  863. config C_AMBEN_B0_B1_B2
  864. bool "Enable Bank 0 & 1 & 2"
  865. config C_AMBEN_ALL
  866. bool "Enable All Banks"
  867. endchoice
  868. endmenu
  869. menu "EBIU_AMBCTL Control"
  870. config BANK_0
  871. hex "Bank 0 (AMBCTL0.L)"
  872. default 0x7BB0
  873. help
  874. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  875. used to control the Asynchronous Memory Bank 0 settings.
  876. config BANK_1
  877. hex "Bank 1 (AMBCTL0.H)"
  878. default 0x7BB0
  879. default 0x5558 if BF54x
  880. help
  881. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  882. used to control the Asynchronous Memory Bank 1 settings.
  883. config BANK_2
  884. hex "Bank 2 (AMBCTL1.L)"
  885. default 0x7BB0
  886. help
  887. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  888. used to control the Asynchronous Memory Bank 2 settings.
  889. config BANK_3
  890. hex "Bank 3 (AMBCTL1.H)"
  891. default 0x99B3
  892. help
  893. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  894. used to control the Asynchronous Memory Bank 3 settings.
  895. endmenu
  896. config EBIU_MBSCTLVAL
  897. hex "EBIU Bank Select Control Register"
  898. depends on BF54x
  899. default 0
  900. config EBIU_MODEVAL
  901. hex "Flash Memory Mode Control Register"
  902. depends on BF54x
  903. default 1
  904. config EBIU_FCTLVAL
  905. hex "Flash Memory Bank Control Register"
  906. depends on BF54x
  907. default 6
  908. endmenu
  909. #############################################################################
  910. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  911. config PCI
  912. bool "PCI support"
  913. depends on BROKEN
  914. help
  915. Support for PCI bus.
  916. source "drivers/pci/Kconfig"
  917. source "drivers/pcmcia/Kconfig"
  918. source "drivers/pci/hotplug/Kconfig"
  919. endmenu
  920. menu "Executable file formats"
  921. source "fs/Kconfig.binfmt"
  922. endmenu
  923. menu "Power management options"
  924. source "kernel/power/Kconfig"
  925. config ARCH_SUSPEND_POSSIBLE
  926. def_bool y
  927. choice
  928. prompt "Standby Power Saving Mode"
  929. depends on PM
  930. default PM_BFIN_SLEEP_DEEPER
  931. config PM_BFIN_SLEEP_DEEPER
  932. bool "Sleep Deeper"
  933. help
  934. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  935. power dissipation by disabling the clock to the processor core (CCLK).
  936. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  937. to 0.85 V to provide the greatest power savings, while preserving the
  938. processor state.
  939. The PLL and system clock (SCLK) continue to operate at a very low
  940. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  941. the SDRAM is put into Self Refresh Mode. Typically an external event
  942. such as GPIO interrupt or RTC activity wakes up the processor.
  943. Various Peripherals such as UART, SPORT, PPI may not function as
  944. normal during Sleep Deeper, due to the reduced SCLK frequency.
  945. When in the sleep mode, system DMA access to L1 memory is not supported.
  946. If unsure, select "Sleep Deeper".
  947. config PM_BFIN_SLEEP
  948. bool "Sleep"
  949. help
  950. Sleep Mode (High Power Savings) - The sleep mode reduces power
  951. dissipation by disabling the clock to the processor core (CCLK).
  952. The PLL and system clock (SCLK), however, continue to operate in
  953. this mode. Typically an external event or RTC activity will wake
  954. up the processor. When in the sleep mode, system DMA access to L1
  955. memory is not supported.
  956. If unsure, select "Sleep Deeper".
  957. endchoice
  958. config PM_WAKEUP_BY_GPIO
  959. bool "Allow Wakeup from Standby by GPIO"
  960. depends on PM && !BF54x
  961. config PM_WAKEUP_GPIO_NUMBER
  962. int "GPIO number"
  963. range 0 47
  964. depends on PM_WAKEUP_BY_GPIO
  965. default 2
  966. choice
  967. prompt "GPIO Polarity"
  968. depends on PM_WAKEUP_BY_GPIO
  969. default PM_WAKEUP_GPIO_POLAR_H
  970. config PM_WAKEUP_GPIO_POLAR_H
  971. bool "Active High"
  972. config PM_WAKEUP_GPIO_POLAR_L
  973. bool "Active Low"
  974. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  975. bool "Falling EDGE"
  976. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  977. bool "Rising EDGE"
  978. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  979. bool "Both EDGE"
  980. endchoice
  981. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  982. depends on PM
  983. config PM_BFIN_WAKE_PH6
  984. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  985. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  986. default n
  987. help
  988. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  989. config PM_BFIN_WAKE_GP
  990. bool "Allow Wake-Up from GPIOs"
  991. depends on PM && BF54x
  992. default n
  993. help
  994. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  995. (all processors, except ADSP-BF549). This option sets
  996. the general-purpose wake-up enable (GPWE) control bit to enable
  997. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  998. On ADSP-BF549 this option enables the the same functionality on the
  999. /MRXON pin also PH7.
  1000. endmenu
  1001. menu "CPU Frequency scaling"
  1002. depends on !SMP
  1003. source "drivers/cpufreq/Kconfig"
  1004. config BFIN_CPU_FREQ
  1005. bool
  1006. depends on CPU_FREQ
  1007. select CPU_FREQ_TABLE
  1008. default y
  1009. config CPU_VOLTAGE
  1010. bool "CPU Voltage scaling"
  1011. depends on EXPERIMENTAL
  1012. depends on CPU_FREQ
  1013. default n
  1014. help
  1015. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1016. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1017. manuals. There is a theoretical risk that during VDDINT transitions
  1018. the PLL may unlock.
  1019. endmenu
  1020. source "net/Kconfig"
  1021. source "drivers/Kconfig"
  1022. source "drivers/firmware/Kconfig"
  1023. source "fs/Kconfig"
  1024. source "arch/blackfin/Kconfig.debug"
  1025. source "security/Kconfig"
  1026. source "crypto/Kconfig"
  1027. source "lib/Kconfig"