qlcnic_83xx_hw.h 12 KB

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  1. #ifndef __QLCNIC_83XX_HW_H
  2. #define __QLCNIC_83XX_HW_H
  3. #include <linux/types.h>
  4. #include <linux/etherdevice.h>
  5. #include "qlcnic_hw.h"
  6. /* Directly mapped registers */
  7. #define QLC_83XX_CRB_WIN_BASE 0x3800
  8. #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
  9. #define QLC_83XX_SEM_LOCK_BASE 0x3840
  10. #define QLC_83XX_SEM_UNLOCK_BASE 0x3844
  11. #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
  12. #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
  13. #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
  14. #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
  15. #define QLC_83XX_LINK_SPEED_FACTOR 10
  16. #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
  17. #define QLC_83XX_INTX_PTR 0x38C0
  18. #define QLC_83XX_INTX_TRGR 0x38C4
  19. #define QLC_83XX_INTX_MASK 0x38C8
  20. #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
  21. #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
  22. #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
  23. #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
  24. #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
  25. #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
  26. #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
  27. #define QLC_83XX_NO_NIC_RESOURCE 0x5
  28. #define QLC_83XX_MAC_PRESENT 0xC
  29. #define QLC_83XX_MAC_ABSENT 0xD
  30. #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
  31. /* PEG status definitions */
  32. #define QLC_83XX_CMDPEG_COMPLETE 0xff01
  33. #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
  34. #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
  35. #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
  36. #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
  37. #define QLC_83XX_LEGACY_INTX_DELAY 4
  38. #define QLC_83XX_REG_DESC 1
  39. #define QLC_83XX_LRO_DESC 2
  40. #define QLC_83XX_CTRL_DESC 3
  41. #define QLC_83XX_FW_CAPABILITY_TSO BIT_6
  42. #define QLC_83XX_FW_CAP_LRO_MSS BIT_17
  43. #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
  44. #define QLC_83XX_HOST_SDS_MBX_IDX 8
  45. #define QLCNIC_HOST_RDS_MBX_IDX 88
  46. #define QLCNIC_MAX_RING_SETS 8
  47. struct qlcnic_intrpt_config {
  48. u8 type;
  49. u8 enabled;
  50. u16 id;
  51. u32 src;
  52. };
  53. struct qlcnic_macvlan_mbx {
  54. u8 mac[ETH_ALEN];
  55. u16 vlan;
  56. };
  57. /* Mailbox process AEN count */
  58. #define QLC_83XX_IDC_COMP_AEN 3
  59. #define QLC_83XX_MBX_AEN_CNT 5
  60. #define QLC_83XX_MODULE_LOADED 1
  61. #define QLC_83XX_MBX_READY 2
  62. #define QLC_83XX_MBX_AEN_ACK 3
  63. #define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
  64. #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
  65. #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
  66. #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
  67. #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
  68. #define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11)
  69. #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
  70. #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
  71. #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
  72. #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
  73. #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
  74. #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
  75. #define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
  76. #define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
  77. #define QLC_83XX_CFG_STD_PAUSE (1 << 5)
  78. #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
  79. #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
  80. #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
  81. #define QLC_83XX_ENABLE_AUTONEG (1 << 15)
  82. #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
  83. #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
  84. #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
  85. /* LED configuration settings */
  86. #define QLC_83XX_ENABLE_BEACON 0xe
  87. #define QLC_83XX_LED_RATE 0xff
  88. #define QLC_83XX_LED_ACT (1 << 10)
  89. #define QLC_83XX_LED_MOD (0 << 13)
  90. #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
  91. QLC_83XX_LED_MOD)
  92. #define QLC_83XX_10M_LINK 1
  93. #define QLC_83XX_100M_LINK 2
  94. #define QLC_83XX_1G_LINK 3
  95. #define QLC_83XX_10G_LINK 4
  96. #define QLC_83XX_STAT_TX 3
  97. #define QLC_83XX_STAT_RX 2
  98. #define QLC_83XX_STAT_MAC 1
  99. #define QLC_83XX_TX_STAT_REGS 14
  100. #define QLC_83XX_RX_STAT_REGS 40
  101. #define QLC_83XX_MAC_STAT_REGS 80
  102. #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
  103. #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
  104. #define QLC_83XX_DEFAULT_OPMODE 0x55555555
  105. #define QLC_83XX_PRIVLEGED_FUNC 0x1
  106. #define QLC_83XX_VIRTUAL_FUNC 0x2
  107. #define QLC_83XX_LB_MAX_FILTERS 2048
  108. #define QLC_83XX_LB_BUCKET_SIZE 256
  109. #define QLC_83XX_MINIMUM_VECTOR 3
  110. #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
  111. #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
  112. #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
  113. #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
  114. #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
  115. #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
  116. #define QLC_83XX_VIRTUAL_NIC_MODE 0xFF
  117. #define QLC_83XX_DEFAULT_MODE 0x0
  118. #define QLCNIC_BRDTYPE_83XX_10G 0x0083
  119. #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
  120. #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
  121. #define QLC_83XX_FLASH_STATUS 0x42100004
  122. #define QLC_83XX_FLASH_CONTROL 0x42110004
  123. #define QLC_83XX_FLASH_ADDR 0x42110008
  124. #define QLC_83XX_FLASH_WRDATA 0x4211000C
  125. #define QLC_83XX_FLASH_RDDATA 0x42110018
  126. #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
  127. #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
  128. #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
  129. #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
  130. #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
  131. #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
  132. #define QLC_83XX_FLASH_STATUS_READY 0x6
  133. #define QLC_83XX_FLASH_BULK_WRITE_MIN 2
  134. #define QLC_83XX_FLASH_BULK_WRITE_MAX 64
  135. #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
  136. #define QLC_83XX_ERASE_MODE 1
  137. #define QLC_83XX_WRITE_MODE 2
  138. #define QLC_83XX_BULK_WRITE_MODE 3
  139. #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
  140. #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
  141. #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
  142. #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
  143. #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
  144. #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
  145. #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
  146. #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
  147. #define QLC_83XX_FLASH_WRDATA_DEF 0x0
  148. #define QLC_83XX_FLASH_READ_CTRL 0x3F
  149. #define QLC_83XX_FLASH_SPI_CTRL 0x4
  150. #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
  151. #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
  152. #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
  153. #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
  154. #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
  155. #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
  156. #define QLC_83xx_FLASH_MAX_WAIT_USEC 100
  157. #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
  158. /* Additional registers in 83xx */
  159. enum qlc_83xx_ext_regs {
  160. QLCNIC_GLOBAL_RESET = 0,
  161. QLCNIC_WILDCARD,
  162. QLCNIC_INFORMANT,
  163. QLCNIC_HOST_MBX_CTRL,
  164. QLCNIC_FW_MBX_CTRL,
  165. QLCNIC_BOOTLOADER_ADDR,
  166. QLCNIC_BOOTLOADER_SIZE,
  167. QLCNIC_FW_IMAGE_ADDR,
  168. QLCNIC_MBX_INTR_ENBL,
  169. QLCNIC_DEF_INT_MASK,
  170. QLCNIC_DEF_INT_ID,
  171. QLC_83XX_IDC_MAJ_VERSION,
  172. QLC_83XX_IDC_DEV_STATE,
  173. QLC_83XX_IDC_DRV_PRESENCE,
  174. QLC_83XX_IDC_DRV_ACK,
  175. QLC_83XX_IDC_CTRL,
  176. QLC_83XX_IDC_DRV_AUDIT,
  177. QLC_83XX_IDC_MIN_VERSION,
  178. QLC_83XX_RECOVER_DRV_LOCK,
  179. QLC_83XX_IDC_PF_0,
  180. QLC_83XX_IDC_PF_1,
  181. QLC_83XX_IDC_PF_2,
  182. QLC_83XX_IDC_PF_3,
  183. QLC_83XX_IDC_PF_4,
  184. QLC_83XX_IDC_PF_5,
  185. QLC_83XX_IDC_PF_6,
  186. QLC_83XX_IDC_PF_7,
  187. QLC_83XX_IDC_PF_8,
  188. QLC_83XX_IDC_PF_9,
  189. QLC_83XX_IDC_PF_10,
  190. QLC_83XX_IDC_PF_11,
  191. QLC_83XX_IDC_PF_12,
  192. QLC_83XX_IDC_PF_13,
  193. QLC_83XX_IDC_PF_14,
  194. QLC_83XX_IDC_PF_15,
  195. QLC_83XX_IDC_DEV_PARTITION_INFO_1,
  196. QLC_83XX_IDC_DEV_PARTITION_INFO_2,
  197. QLC_83XX_DRV_OP_MODE,
  198. QLC_83XX_VNIC_STATE,
  199. QLC_83XX_DRV_LOCK,
  200. QLC_83XX_DRV_UNLOCK,
  201. QLC_83XX_DRV_LOCK_ID,
  202. QLC_83XX_ASIC_TEMP,
  203. };
  204. /* 83xx funcitons */
  205. int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
  206. int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
  207. int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
  208. void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
  209. int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
  210. void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
  211. int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
  212. void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
  213. void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
  214. void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
  215. void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
  216. int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
  217. int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
  218. void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
  219. int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
  220. int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
  221. int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
  222. int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
  223. int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
  224. int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
  225. void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);
  226. int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
  227. int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
  228. void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
  229. int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
  230. void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
  231. void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
  232. void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
  233. int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
  234. void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
  235. int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
  236. void qlcnic_83xx_get_stats(struct qlcnic_adapter *,
  237. struct ethtool_stats *, u64 *);
  238. int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
  239. int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
  240. struct qlcnic_host_tx_ring *, int);
  241. int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
  242. int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
  243. void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
  244. int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
  245. int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
  246. int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
  247. void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
  248. struct qlcnic_cmd_args *);
  249. int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
  250. struct qlcnic_adapter *, u32);
  251. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
  252. void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
  253. struct qlcnic_info *);
  254. void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
  255. irqreturn_t qlcnic_83xx_handle_aen(int, void *);
  256. int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
  257. void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
  258. irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
  259. irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
  260. void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
  261. struct qlcnic_host_sds_ring *);
  262. void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
  263. const struct pci_device_id *);
  264. void qlcnic_83xx_process_aen(struct qlcnic_adapter *);
  265. int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
  266. int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
  267. int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
  268. int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
  269. int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
  270. int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
  271. void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
  272. void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
  273. void qlcnic_83xx_idc_aen_work(struct work_struct *);
  274. void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
  275. int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
  276. int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
  277. int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
  278. int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
  279. void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
  280. int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
  281. int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
  282. int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
  283. int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
  284. #endif