ql4_mbx.c 36 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. /* To prevent overwriting mailbox registers for a command that has
  81. * not yet been serviced, check to see if an active command
  82. * (AEN, IOCB, etc.) is interrupting, then service it.
  83. * -----------------------------------------------------------------
  84. */
  85. spin_lock_irqsave(&ha->hardware_lock, flags);
  86. if (!is_qla8022(ha)) {
  87. intr_status = readl(&ha->reg->ctrl_status);
  88. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  89. /* Service existing interrupt */
  90. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  91. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  92. }
  93. }
  94. ha->mbox_status_count = outCount;
  95. for (i = 0; i < outCount; i++)
  96. ha->mbox_status[i] = 0;
  97. if (is_qla8022(ha)) {
  98. /* Load all mailbox registers, except mailbox 0. */
  99. DEBUG5(
  100. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  101. for (i = 0; i < inCount; i++)
  102. printk("mb%d=%04x ", i, mbx_cmd[i]);
  103. printk("\n"));
  104. for (i = 1; i < inCount; i++)
  105. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  106. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  107. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  108. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  109. } else {
  110. /* Load all mailbox registers, except mailbox 0. */
  111. for (i = 1; i < inCount; i++)
  112. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  113. /* Wakeup firmware */
  114. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  115. readl(&ha->reg->mailbox[0]);
  116. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  117. readl(&ha->reg->ctrl_status);
  118. }
  119. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  120. /* Wait for completion */
  121. /*
  122. * If we don't want status, don't wait for the mailbox command to
  123. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  124. * you must poll the inbound Interrupt Mask for completion.
  125. */
  126. if (outCount == 0) {
  127. status = QLA_SUCCESS;
  128. goto mbox_exit;
  129. }
  130. /*
  131. * Wait for completion: Poll or completion queue
  132. */
  133. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  134. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  135. test_bit(AF_ONLINE, &ha->flags) &&
  136. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  137. /* Do not poll for completion. Use completion queue */
  138. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  139. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  140. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  141. } else {
  142. /* Poll for command to complete */
  143. wait_count = jiffies + MBOX_TOV * HZ;
  144. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  145. if (time_after_eq(jiffies, wait_count))
  146. break;
  147. /*
  148. * Service the interrupt.
  149. * The ISR will save the mailbox status registers
  150. * to a temporary storage location in the adapter
  151. * structure.
  152. */
  153. spin_lock_irqsave(&ha->hardware_lock, flags);
  154. if (is_qla8022(ha)) {
  155. intr_status =
  156. readl(&ha->qla4_8xxx_reg->host_int);
  157. if (intr_status & ISRX_82XX_RISC_INT) {
  158. ha->mbox_status_count = outCount;
  159. intr_status =
  160. readl(&ha->qla4_8xxx_reg->host_status);
  161. ha->isp_ops->interrupt_service_routine(
  162. ha, intr_status);
  163. if (test_bit(AF_INTERRUPTS_ON,
  164. &ha->flags) &&
  165. test_bit(AF_INTx_ENABLED,
  166. &ha->flags))
  167. qla4_8xxx_wr_32(ha,
  168. ha->nx_legacy_intr.tgt_mask_reg,
  169. 0xfbff);
  170. }
  171. } else {
  172. intr_status = readl(&ha->reg->ctrl_status);
  173. if (intr_status & INTR_PENDING) {
  174. /*
  175. * Service the interrupt.
  176. * The ISR will save the mailbox status
  177. * registers to a temporary storage
  178. * location in the adapter structure.
  179. */
  180. ha->mbox_status_count = outCount;
  181. ha->isp_ops->interrupt_service_routine(
  182. ha, intr_status);
  183. }
  184. }
  185. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  186. msleep(10);
  187. }
  188. }
  189. /* Check for mailbox timeout. */
  190. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  191. if (is_qla8022(ha) &&
  192. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  193. DEBUG2(ql4_printk(KERN_INFO, ha,
  194. "scsi%ld: %s: prematurely completing mbx cmd as "
  195. "firmware recovery detected\n",
  196. ha->host_no, __func__));
  197. goto mbox_exit;
  198. }
  199. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  200. " Scheduling Adapter Reset\n", ha->host_no,
  201. mbx_cmd[0]));
  202. ha->mailbox_timeout_count++;
  203. mbx_sts[0] = (-1);
  204. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  205. goto mbox_exit;
  206. }
  207. /*
  208. * Copy the mailbox out registers to the caller's mailbox in/out
  209. * structure.
  210. */
  211. spin_lock_irqsave(&ha->hardware_lock, flags);
  212. for (i = 0; i < outCount; i++)
  213. mbx_sts[i] = ha->mbox_status[i];
  214. /* Set return status and error flags (if applicable). */
  215. switch (ha->mbox_status[0]) {
  216. case MBOX_STS_COMMAND_COMPLETE:
  217. status = QLA_SUCCESS;
  218. break;
  219. case MBOX_STS_INTERMEDIATE_COMPLETION:
  220. status = QLA_SUCCESS;
  221. break;
  222. case MBOX_STS_BUSY:
  223. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  224. ha->host_no, __func__, mbx_cmd[0]));
  225. ha->mailbox_timeout_count++;
  226. break;
  227. default:
  228. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  229. "sts = %08X ****\n", ha->host_no, __func__,
  230. mbx_cmd[0], mbx_sts[0]));
  231. break;
  232. }
  233. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  234. mbox_exit:
  235. mutex_lock(&ha->mbox_sem);
  236. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  237. mutex_unlock(&ha->mbox_sem);
  238. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  239. return status;
  240. }
  241. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  242. {
  243. set_bit(AF_FW_RECOVERY, &ha->flags);
  244. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  245. ha->host_no, __func__);
  246. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  247. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  248. complete(&ha->mbx_intr_comp);
  249. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  250. "recovery, doing premature completion of "
  251. "mbx cmd\n", ha->host_no, __func__);
  252. } else {
  253. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  254. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  255. "recovery, doing premature completion of "
  256. "polling mbx cmd\n", ha->host_no, __func__);
  257. }
  258. }
  259. }
  260. static uint8_t
  261. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  262. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  263. {
  264. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  265. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  266. if (is_qla8022(ha))
  267. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  268. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  269. mbox_cmd[1] = 0;
  270. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  271. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  272. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  273. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  274. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  275. QLA_SUCCESS) {
  276. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  277. "MBOX_CMD_INITIALIZE_FIRMWARE"
  278. " failed w/ status %04X\n",
  279. ha->host_no, __func__, mbox_sts[0]));
  280. return QLA_ERROR;
  281. }
  282. return QLA_SUCCESS;
  283. }
  284. static uint8_t
  285. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  286. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  287. {
  288. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  289. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  290. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  291. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  292. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  293. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  294. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  295. QLA_SUCCESS) {
  296. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  297. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  298. " failed w/ status %04X\n",
  299. ha->host_no, __func__, mbox_sts[0]));
  300. return QLA_ERROR;
  301. }
  302. return QLA_SUCCESS;
  303. }
  304. static void
  305. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  306. struct addr_ctrl_blk *init_fw_cb)
  307. {
  308. /* Save IPv4 Address Info */
  309. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  310. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  311. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  312. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  313. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  314. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  315. if (is_ipv6_enabled(ha)) {
  316. /* Save IPv6 Address */
  317. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  318. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  319. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  320. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  321. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  322. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  323. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  324. init_fw_cb->ipv6_if_id,
  325. min(sizeof(ha->ipv6_link_local_addr)/2,
  326. sizeof(init_fw_cb->ipv6_if_id)));
  327. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  328. min(sizeof(ha->ipv6_addr0),
  329. sizeof(init_fw_cb->ipv6_addr0)));
  330. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  331. min(sizeof(ha->ipv6_addr1),
  332. sizeof(init_fw_cb->ipv6_addr1)));
  333. memcpy(&ha->ipv6_default_router_addr,
  334. init_fw_cb->ipv6_dflt_rtr_addr,
  335. min(sizeof(ha->ipv6_default_router_addr),
  336. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  337. }
  338. }
  339. static uint8_t
  340. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  341. uint32_t *mbox_cmd,
  342. uint32_t *mbox_sts,
  343. struct addr_ctrl_blk *init_fw_cb,
  344. dma_addr_t init_fw_cb_dma)
  345. {
  346. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  347. != QLA_SUCCESS) {
  348. DEBUG2(printk(KERN_WARNING
  349. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  350. ha->host_no, __func__));
  351. return QLA_ERROR;
  352. }
  353. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  354. /* Save some info in adapter structure. */
  355. ha->acb_version = init_fw_cb->acb_version;
  356. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  357. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  358. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  359. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  360. ha->heartbeat_interval = init_fw_cb->hb_interval;
  361. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  362. min(sizeof(ha->name_string),
  363. sizeof(init_fw_cb->iscsi_name)));
  364. /*memcpy(ha->alias, init_fw_cb->Alias,
  365. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  366. if (ha->acb_version == ACB_SUPPORTED) {
  367. ha->ipv6_options = init_fw_cb->ipv6_opts;
  368. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  369. }
  370. qla4xxx_update_local_ip(ha, init_fw_cb);
  371. return QLA_SUCCESS;
  372. }
  373. /**
  374. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  375. * @ha: Pointer to host adapter structure.
  376. **/
  377. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  378. {
  379. struct addr_ctrl_blk *init_fw_cb;
  380. dma_addr_t init_fw_cb_dma;
  381. uint32_t mbox_cmd[MBOX_REG_COUNT];
  382. uint32_t mbox_sts[MBOX_REG_COUNT];
  383. int status = QLA_ERROR;
  384. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  385. sizeof(struct addr_ctrl_blk),
  386. &init_fw_cb_dma, GFP_KERNEL);
  387. if (init_fw_cb == NULL) {
  388. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  389. ha->host_no, __func__));
  390. goto exit_init_fw_cb_no_free;
  391. }
  392. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  393. /* Get Initialize Firmware Control Block. */
  394. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  395. memset(&mbox_sts, 0, sizeof(mbox_sts));
  396. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  397. QLA_SUCCESS) {
  398. dma_free_coherent(&ha->pdev->dev,
  399. sizeof(struct addr_ctrl_blk),
  400. init_fw_cb, init_fw_cb_dma);
  401. goto exit_init_fw_cb;
  402. }
  403. /* Initialize request and response queues. */
  404. qla4xxx_init_rings(ha);
  405. /* Fill in the request and response queue information. */
  406. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  407. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  408. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  409. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  410. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  411. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  412. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  413. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  414. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  415. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  416. /* Set up required options. */
  417. init_fw_cb->fw_options |=
  418. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  419. FWOPT_INITIATOR_MODE);
  420. if (is_qla8022(ha))
  421. init_fw_cb->fw_options |=
  422. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  423. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  424. /* Set bit for "serialize task mgmt" all other bits need to be zero */
  425. init_fw_cb->add_fw_options = 0;
  426. init_fw_cb->add_fw_options |=
  427. __constant_cpu_to_le16(SERIALIZE_TASK_MGMT);
  428. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  429. != QLA_SUCCESS) {
  430. DEBUG2(printk(KERN_WARNING
  431. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  432. ha->host_no, __func__));
  433. goto exit_init_fw_cb;
  434. }
  435. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  436. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  437. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  438. ha->host_no, __func__));
  439. goto exit_init_fw_cb;
  440. }
  441. status = QLA_SUCCESS;
  442. exit_init_fw_cb:
  443. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  444. init_fw_cb, init_fw_cb_dma);
  445. exit_init_fw_cb_no_free:
  446. return status;
  447. }
  448. /**
  449. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  450. * @ha: Pointer to host adapter structure.
  451. **/
  452. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  453. {
  454. struct addr_ctrl_blk *init_fw_cb;
  455. dma_addr_t init_fw_cb_dma;
  456. uint32_t mbox_cmd[MBOX_REG_COUNT];
  457. uint32_t mbox_sts[MBOX_REG_COUNT];
  458. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  459. sizeof(struct addr_ctrl_blk),
  460. &init_fw_cb_dma, GFP_KERNEL);
  461. if (init_fw_cb == NULL) {
  462. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  463. __func__);
  464. return QLA_ERROR;
  465. }
  466. /* Get Initialize Firmware Control Block. */
  467. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  468. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  469. QLA_SUCCESS) {
  470. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  471. ha->host_no, __func__));
  472. dma_free_coherent(&ha->pdev->dev,
  473. sizeof(struct addr_ctrl_blk),
  474. init_fw_cb, init_fw_cb_dma);
  475. return QLA_ERROR;
  476. }
  477. /* Save IP Address. */
  478. qla4xxx_update_local_ip(ha, init_fw_cb);
  479. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  480. init_fw_cb, init_fw_cb_dma);
  481. return QLA_SUCCESS;
  482. }
  483. /**
  484. * qla4xxx_get_firmware_state - gets firmware state of HBA
  485. * @ha: Pointer to host adapter structure.
  486. **/
  487. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  488. {
  489. uint32_t mbox_cmd[MBOX_REG_COUNT];
  490. uint32_t mbox_sts[MBOX_REG_COUNT];
  491. /* Get firmware version */
  492. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  493. memset(&mbox_sts, 0, sizeof(mbox_sts));
  494. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  495. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  496. QLA_SUCCESS) {
  497. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  498. "status %04X\n", ha->host_no, __func__,
  499. mbox_sts[0]));
  500. return QLA_ERROR;
  501. }
  502. ha->firmware_state = mbox_sts[1];
  503. ha->board_id = mbox_sts[2];
  504. ha->addl_fw_state = mbox_sts[3];
  505. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  506. ha->host_no, __func__, ha->firmware_state);)
  507. return QLA_SUCCESS;
  508. }
  509. /**
  510. * qla4xxx_get_firmware_status - retrieves firmware status
  511. * @ha: Pointer to host adapter structure.
  512. **/
  513. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  514. {
  515. uint32_t mbox_cmd[MBOX_REG_COUNT];
  516. uint32_t mbox_sts[MBOX_REG_COUNT];
  517. /* Get firmware version */
  518. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  519. memset(&mbox_sts, 0, sizeof(mbox_sts));
  520. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  521. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  522. QLA_SUCCESS) {
  523. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  524. "status %04X\n", ha->host_no, __func__,
  525. mbox_sts[0]));
  526. return QLA_ERROR;
  527. }
  528. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  529. ha->host_no, mbox_sts[2]);
  530. return QLA_SUCCESS;
  531. }
  532. /**
  533. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  534. * @ha: Pointer to host adapter structure.
  535. * @fw_ddb_index: Firmware's device database index
  536. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  537. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  538. * @next_ddb_index: Pointer to next valid device database index
  539. * @fw_ddb_device_state: Pointer to device state
  540. **/
  541. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  542. uint16_t fw_ddb_index,
  543. struct dev_db_entry *fw_ddb_entry,
  544. dma_addr_t fw_ddb_entry_dma,
  545. uint32_t *num_valid_ddb_entries,
  546. uint32_t *next_ddb_index,
  547. uint32_t *fw_ddb_device_state,
  548. uint32_t *conn_err_detail,
  549. uint16_t *tcp_source_port_num,
  550. uint16_t *connection_id)
  551. {
  552. int status = QLA_ERROR;
  553. uint16_t options;
  554. uint32_t mbox_cmd[MBOX_REG_COUNT];
  555. uint32_t mbox_sts[MBOX_REG_COUNT];
  556. /* Make sure the device index is valid */
  557. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  558. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  559. ha->host_no, __func__, fw_ddb_index));
  560. goto exit_get_fwddb;
  561. }
  562. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  563. memset(&mbox_sts, 0, sizeof(mbox_sts));
  564. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  565. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  566. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  567. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  568. mbox_cmd[4] = sizeof(struct dev_db_entry);
  569. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  570. QLA_ERROR) {
  571. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  572. " with status 0x%04X\n", ha->host_no, __func__,
  573. mbox_sts[0]));
  574. goto exit_get_fwddb;
  575. }
  576. if (fw_ddb_index != mbox_sts[1]) {
  577. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  578. ha->host_no, __func__, fw_ddb_index,
  579. mbox_sts[1]));
  580. goto exit_get_fwddb;
  581. }
  582. if (fw_ddb_entry) {
  583. options = le16_to_cpu(fw_ddb_entry->options);
  584. if (options & DDB_OPT_IPV6_DEVICE) {
  585. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  586. "Next %d State %04x ConnErr %08x %pI6 "
  587. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  588. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  589. mbox_sts[4], mbox_sts[5],
  590. fw_ddb_entry->ip_addr,
  591. le16_to_cpu(fw_ddb_entry->port),
  592. fw_ddb_entry->iscsi_name);
  593. } else {
  594. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  595. "Next %d State %04x ConnErr %08x %pI4 "
  596. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  597. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  598. mbox_sts[4], mbox_sts[5],
  599. fw_ddb_entry->ip_addr,
  600. le16_to_cpu(fw_ddb_entry->port),
  601. fw_ddb_entry->iscsi_name);
  602. }
  603. }
  604. if (num_valid_ddb_entries)
  605. *num_valid_ddb_entries = mbox_sts[2];
  606. if (next_ddb_index)
  607. *next_ddb_index = mbox_sts[3];
  608. if (fw_ddb_device_state)
  609. *fw_ddb_device_state = mbox_sts[4];
  610. /*
  611. * RA: This mailbox has been changed to pass connection error and
  612. * details. Its true for ISP4010 as per Version E - Not sure when it
  613. * was changed. Get the time2wait from the fw_dd_entry field :
  614. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  615. * struct.
  616. */
  617. if (conn_err_detail)
  618. *conn_err_detail = mbox_sts[5];
  619. if (tcp_source_port_num)
  620. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  621. if (connection_id)
  622. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  623. status = QLA_SUCCESS;
  624. exit_get_fwddb:
  625. return status;
  626. }
  627. /**
  628. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  629. * @ha: Pointer to host adapter structure.
  630. * @fw_ddb_index: Firmware's device database index
  631. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  632. *
  633. * This routine initializes or updates the adapter's device database
  634. * entry for the specified device. It also triggers a login for the
  635. * specified device. Therefore, it may also be used as a secondary
  636. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  637. **/
  638. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  639. dma_addr_t fw_ddb_entry_dma)
  640. {
  641. uint32_t mbox_cmd[MBOX_REG_COUNT];
  642. uint32_t mbox_sts[MBOX_REG_COUNT];
  643. int status;
  644. /* Do not wait for completion. The firmware will send us an
  645. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  646. */
  647. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  648. memset(&mbox_sts, 0, sizeof(mbox_sts));
  649. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  650. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  651. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  652. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  653. mbox_cmd[4] = sizeof(struct dev_db_entry);
  654. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  655. &mbox_sts[0]);
  656. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  657. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  658. return status;
  659. }
  660. /**
  661. * qla4xxx_get_crash_record - retrieves crash record.
  662. * @ha: Pointer to host adapter structure.
  663. *
  664. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  665. **/
  666. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  667. {
  668. uint32_t mbox_cmd[MBOX_REG_COUNT];
  669. uint32_t mbox_sts[MBOX_REG_COUNT];
  670. struct crash_record *crash_record = NULL;
  671. dma_addr_t crash_record_dma = 0;
  672. uint32_t crash_record_size = 0;
  673. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  674. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  675. /* Get size of crash record. */
  676. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  677. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  678. QLA_SUCCESS) {
  679. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  680. ha->host_no, __func__));
  681. goto exit_get_crash_record;
  682. }
  683. crash_record_size = mbox_sts[4];
  684. if (crash_record_size == 0) {
  685. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  686. ha->host_no, __func__));
  687. goto exit_get_crash_record;
  688. }
  689. /* Alloc Memory for Crash Record. */
  690. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  691. &crash_record_dma, GFP_KERNEL);
  692. if (crash_record == NULL)
  693. goto exit_get_crash_record;
  694. /* Get Crash Record. */
  695. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  696. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  697. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  698. mbox_cmd[2] = LSDW(crash_record_dma);
  699. mbox_cmd[3] = MSDW(crash_record_dma);
  700. mbox_cmd[4] = crash_record_size;
  701. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  702. QLA_SUCCESS)
  703. goto exit_get_crash_record;
  704. /* Dump Crash Record. */
  705. exit_get_crash_record:
  706. if (crash_record)
  707. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  708. crash_record, crash_record_dma);
  709. }
  710. /**
  711. * qla4xxx_get_conn_event_log - retrieves connection event log
  712. * @ha: Pointer to host adapter structure.
  713. **/
  714. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  715. {
  716. uint32_t mbox_cmd[MBOX_REG_COUNT];
  717. uint32_t mbox_sts[MBOX_REG_COUNT];
  718. struct conn_event_log_entry *event_log = NULL;
  719. dma_addr_t event_log_dma = 0;
  720. uint32_t event_log_size = 0;
  721. uint32_t num_valid_entries;
  722. uint32_t oldest_entry = 0;
  723. uint32_t max_event_log_entries;
  724. uint8_t i;
  725. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  726. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  727. /* Get size of crash record. */
  728. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  729. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  730. QLA_SUCCESS)
  731. goto exit_get_event_log;
  732. event_log_size = mbox_sts[4];
  733. if (event_log_size == 0)
  734. goto exit_get_event_log;
  735. /* Alloc Memory for Crash Record. */
  736. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  737. &event_log_dma, GFP_KERNEL);
  738. if (event_log == NULL)
  739. goto exit_get_event_log;
  740. /* Get Crash Record. */
  741. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  742. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  743. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  744. mbox_cmd[2] = LSDW(event_log_dma);
  745. mbox_cmd[3] = MSDW(event_log_dma);
  746. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  747. QLA_SUCCESS) {
  748. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  749. "log!\n", ha->host_no, __func__));
  750. goto exit_get_event_log;
  751. }
  752. /* Dump Event Log. */
  753. num_valid_entries = mbox_sts[1];
  754. max_event_log_entries = event_log_size /
  755. sizeof(struct conn_event_log_entry);
  756. if (num_valid_entries > max_event_log_entries)
  757. oldest_entry = num_valid_entries % max_event_log_entries;
  758. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  759. ha->host_no, num_valid_entries));
  760. if (ql4xextended_error_logging == 3) {
  761. if (oldest_entry == 0) {
  762. /* Circular Buffer has not wrapped around */
  763. for (i=0; i < num_valid_entries; i++) {
  764. qla4xxx_dump_buffer((uint8_t *)event_log+
  765. (i*sizeof(*event_log)),
  766. sizeof(*event_log));
  767. }
  768. }
  769. else {
  770. /* Circular Buffer has wrapped around -
  771. * display accordingly*/
  772. for (i=oldest_entry; i < max_event_log_entries; i++) {
  773. qla4xxx_dump_buffer((uint8_t *)event_log+
  774. (i*sizeof(*event_log)),
  775. sizeof(*event_log));
  776. }
  777. for (i=0; i < oldest_entry; i++) {
  778. qla4xxx_dump_buffer((uint8_t *)event_log+
  779. (i*sizeof(*event_log)),
  780. sizeof(*event_log));
  781. }
  782. }
  783. }
  784. exit_get_event_log:
  785. if (event_log)
  786. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  787. event_log_dma);
  788. }
  789. /**
  790. * qla4xxx_abort_task - issues Abort Task
  791. * @ha: Pointer to host adapter structure.
  792. * @srb: Pointer to srb entry
  793. *
  794. * This routine performs a LUN RESET on the specified target/lun.
  795. * The caller must ensure that the ddb_entry and lun_entry pointers
  796. * are valid before calling this routine.
  797. **/
  798. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  799. {
  800. uint32_t mbox_cmd[MBOX_REG_COUNT];
  801. uint32_t mbox_sts[MBOX_REG_COUNT];
  802. struct scsi_cmnd *cmd = srb->cmd;
  803. int status = QLA_SUCCESS;
  804. unsigned long flags = 0;
  805. uint32_t index;
  806. /*
  807. * Send abort task command to ISP, so that the ISP will return
  808. * request with ABORT status
  809. */
  810. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  811. memset(&mbox_sts, 0, sizeof(mbox_sts));
  812. spin_lock_irqsave(&ha->hardware_lock, flags);
  813. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  814. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  815. /* Firmware already posted completion on response queue */
  816. if (index == MAX_SRBS)
  817. return status;
  818. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  819. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  820. mbox_cmd[2] = index;
  821. /* Immediate Command Enable */
  822. mbox_cmd[5] = 0x01;
  823. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  824. &mbox_sts[0]);
  825. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  826. status = QLA_ERROR;
  827. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  828. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  829. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  830. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  831. }
  832. return status;
  833. }
  834. /**
  835. * qla4xxx_reset_lun - issues LUN Reset
  836. * @ha: Pointer to host adapter structure.
  837. * @ddb_entry: Pointer to device database entry
  838. * @lun: lun number
  839. *
  840. * This routine performs a LUN RESET on the specified target/lun.
  841. * The caller must ensure that the ddb_entry and lun_entry pointers
  842. * are valid before calling this routine.
  843. **/
  844. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  845. int lun)
  846. {
  847. uint32_t mbox_cmd[MBOX_REG_COUNT];
  848. uint32_t mbox_sts[MBOX_REG_COUNT];
  849. int status = QLA_SUCCESS;
  850. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  851. ddb_entry->fw_ddb_index, lun));
  852. /*
  853. * Send lun reset command to ISP, so that the ISP will return all
  854. * outstanding requests with RESET status
  855. */
  856. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  857. memset(&mbox_sts, 0, sizeof(mbox_sts));
  858. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  859. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  860. mbox_cmd[2] = lun << 8;
  861. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  862. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  863. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  864. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  865. status = QLA_ERROR;
  866. return status;
  867. }
  868. /**
  869. * qla4xxx_reset_target - issues target Reset
  870. * @ha: Pointer to host adapter structure.
  871. * @db_entry: Pointer to device database entry
  872. * @un_entry: Pointer to lun entry structure
  873. *
  874. * This routine performs a TARGET RESET on the specified target.
  875. * The caller must ensure that the ddb_entry pointers
  876. * are valid before calling this routine.
  877. **/
  878. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  879. struct ddb_entry *ddb_entry)
  880. {
  881. uint32_t mbox_cmd[MBOX_REG_COUNT];
  882. uint32_t mbox_sts[MBOX_REG_COUNT];
  883. int status = QLA_SUCCESS;
  884. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  885. ddb_entry->fw_ddb_index));
  886. /*
  887. * Send target reset command to ISP, so that the ISP will return all
  888. * outstanding requests with RESET status
  889. */
  890. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  891. memset(&mbox_sts, 0, sizeof(mbox_sts));
  892. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  893. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  894. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  895. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  896. &mbox_sts[0]);
  897. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  898. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  899. status = QLA_ERROR;
  900. return status;
  901. }
  902. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  903. uint32_t offset, uint32_t len)
  904. {
  905. uint32_t mbox_cmd[MBOX_REG_COUNT];
  906. uint32_t mbox_sts[MBOX_REG_COUNT];
  907. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  908. memset(&mbox_sts, 0, sizeof(mbox_sts));
  909. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  910. mbox_cmd[1] = LSDW(dma_addr);
  911. mbox_cmd[2] = MSDW(dma_addr);
  912. mbox_cmd[3] = offset;
  913. mbox_cmd[4] = len;
  914. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  915. QLA_SUCCESS) {
  916. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  917. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  918. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  919. return QLA_ERROR;
  920. }
  921. return QLA_SUCCESS;
  922. }
  923. /**
  924. * qla4xxx_get_fw_version - gets firmware version
  925. * @ha: Pointer to host adapter structure.
  926. *
  927. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  928. * hold an address for data. Make sure that we write 0 to those mailboxes,
  929. * if unused.
  930. **/
  931. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  932. {
  933. uint32_t mbox_cmd[MBOX_REG_COUNT];
  934. uint32_t mbox_sts[MBOX_REG_COUNT];
  935. /* Get firmware version. */
  936. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  937. memset(&mbox_sts, 0, sizeof(mbox_sts));
  938. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  939. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  940. QLA_SUCCESS) {
  941. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  942. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  943. return QLA_ERROR;
  944. }
  945. /* Save firmware version information. */
  946. ha->firmware_version[0] = mbox_sts[1];
  947. ha->firmware_version[1] = mbox_sts[2];
  948. ha->patch_number = mbox_sts[3];
  949. ha->build_number = mbox_sts[4];
  950. return QLA_SUCCESS;
  951. }
  952. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  953. dma_addr_t dma_addr)
  954. {
  955. uint32_t mbox_cmd[MBOX_REG_COUNT];
  956. uint32_t mbox_sts[MBOX_REG_COUNT];
  957. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  958. memset(&mbox_sts, 0, sizeof(mbox_sts));
  959. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  960. mbox_cmd[2] = LSDW(dma_addr);
  961. mbox_cmd[3] = MSDW(dma_addr);
  962. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  963. QLA_SUCCESS) {
  964. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  965. ha->host_no, __func__, mbox_sts[0]));
  966. return QLA_ERROR;
  967. }
  968. return QLA_SUCCESS;
  969. }
  970. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  971. {
  972. uint32_t mbox_cmd[MBOX_REG_COUNT];
  973. uint32_t mbox_sts[MBOX_REG_COUNT];
  974. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  975. memset(&mbox_sts, 0, sizeof(mbox_sts));
  976. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  977. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  978. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  979. QLA_SUCCESS) {
  980. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  981. *ddb_index = mbox_sts[2];
  982. } else {
  983. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  984. ha->host_no, __func__, mbox_sts[0]));
  985. return QLA_ERROR;
  986. }
  987. } else {
  988. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  989. }
  990. return QLA_SUCCESS;
  991. }
  992. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  993. {
  994. struct dev_db_entry *fw_ddb_entry;
  995. dma_addr_t fw_ddb_entry_dma;
  996. uint32_t ddb_index;
  997. int ret_val = QLA_SUCCESS;
  998. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  999. sizeof(*fw_ddb_entry),
  1000. &fw_ddb_entry_dma, GFP_KERNEL);
  1001. if (!fw_ddb_entry) {
  1002. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  1003. ha->host_no, __func__));
  1004. ret_val = QLA_ERROR;
  1005. goto exit_send_tgts_no_free;
  1006. }
  1007. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  1008. if (ret_val != QLA_SUCCESS)
  1009. goto exit_send_tgts;
  1010. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1011. if (ret_val != QLA_SUCCESS)
  1012. goto exit_send_tgts;
  1013. memset(fw_ddb_entry->iscsi_alias, 0,
  1014. sizeof(fw_ddb_entry->iscsi_alias));
  1015. memset(fw_ddb_entry->iscsi_name, 0,
  1016. sizeof(fw_ddb_entry->iscsi_name));
  1017. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1018. memset(fw_ddb_entry->tgt_addr, 0,
  1019. sizeof(fw_ddb_entry->tgt_addr));
  1020. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1021. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1022. fw_ddb_entry->ip_addr[0] = *ip;
  1023. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1024. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1025. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1026. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1027. exit_send_tgts:
  1028. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1029. fw_ddb_entry, fw_ddb_entry_dma);
  1030. exit_send_tgts_no_free:
  1031. return ret_val;
  1032. }