smsc95xx.c 34 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc95xx.h"
  32. #define SMSC_CHIPNAME "smsc95xx"
  33. #define SMSC_DRIVER_VERSION "1.0.4"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (2048)
  40. #define LAN95XX_EEPROM_MAGIC (0x9500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC95XX_INTERNAL_PHY_ID (1)
  45. #define SMSC95XX_TX_OVERHEAD (8)
  46. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  47. struct smsc95xx_priv {
  48. u32 mac_cr;
  49. u32 hash_hi;
  50. u32 hash_lo;
  51. spinlock_t mac_cr_lock;
  52. bool use_tx_csum;
  53. bool use_rx_csum;
  54. };
  55. struct usb_context {
  56. struct usb_ctrlrequest req;
  57. struct usbnet *dev;
  58. };
  59. static int turbo_mode = true;
  60. module_param(turbo_mode, bool, 0644);
  61. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  62. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  63. {
  64. u32 *buf = kmalloc(4, GFP_KERNEL);
  65. int ret;
  66. BUG_ON(!dev);
  67. if (!buf)
  68. return -ENOMEM;
  69. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  70. USB_VENDOR_REQUEST_READ_REGISTER,
  71. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  72. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  73. if (unlikely(ret < 0))
  74. netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
  75. le32_to_cpus(buf);
  76. *data = *buf;
  77. kfree(buf);
  78. return ret;
  79. }
  80. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  81. {
  82. u32 *buf = kmalloc(4, GFP_KERNEL);
  83. int ret;
  84. BUG_ON(!dev);
  85. if (!buf)
  86. return -ENOMEM;
  87. *buf = data;
  88. cpu_to_le32s(buf);
  89. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  90. USB_VENDOR_REQUEST_WRITE_REGISTER,
  91. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  92. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  93. if (unlikely(ret < 0))
  94. netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
  95. kfree(buf);
  96. return ret;
  97. }
  98. /* Loop until the read is completed with timeout
  99. * called with phy_mutex held */
  100. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  101. {
  102. unsigned long start_time = jiffies;
  103. u32 val;
  104. do {
  105. smsc95xx_read_reg(dev, MII_ADDR, &val);
  106. if (!(val & MII_BUSY_))
  107. return 0;
  108. } while (!time_after(jiffies, start_time + HZ));
  109. return -EIO;
  110. }
  111. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  112. {
  113. struct usbnet *dev = netdev_priv(netdev);
  114. u32 val, addr;
  115. mutex_lock(&dev->phy_mutex);
  116. /* confirm MII not busy */
  117. if (smsc95xx_phy_wait_not_busy(dev)) {
  118. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  119. mutex_unlock(&dev->phy_mutex);
  120. return -EIO;
  121. }
  122. /* set the address, index & direction (read from PHY) */
  123. phy_id &= dev->mii.phy_id_mask;
  124. idx &= dev->mii.reg_num_mask;
  125. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  126. smsc95xx_write_reg(dev, MII_ADDR, addr);
  127. if (smsc95xx_phy_wait_not_busy(dev)) {
  128. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  129. mutex_unlock(&dev->phy_mutex);
  130. return -EIO;
  131. }
  132. smsc95xx_read_reg(dev, MII_DATA, &val);
  133. mutex_unlock(&dev->phy_mutex);
  134. return (u16)(val & 0xFFFF);
  135. }
  136. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  137. int regval)
  138. {
  139. struct usbnet *dev = netdev_priv(netdev);
  140. u32 val, addr;
  141. mutex_lock(&dev->phy_mutex);
  142. /* confirm MII not busy */
  143. if (smsc95xx_phy_wait_not_busy(dev)) {
  144. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  145. mutex_unlock(&dev->phy_mutex);
  146. return;
  147. }
  148. val = regval;
  149. smsc95xx_write_reg(dev, MII_DATA, val);
  150. /* set the address, index & direction (write to PHY) */
  151. phy_id &= dev->mii.phy_id_mask;
  152. idx &= dev->mii.reg_num_mask;
  153. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  154. smsc95xx_write_reg(dev, MII_ADDR, addr);
  155. if (smsc95xx_phy_wait_not_busy(dev))
  156. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  157. mutex_unlock(&dev->phy_mutex);
  158. }
  159. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  160. {
  161. unsigned long start_time = jiffies;
  162. u32 val;
  163. do {
  164. smsc95xx_read_reg(dev, E2P_CMD, &val);
  165. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  166. break;
  167. udelay(40);
  168. } while (!time_after(jiffies, start_time + HZ));
  169. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  170. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  171. return -EIO;
  172. }
  173. return 0;
  174. }
  175. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  176. {
  177. unsigned long start_time = jiffies;
  178. u32 val;
  179. do {
  180. smsc95xx_read_reg(dev, E2P_CMD, &val);
  181. if (!(val & E2P_CMD_BUSY_))
  182. return 0;
  183. udelay(40);
  184. } while (!time_after(jiffies, start_time + HZ));
  185. netdev_warn(dev->net, "EEPROM is busy\n");
  186. return -EIO;
  187. }
  188. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  189. u8 *data)
  190. {
  191. u32 val;
  192. int i, ret;
  193. BUG_ON(!dev);
  194. BUG_ON(!data);
  195. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  196. if (ret)
  197. return ret;
  198. for (i = 0; i < length; i++) {
  199. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  200. smsc95xx_write_reg(dev, E2P_CMD, val);
  201. ret = smsc95xx_wait_eeprom(dev);
  202. if (ret < 0)
  203. return ret;
  204. smsc95xx_read_reg(dev, E2P_DATA, &val);
  205. data[i] = val & 0xFF;
  206. offset++;
  207. }
  208. return 0;
  209. }
  210. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  211. u8 *data)
  212. {
  213. u32 val;
  214. int i, ret;
  215. BUG_ON(!dev);
  216. BUG_ON(!data);
  217. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  218. if (ret)
  219. return ret;
  220. /* Issue write/erase enable command */
  221. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  222. smsc95xx_write_reg(dev, E2P_CMD, val);
  223. ret = smsc95xx_wait_eeprom(dev);
  224. if (ret < 0)
  225. return ret;
  226. for (i = 0; i < length; i++) {
  227. /* Fill data register */
  228. val = data[i];
  229. smsc95xx_write_reg(dev, E2P_DATA, val);
  230. /* Send "write" command */
  231. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  232. smsc95xx_write_reg(dev, E2P_CMD, val);
  233. ret = smsc95xx_wait_eeprom(dev);
  234. if (ret < 0)
  235. return ret;
  236. offset++;
  237. }
  238. return 0;
  239. }
  240. static void smsc95xx_async_cmd_callback(struct urb *urb)
  241. {
  242. struct usb_context *usb_context = urb->context;
  243. struct usbnet *dev = usb_context->dev;
  244. int status = urb->status;
  245. if (status < 0)
  246. netdev_warn(dev->net, "async callback failed with %d\n", status);
  247. kfree(usb_context);
  248. usb_free_urb(urb);
  249. }
  250. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  251. {
  252. struct usb_context *usb_context;
  253. int status;
  254. struct urb *urb;
  255. const u16 size = 4;
  256. urb = usb_alloc_urb(0, GFP_ATOMIC);
  257. if (!urb) {
  258. netdev_warn(dev->net, "Error allocating URB\n");
  259. return -ENOMEM;
  260. }
  261. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  262. if (usb_context == NULL) {
  263. netdev_warn(dev->net, "Error allocating control msg\n");
  264. usb_free_urb(urb);
  265. return -ENOMEM;
  266. }
  267. usb_context->req.bRequestType =
  268. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  269. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  270. usb_context->req.wValue = 00;
  271. usb_context->req.wIndex = cpu_to_le16(index);
  272. usb_context->req.wLength = cpu_to_le16(size);
  273. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  274. (void *)&usb_context->req, data, size,
  275. smsc95xx_async_cmd_callback,
  276. (void *)usb_context);
  277. status = usb_submit_urb(urb, GFP_ATOMIC);
  278. if (status < 0) {
  279. netdev_warn(dev->net, "Error submitting control msg, sts=%d\n",
  280. status);
  281. kfree(usb_context);
  282. usb_free_urb(urb);
  283. }
  284. return status;
  285. }
  286. /* returns hash bit number for given MAC address
  287. * example:
  288. * 01 00 5E 00 00 01 -> returns bit number 31 */
  289. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  290. {
  291. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  292. }
  293. static void smsc95xx_set_multicast(struct net_device *netdev)
  294. {
  295. struct usbnet *dev = netdev_priv(netdev);
  296. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  297. unsigned long flags;
  298. pdata->hash_hi = 0;
  299. pdata->hash_lo = 0;
  300. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  301. if (dev->net->flags & IFF_PROMISC) {
  302. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  303. pdata->mac_cr |= MAC_CR_PRMS_;
  304. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  305. } else if (dev->net->flags & IFF_ALLMULTI) {
  306. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  307. pdata->mac_cr |= MAC_CR_MCPAS_;
  308. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  309. } else if (!netdev_mc_empty(dev->net)) {
  310. struct netdev_hw_addr *ha;
  311. pdata->mac_cr |= MAC_CR_HPFILT_;
  312. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  313. netdev_for_each_mc_addr(ha, netdev) {
  314. u32 bitnum = smsc95xx_hash(ha->addr);
  315. u32 mask = 0x01 << (bitnum & 0x1F);
  316. if (bitnum & 0x20)
  317. pdata->hash_hi |= mask;
  318. else
  319. pdata->hash_lo |= mask;
  320. }
  321. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  322. pdata->hash_hi, pdata->hash_lo);
  323. } else {
  324. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  325. pdata->mac_cr &=
  326. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  327. }
  328. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  329. /* Initiate async writes, as we can't wait for completion here */
  330. smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi);
  331. smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo);
  332. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  333. }
  334. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  335. u16 lcladv, u16 rmtadv)
  336. {
  337. u32 flow, afc_cfg = 0;
  338. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  339. if (ret < 0) {
  340. netdev_warn(dev->net, "error reading AFC_CFG\n");
  341. return;
  342. }
  343. if (duplex == DUPLEX_FULL) {
  344. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  345. if (cap & FLOW_CTRL_RX)
  346. flow = 0xFFFF0002;
  347. else
  348. flow = 0;
  349. if (cap & FLOW_CTRL_TX)
  350. afc_cfg |= 0xF;
  351. else
  352. afc_cfg &= ~0xF;
  353. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  354. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  355. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  356. } else {
  357. netif_dbg(dev, link, dev->net, "half duplex\n");
  358. flow = 0;
  359. afc_cfg |= 0xF;
  360. }
  361. smsc95xx_write_reg(dev, FLOW, flow);
  362. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  363. }
  364. static int smsc95xx_link_reset(struct usbnet *dev)
  365. {
  366. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  367. struct mii_if_info *mii = &dev->mii;
  368. struct ethtool_cmd ecmd;
  369. unsigned long flags;
  370. u16 lcladv, rmtadv;
  371. u32 intdata;
  372. /* clear interrupt status */
  373. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  374. intdata = 0xFFFFFFFF;
  375. smsc95xx_write_reg(dev, INT_STS, intdata);
  376. mii_check_media(mii, 1, 1);
  377. mii_ethtool_gset(&dev->mii, &ecmd);
  378. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  379. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  380. netif_dbg(dev, link, dev->net, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x\n",
  381. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  382. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  383. if (ecmd.duplex != DUPLEX_FULL) {
  384. pdata->mac_cr &= ~MAC_CR_FDPX_;
  385. pdata->mac_cr |= MAC_CR_RCVOWN_;
  386. } else {
  387. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  388. pdata->mac_cr |= MAC_CR_FDPX_;
  389. }
  390. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  391. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  392. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  393. return 0;
  394. }
  395. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  396. {
  397. u32 intdata;
  398. if (urb->actual_length != 4) {
  399. netdev_warn(dev->net, "unexpected urb length %d\n",
  400. urb->actual_length);
  401. return;
  402. }
  403. memcpy(&intdata, urb->transfer_buffer, 4);
  404. le32_to_cpus(&intdata);
  405. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  406. if (intdata & INT_ENP_PHY_INT_)
  407. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  408. else
  409. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  410. intdata);
  411. }
  412. /* Enable or disable Tx & Rx checksum offload engines */
  413. static int smsc95xx_set_csums(struct usbnet *dev)
  414. {
  415. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  416. u32 read_buf;
  417. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  418. if (ret < 0) {
  419. netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret);
  420. return ret;
  421. }
  422. if (pdata->use_tx_csum)
  423. read_buf |= Tx_COE_EN_;
  424. else
  425. read_buf &= ~Tx_COE_EN_;
  426. if (pdata->use_rx_csum)
  427. read_buf |= Rx_COE_EN_;
  428. else
  429. read_buf &= ~Rx_COE_EN_;
  430. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  431. if (ret < 0) {
  432. netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret);
  433. return ret;
  434. }
  435. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  436. return 0;
  437. }
  438. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  439. {
  440. return MAX_EEPROM_SIZE;
  441. }
  442. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  443. struct ethtool_eeprom *ee, u8 *data)
  444. {
  445. struct usbnet *dev = netdev_priv(netdev);
  446. ee->magic = LAN95XX_EEPROM_MAGIC;
  447. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  448. }
  449. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  450. struct ethtool_eeprom *ee, u8 *data)
  451. {
  452. struct usbnet *dev = netdev_priv(netdev);
  453. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  454. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  455. ee->magic);
  456. return -EINVAL;
  457. }
  458. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  459. }
  460. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  461. {
  462. struct usbnet *dev = netdev_priv(netdev);
  463. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  464. return pdata->use_rx_csum;
  465. }
  466. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  467. {
  468. struct usbnet *dev = netdev_priv(netdev);
  469. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  470. pdata->use_rx_csum = !!val;
  471. return smsc95xx_set_csums(dev);
  472. }
  473. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  474. {
  475. struct usbnet *dev = netdev_priv(netdev);
  476. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  477. return pdata->use_tx_csum;
  478. }
  479. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  480. {
  481. struct usbnet *dev = netdev_priv(netdev);
  482. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  483. pdata->use_tx_csum = !!val;
  484. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  485. return smsc95xx_set_csums(dev);
  486. }
  487. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  488. .get_link = usbnet_get_link,
  489. .nway_reset = usbnet_nway_reset,
  490. .get_drvinfo = usbnet_get_drvinfo,
  491. .get_msglevel = usbnet_get_msglevel,
  492. .set_msglevel = usbnet_set_msglevel,
  493. .get_settings = usbnet_get_settings,
  494. .set_settings = usbnet_set_settings,
  495. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  496. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  497. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  498. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  499. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  500. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  501. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  502. };
  503. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  504. {
  505. struct usbnet *dev = netdev_priv(netdev);
  506. if (!netif_running(netdev))
  507. return -EINVAL;
  508. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  509. }
  510. static void smsc95xx_init_mac_address(struct usbnet *dev)
  511. {
  512. /* try reading mac address from EEPROM */
  513. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  514. dev->net->dev_addr) == 0) {
  515. if (is_valid_ether_addr(dev->net->dev_addr)) {
  516. /* eeprom values are valid so use them */
  517. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  518. return;
  519. }
  520. }
  521. /* no eeprom, or eeprom values are invalid. generate random MAC */
  522. random_ether_addr(dev->net->dev_addr);
  523. netif_dbg(dev, ifup, dev->net, "MAC address set to random_ether_addr\n");
  524. }
  525. static int smsc95xx_set_mac_address(struct usbnet *dev)
  526. {
  527. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  528. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  529. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  530. int ret;
  531. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  532. if (ret < 0) {
  533. netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret);
  534. return ret;
  535. }
  536. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  537. if (ret < 0) {
  538. netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret);
  539. return ret;
  540. }
  541. return 0;
  542. }
  543. /* starts the TX path */
  544. static void smsc95xx_start_tx_path(struct usbnet *dev)
  545. {
  546. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  547. unsigned long flags;
  548. u32 reg_val;
  549. /* Enable Tx at MAC */
  550. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  551. pdata->mac_cr |= MAC_CR_TXEN_;
  552. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  553. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  554. /* Enable Tx at SCSRs */
  555. reg_val = TX_CFG_ON_;
  556. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  557. }
  558. /* Starts the Receive path */
  559. static void smsc95xx_start_rx_path(struct usbnet *dev)
  560. {
  561. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  562. unsigned long flags;
  563. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  564. pdata->mac_cr |= MAC_CR_RXEN_;
  565. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  566. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  567. }
  568. static int smsc95xx_phy_initialize(struct usbnet *dev)
  569. {
  570. int bmcr, timeout = 0;
  571. /* Initialize MII structure */
  572. dev->mii.dev = dev->net;
  573. dev->mii.mdio_read = smsc95xx_mdio_read;
  574. dev->mii.mdio_write = smsc95xx_mdio_write;
  575. dev->mii.phy_id_mask = 0x1f;
  576. dev->mii.reg_num_mask = 0x1f;
  577. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  578. /* reset phy and wait for reset to complete */
  579. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  580. do {
  581. msleep(10);
  582. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  583. timeout++;
  584. } while ((bmcr & MII_BMCR) && (timeout < 100));
  585. if (timeout >= 100) {
  586. netdev_warn(dev->net, "timeout on PHY Reset");
  587. return -EIO;
  588. }
  589. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  590. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  591. ADVERTISE_PAUSE_ASYM);
  592. /* read to clear */
  593. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  594. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  595. PHY_INT_MASK_DEFAULT_);
  596. mii_nway_restart(&dev->mii);
  597. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  598. return 0;
  599. }
  600. static int smsc95xx_reset(struct usbnet *dev)
  601. {
  602. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  603. struct net_device *netdev = dev->net;
  604. u32 read_buf, write_buf, burst_cap;
  605. int ret = 0, timeout;
  606. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  607. write_buf = HW_CFG_LRST_;
  608. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  609. if (ret < 0) {
  610. netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
  611. ret);
  612. return ret;
  613. }
  614. timeout = 0;
  615. do {
  616. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  617. if (ret < 0) {
  618. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  619. return ret;
  620. }
  621. msleep(10);
  622. timeout++;
  623. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  624. if (timeout >= 100) {
  625. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  626. return ret;
  627. }
  628. write_buf = PM_CTL_PHY_RST_;
  629. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  630. if (ret < 0) {
  631. netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
  632. return ret;
  633. }
  634. timeout = 0;
  635. do {
  636. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  637. if (ret < 0) {
  638. netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret);
  639. return ret;
  640. }
  641. msleep(10);
  642. timeout++;
  643. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  644. if (timeout >= 100) {
  645. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  646. return ret;
  647. }
  648. ret = smsc95xx_set_mac_address(dev);
  649. if (ret < 0)
  650. return ret;
  651. netif_dbg(dev, ifup, dev->net,
  652. "MAC Address: %pM\n", dev->net->dev_addr);
  653. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  654. if (ret < 0) {
  655. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  656. return ret;
  657. }
  658. netif_dbg(dev, ifup, dev->net,
  659. "Read Value from HW_CFG : 0x%08x\n", read_buf);
  660. read_buf |= HW_CFG_BIR_;
  661. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  662. if (ret < 0) {
  663. netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n",
  664. ret);
  665. return ret;
  666. }
  667. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  668. if (ret < 0) {
  669. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  670. return ret;
  671. }
  672. netif_dbg(dev, ifup, dev->net,
  673. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  674. read_buf);
  675. if (!turbo_mode) {
  676. burst_cap = 0;
  677. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  678. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  679. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  680. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  681. } else {
  682. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  683. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  684. }
  685. netif_dbg(dev, ifup, dev->net,
  686. "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
  687. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  688. if (ret < 0) {
  689. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  690. return ret;
  691. }
  692. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  693. if (ret < 0) {
  694. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  695. return ret;
  696. }
  697. netif_dbg(dev, ifup, dev->net,
  698. "Read Value from BURST_CAP after writing: 0x%08x\n",
  699. read_buf);
  700. read_buf = DEFAULT_BULK_IN_DELAY;
  701. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  702. if (ret < 0) {
  703. netdev_warn(dev->net, "ret = %d\n", ret);
  704. return ret;
  705. }
  706. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  707. if (ret < 0) {
  708. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  709. return ret;
  710. }
  711. netif_dbg(dev, ifup, dev->net,
  712. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  713. read_buf);
  714. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  715. if (ret < 0) {
  716. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  717. return ret;
  718. }
  719. netif_dbg(dev, ifup, dev->net,
  720. "Read Value from HW_CFG: 0x%08x\n", read_buf);
  721. if (turbo_mode)
  722. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  723. read_buf &= ~HW_CFG_RXDOFF_;
  724. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  725. read_buf |= NET_IP_ALIGN << 9;
  726. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  727. if (ret < 0) {
  728. netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n",
  729. ret);
  730. return ret;
  731. }
  732. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  733. if (ret < 0) {
  734. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  735. return ret;
  736. }
  737. netif_dbg(dev, ifup, dev->net,
  738. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  739. write_buf = 0xFFFFFFFF;
  740. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  741. if (ret < 0) {
  742. netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
  743. ret);
  744. return ret;
  745. }
  746. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  747. if (ret < 0) {
  748. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  749. return ret;
  750. }
  751. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  752. /* Configure GPIO pins as LED outputs */
  753. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  754. LED_GPIO_CFG_FDX_LED;
  755. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  756. if (ret < 0) {
  757. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n",
  758. ret);
  759. return ret;
  760. }
  761. /* Init Tx */
  762. write_buf = 0;
  763. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  764. if (ret < 0) {
  765. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  766. return ret;
  767. }
  768. read_buf = AFC_CFG_DEFAULT;
  769. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  770. if (ret < 0) {
  771. netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
  772. return ret;
  773. }
  774. /* Don't need mac_cr_lock during initialisation */
  775. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  776. if (ret < 0) {
  777. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  778. return ret;
  779. }
  780. /* Init Rx */
  781. /* Set Vlan */
  782. write_buf = (u32)ETH_P_8021Q;
  783. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  784. if (ret < 0) {
  785. netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
  786. return ret;
  787. }
  788. /* Enable or disable checksum offload engines */
  789. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  790. ret = smsc95xx_set_csums(dev);
  791. if (ret < 0) {
  792. netdev_warn(dev->net, "Failed to set csum offload: %d\n", ret);
  793. return ret;
  794. }
  795. smsc95xx_set_multicast(dev->net);
  796. if (smsc95xx_phy_initialize(dev) < 0)
  797. return -EIO;
  798. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  799. if (ret < 0) {
  800. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  801. return ret;
  802. }
  803. /* enable PHY interrupts */
  804. read_buf |= INT_EP_CTL_PHY_INT_;
  805. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  806. if (ret < 0) {
  807. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  808. return ret;
  809. }
  810. smsc95xx_start_tx_path(dev);
  811. smsc95xx_start_rx_path(dev);
  812. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  813. return 0;
  814. }
  815. static const struct net_device_ops smsc95xx_netdev_ops = {
  816. .ndo_open = usbnet_open,
  817. .ndo_stop = usbnet_stop,
  818. .ndo_start_xmit = usbnet_start_xmit,
  819. .ndo_tx_timeout = usbnet_tx_timeout,
  820. .ndo_change_mtu = usbnet_change_mtu,
  821. .ndo_set_mac_address = eth_mac_addr,
  822. .ndo_validate_addr = eth_validate_addr,
  823. .ndo_do_ioctl = smsc95xx_ioctl,
  824. .ndo_set_multicast_list = smsc95xx_set_multicast,
  825. };
  826. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  827. {
  828. struct smsc95xx_priv *pdata = NULL;
  829. int ret;
  830. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  831. ret = usbnet_get_endpoints(dev, intf);
  832. if (ret < 0) {
  833. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  834. return ret;
  835. }
  836. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  837. GFP_KERNEL);
  838. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  839. if (!pdata) {
  840. netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
  841. return -ENOMEM;
  842. }
  843. spin_lock_init(&pdata->mac_cr_lock);
  844. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  845. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  846. smsc95xx_init_mac_address(dev);
  847. /* Init all registers */
  848. ret = smsc95xx_reset(dev);
  849. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  850. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  851. dev->net->flags |= IFF_MULTICAST;
  852. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  853. return 0;
  854. }
  855. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  856. {
  857. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  858. if (pdata) {
  859. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  860. kfree(pdata);
  861. pdata = NULL;
  862. dev->data[0] = 0;
  863. }
  864. }
  865. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  866. {
  867. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  868. skb->ip_summed = CHECKSUM_COMPLETE;
  869. skb_trim(skb, skb->len - 2);
  870. }
  871. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  872. {
  873. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  874. while (skb->len > 0) {
  875. u32 header, align_count;
  876. struct sk_buff *ax_skb;
  877. unsigned char *packet;
  878. u16 size;
  879. memcpy(&header, skb->data, sizeof(header));
  880. le32_to_cpus(&header);
  881. skb_pull(skb, 4 + NET_IP_ALIGN);
  882. packet = skb->data;
  883. /* get the packet length */
  884. size = (u16)((header & RX_STS_FL_) >> 16);
  885. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  886. if (unlikely(header & RX_STS_ES_)) {
  887. netif_dbg(dev, rx_err, dev->net,
  888. "Error header=0x%08x\n", header);
  889. dev->net->stats.rx_errors++;
  890. dev->net->stats.rx_dropped++;
  891. if (header & RX_STS_CRC_) {
  892. dev->net->stats.rx_crc_errors++;
  893. } else {
  894. if (header & (RX_STS_TL_ | RX_STS_RF_))
  895. dev->net->stats.rx_frame_errors++;
  896. if ((header & RX_STS_LE_) &&
  897. (!(header & RX_STS_FT_)))
  898. dev->net->stats.rx_length_errors++;
  899. }
  900. } else {
  901. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  902. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  903. netif_dbg(dev, rx_err, dev->net,
  904. "size err header=0x%08x\n", header);
  905. return 0;
  906. }
  907. /* last frame in this batch */
  908. if (skb->len == size) {
  909. if (pdata->use_rx_csum)
  910. smsc95xx_rx_csum_offload(skb);
  911. skb_trim(skb, skb->len - 4); /* remove fcs */
  912. skb->truesize = size + sizeof(struct sk_buff);
  913. return 1;
  914. }
  915. ax_skb = skb_clone(skb, GFP_ATOMIC);
  916. if (unlikely(!ax_skb)) {
  917. netdev_warn(dev->net, "Error allocating skb\n");
  918. return 0;
  919. }
  920. ax_skb->len = size;
  921. ax_skb->data = packet;
  922. skb_set_tail_pointer(ax_skb, size);
  923. if (pdata->use_rx_csum)
  924. smsc95xx_rx_csum_offload(ax_skb);
  925. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  926. ax_skb->truesize = size + sizeof(struct sk_buff);
  927. usbnet_skb_return(dev, ax_skb);
  928. }
  929. skb_pull(skb, size);
  930. /* padding bytes before the next frame starts */
  931. if (skb->len)
  932. skb_pull(skb, align_count);
  933. }
  934. if (unlikely(skb->len < 0)) {
  935. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  936. return 0;
  937. }
  938. return 1;
  939. }
  940. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  941. {
  942. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  943. u16 high_16 = low_16 + skb->csum_offset;
  944. return (high_16 << 16) | low_16;
  945. }
  946. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  947. struct sk_buff *skb, gfp_t flags)
  948. {
  949. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  950. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  951. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  952. u32 tx_cmd_a, tx_cmd_b;
  953. /* We do not advertise SG, so skbs should be already linearized */
  954. BUG_ON(skb_shinfo(skb)->nr_frags);
  955. if (skb_headroom(skb) < overhead) {
  956. struct sk_buff *skb2 = skb_copy_expand(skb,
  957. overhead, 0, flags);
  958. dev_kfree_skb_any(skb);
  959. skb = skb2;
  960. if (!skb)
  961. return NULL;
  962. }
  963. if (csum) {
  964. if (skb->len <= 45) {
  965. /* workaround - hardware tx checksum does not work
  966. * properly with extremely small packets */
  967. long csstart = skb_checksum_start_offset(skb);
  968. __wsum calc = csum_partial(skb->data + csstart,
  969. skb->len - csstart, 0);
  970. *((__sum16 *)(skb->data + csstart
  971. + skb->csum_offset)) = csum_fold(calc);
  972. csum = false;
  973. } else {
  974. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  975. skb_push(skb, 4);
  976. memcpy(skb->data, &csum_preamble, 4);
  977. }
  978. }
  979. skb_push(skb, 4);
  980. tx_cmd_b = (u32)(skb->len - 4);
  981. if (csum)
  982. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  983. cpu_to_le32s(&tx_cmd_b);
  984. memcpy(skb->data, &tx_cmd_b, 4);
  985. skb_push(skb, 4);
  986. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  987. TX_CMD_A_LAST_SEG_;
  988. cpu_to_le32s(&tx_cmd_a);
  989. memcpy(skb->data, &tx_cmd_a, 4);
  990. return skb;
  991. }
  992. static const struct driver_info smsc95xx_info = {
  993. .description = "smsc95xx USB 2.0 Ethernet",
  994. .bind = smsc95xx_bind,
  995. .unbind = smsc95xx_unbind,
  996. .link_reset = smsc95xx_link_reset,
  997. .reset = smsc95xx_reset,
  998. .rx_fixup = smsc95xx_rx_fixup,
  999. .tx_fixup = smsc95xx_tx_fixup,
  1000. .status = smsc95xx_status,
  1001. .flags = FLAG_ETHER | FLAG_SEND_ZLP,
  1002. };
  1003. static const struct usb_device_id products[] = {
  1004. {
  1005. /* SMSC9500 USB Ethernet Device */
  1006. USB_DEVICE(0x0424, 0x9500),
  1007. .driver_info = (unsigned long) &smsc95xx_info,
  1008. },
  1009. {
  1010. /* SMSC9505 USB Ethernet Device */
  1011. USB_DEVICE(0x0424, 0x9505),
  1012. .driver_info = (unsigned long) &smsc95xx_info,
  1013. },
  1014. {
  1015. /* SMSC9500A USB Ethernet Device */
  1016. USB_DEVICE(0x0424, 0x9E00),
  1017. .driver_info = (unsigned long) &smsc95xx_info,
  1018. },
  1019. {
  1020. /* SMSC9505A USB Ethernet Device */
  1021. USB_DEVICE(0x0424, 0x9E01),
  1022. .driver_info = (unsigned long) &smsc95xx_info,
  1023. },
  1024. {
  1025. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1026. USB_DEVICE(0x0424, 0xec00),
  1027. .driver_info = (unsigned long) &smsc95xx_info,
  1028. },
  1029. {
  1030. /* SMSC9500 USB Ethernet Device (SAL10) */
  1031. USB_DEVICE(0x0424, 0x9900),
  1032. .driver_info = (unsigned long) &smsc95xx_info,
  1033. },
  1034. {
  1035. /* SMSC9505 USB Ethernet Device (SAL10) */
  1036. USB_DEVICE(0x0424, 0x9901),
  1037. .driver_info = (unsigned long) &smsc95xx_info,
  1038. },
  1039. {
  1040. /* SMSC9500A USB Ethernet Device (SAL10) */
  1041. USB_DEVICE(0x0424, 0x9902),
  1042. .driver_info = (unsigned long) &smsc95xx_info,
  1043. },
  1044. {
  1045. /* SMSC9505A USB Ethernet Device (SAL10) */
  1046. USB_DEVICE(0x0424, 0x9903),
  1047. .driver_info = (unsigned long) &smsc95xx_info,
  1048. },
  1049. {
  1050. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1051. USB_DEVICE(0x0424, 0x9904),
  1052. .driver_info = (unsigned long) &smsc95xx_info,
  1053. },
  1054. {
  1055. /* SMSC9500A USB Ethernet Device (HAL) */
  1056. USB_DEVICE(0x0424, 0x9905),
  1057. .driver_info = (unsigned long) &smsc95xx_info,
  1058. },
  1059. {
  1060. /* SMSC9505A USB Ethernet Device (HAL) */
  1061. USB_DEVICE(0x0424, 0x9906),
  1062. .driver_info = (unsigned long) &smsc95xx_info,
  1063. },
  1064. {
  1065. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1066. USB_DEVICE(0x0424, 0x9907),
  1067. .driver_info = (unsigned long) &smsc95xx_info,
  1068. },
  1069. {
  1070. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1071. USB_DEVICE(0x0424, 0x9908),
  1072. .driver_info = (unsigned long) &smsc95xx_info,
  1073. },
  1074. {
  1075. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1076. USB_DEVICE(0x0424, 0x9909),
  1077. .driver_info = (unsigned long) &smsc95xx_info,
  1078. },
  1079. { }, /* END */
  1080. };
  1081. MODULE_DEVICE_TABLE(usb, products);
  1082. static struct usb_driver smsc95xx_driver = {
  1083. .name = "smsc95xx",
  1084. .id_table = products,
  1085. .probe = usbnet_probe,
  1086. .suspend = usbnet_suspend,
  1087. .resume = usbnet_resume,
  1088. .disconnect = usbnet_disconnect,
  1089. };
  1090. static int __init smsc95xx_init(void)
  1091. {
  1092. return usb_register(&smsc95xx_driver);
  1093. }
  1094. module_init(smsc95xx_init);
  1095. static void __exit smsc95xx_exit(void)
  1096. {
  1097. usb_deregister(&smsc95xx_driver);
  1098. }
  1099. module_exit(smsc95xx_exit);
  1100. MODULE_AUTHOR("Nancy Lin");
  1101. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1102. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1103. MODULE_LICENSE("GPL");