pnav10.c 13 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/etherdevice.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/irq.h>
  16. #include <asm/dma.h>
  17. #include <asm/bfin5xx_spi.h>
  18. #include <asm/portmux.h>
  19. #include <linux/spi/ad7877.h>
  20. /*
  21. * Name the Board for the /proc/cpuinfo
  22. */
  23. const char bfin_board_name[] = "ADI PNAV-1.0";
  24. /*
  25. * Driver needs to know address, irq and flag pin.
  26. */
  27. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  28. static struct resource bfin_pcmcia_cf_resources[] = {
  29. {
  30. .start = 0x20310000, /* IO PORT */
  31. .end = 0x20312000,
  32. .flags = IORESOURCE_MEM,
  33. }, {
  34. .start = 0x20311000, /* Attribute Memory */
  35. .end = 0x20311FFF,
  36. .flags = IORESOURCE_MEM,
  37. }, {
  38. .start = IRQ_PF4,
  39. .end = IRQ_PF4,
  40. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  41. }, {
  42. .start = 6, /* Card Detect PF6 */
  43. .end = 6,
  44. .flags = IORESOURCE_IRQ,
  45. },
  46. };
  47. static struct platform_device bfin_pcmcia_cf_device = {
  48. .name = "bfin_cf_pcmcia",
  49. .id = -1,
  50. .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
  51. .resource = bfin_pcmcia_cf_resources,
  52. };
  53. #endif
  54. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  55. static struct platform_device rtc_device = {
  56. .name = "rtc-bfin",
  57. .id = -1,
  58. };
  59. #endif
  60. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  61. #include <linux/smc91x.h>
  62. static struct smc91x_platdata smc91x_info = {
  63. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  64. .leda = RPC_LED_100_10,
  65. .ledb = RPC_LED_TX_RX,
  66. };
  67. static struct resource smc91x_resources[] = {
  68. {
  69. .name = "smc91x-regs",
  70. .start = 0x20300300,
  71. .end = 0x20300300 + 16,
  72. .flags = IORESOURCE_MEM,
  73. }, {
  74. .start = IRQ_PF7,
  75. .end = IRQ_PF7,
  76. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  77. },
  78. };
  79. static struct platform_device smc91x_device = {
  80. .name = "smc91x",
  81. .id = 0,
  82. .num_resources = ARRAY_SIZE(smc91x_resources),
  83. .resource = smc91x_resources,
  84. .dev = {
  85. .platform_data = &smc91x_info,
  86. },
  87. };
  88. #endif
  89. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  90. #include <linux/bfin_mac.h>
  91. static const unsigned short bfin_mac_peripherals[] = P_RMII0;
  92. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  93. {
  94. .addr = 1,
  95. .irq = IRQ_MAC_PHYINT,
  96. },
  97. };
  98. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  99. .phydev_number = 1,
  100. .phydev_data = bfin_phydev_data,
  101. .phy_mode = PHY_INTERFACE_MODE_RMII,
  102. .mac_peripherals = bfin_mac_peripherals,
  103. };
  104. static struct platform_device bfin_mii_bus = {
  105. .name = "bfin_mii_bus",
  106. .dev = {
  107. .platform_data = &bfin_mii_bus_data,
  108. }
  109. };
  110. static struct platform_device bfin_mac_device = {
  111. .name = "bfin_mac",
  112. .dev = {
  113. .platform_data = &bfin_mii_bus,
  114. }
  115. };
  116. #endif
  117. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  118. static struct resource net2272_bfin_resources[] = {
  119. {
  120. .start = 0x20300000,
  121. .end = 0x20300000 + 0x100,
  122. .flags = IORESOURCE_MEM,
  123. }, {
  124. .start = IRQ_PF7,
  125. .end = IRQ_PF7,
  126. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  127. },
  128. };
  129. static struct platform_device net2272_bfin_device = {
  130. .name = "net2272",
  131. .id = -1,
  132. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  133. .resource = net2272_bfin_resources,
  134. };
  135. #endif
  136. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  137. /* all SPI peripherals info goes here */
  138. #if defined(CONFIG_MTD_M25P80) \
  139. || defined(CONFIG_MTD_M25P80_MODULE)
  140. static struct mtd_partition bfin_spi_flash_partitions[] = {
  141. {
  142. .name = "bootloader(spi)",
  143. .size = 0x00020000,
  144. .offset = 0,
  145. .mask_flags = MTD_CAP_ROM
  146. }, {
  147. .name = "linux kernel(spi)",
  148. .size = 0xe0000,
  149. .offset = 0x20000
  150. }, {
  151. .name = "file system(spi)",
  152. .size = 0x700000,
  153. .offset = 0x00100000,
  154. }
  155. };
  156. static struct flash_platform_data bfin_spi_flash_data = {
  157. .name = "m25p80",
  158. .parts = bfin_spi_flash_partitions,
  159. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  160. .type = "m25p64",
  161. };
  162. /* SPI flash chip (m25p64) */
  163. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  164. .enable_dma = 0, /* use dma transfer with this chip*/
  165. .bits_per_word = 8,
  166. };
  167. #endif
  168. #if defined(CONFIG_BFIN_SPI_ADC) \
  169. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  170. /* SPI ADC chip */
  171. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  172. .enable_dma = 1, /* use dma transfer with this chip*/
  173. .bits_per_word = 16,
  174. };
  175. #endif
  176. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
  177. || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  178. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  179. .enable_dma = 0,
  180. .bits_per_word = 16,
  181. };
  182. #endif
  183. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  184. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  185. .enable_dma = 0,
  186. .bits_per_word = 8,
  187. };
  188. #endif
  189. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  190. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  191. .enable_dma = 0,
  192. .bits_per_word = 16,
  193. };
  194. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  195. .model = 7877,
  196. .vref_delay_usecs = 50, /* internal, no capacitor */
  197. .x_plate_ohms = 419,
  198. .y_plate_ohms = 486,
  199. .pressure_max = 1000,
  200. .pressure_min = 0,
  201. .stopacq_polarity = 1,
  202. .first_conversion_delay = 3,
  203. .acquisition_time = 1,
  204. .averaging = 1,
  205. .pen_down_acc_interval = 1,
  206. };
  207. #endif
  208. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  209. #if defined(CONFIG_MTD_M25P80) \
  210. || defined(CONFIG_MTD_M25P80_MODULE)
  211. {
  212. /* the modalias must be the same as spi device driver name */
  213. .modalias = "m25p80", /* Name of spi_driver for this device */
  214. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  215. .bus_num = 0, /* Framework bus number */
  216. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  217. .platform_data = &bfin_spi_flash_data,
  218. .controller_data = &spi_flash_chip_info,
  219. .mode = SPI_MODE_3,
  220. },
  221. #endif
  222. #if defined(CONFIG_BFIN_SPI_ADC) \
  223. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  224. {
  225. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  226. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  227. .bus_num = 0, /* Framework bus number */
  228. .chip_select = 1, /* Framework chip select. */
  229. .platform_data = NULL, /* No spi_driver specific config */
  230. .controller_data = &spi_adc_chip_info,
  231. },
  232. #endif
  233. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
  234. || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  235. {
  236. .modalias = "ad183x",
  237. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  238. .bus_num = 0,
  239. .chip_select = 4,
  240. .controller_data = &ad1836_spi_chip_info,
  241. },
  242. #endif
  243. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  244. {
  245. .modalias = "mmc_spi",
  246. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  247. .bus_num = 0,
  248. .chip_select = 5,
  249. .controller_data = &mmc_spi_chip_info,
  250. .mode = SPI_MODE_3,
  251. },
  252. #endif
  253. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  254. {
  255. .modalias = "ad7877",
  256. .platform_data = &bfin_ad7877_ts_info,
  257. .irq = IRQ_PF2,
  258. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  259. .bus_num = 0,
  260. .chip_select = 5,
  261. .controller_data = &spi_ad7877_chip_info,
  262. },
  263. #endif
  264. };
  265. /* SPI (0) */
  266. static struct resource bfin_spi0_resource[] = {
  267. [0] = {
  268. .start = SPI0_REGBASE,
  269. .end = SPI0_REGBASE + 0xFF,
  270. .flags = IORESOURCE_MEM,
  271. },
  272. [1] = {
  273. .start = CH_SPI,
  274. .end = CH_SPI,
  275. .flags = IORESOURCE_DMA,
  276. },
  277. [2] = {
  278. .start = IRQ_SPI,
  279. .end = IRQ_SPI,
  280. .flags = IORESOURCE_IRQ,
  281. },
  282. };
  283. /* SPI controller data */
  284. static struct bfin5xx_spi_master bfin_spi0_info = {
  285. .num_chipselect = 8,
  286. .enable_dma = 1, /* master has the ability to do dma transfer */
  287. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  288. };
  289. static struct platform_device bfin_spi0_device = {
  290. .name = "bfin-spi",
  291. .id = 0, /* Bus number */
  292. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  293. .resource = bfin_spi0_resource,
  294. .dev = {
  295. .platform_data = &bfin_spi0_info, /* Passed to driver */
  296. },
  297. };
  298. #endif /* spi master and devices */
  299. #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
  300. static struct platform_device bfin_fb_device = {
  301. .name = "bf537-lq035",
  302. };
  303. #endif
  304. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  305. #ifdef CONFIG_SERIAL_BFIN_UART0
  306. static struct resource bfin_uart0_resources[] = {
  307. {
  308. .start = UART0_THR,
  309. .end = UART0_GCTL+2,
  310. .flags = IORESOURCE_MEM,
  311. },
  312. {
  313. .start = IRQ_UART0_RX,
  314. .end = IRQ_UART0_RX+1,
  315. .flags = IORESOURCE_IRQ,
  316. },
  317. {
  318. .start = IRQ_UART0_ERROR,
  319. .end = IRQ_UART0_ERROR,
  320. .flags = IORESOURCE_IRQ,
  321. },
  322. {
  323. .start = CH_UART0_TX,
  324. .end = CH_UART0_TX,
  325. .flags = IORESOURCE_DMA,
  326. },
  327. {
  328. .start = CH_UART0_RX,
  329. .end = CH_UART0_RX,
  330. .flags = IORESOURCE_DMA,
  331. },
  332. };
  333. static unsigned short bfin_uart0_peripherals[] = {
  334. P_UART0_TX, P_UART0_RX, 0
  335. };
  336. static struct platform_device bfin_uart0_device = {
  337. .name = "bfin-uart",
  338. .id = 0,
  339. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  340. .resource = bfin_uart0_resources,
  341. .dev = {
  342. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  343. },
  344. };
  345. #endif
  346. #ifdef CONFIG_SERIAL_BFIN_UART1
  347. static struct resource bfin_uart1_resources[] = {
  348. {
  349. .start = UART1_THR,
  350. .end = UART1_GCTL+2,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. {
  354. .start = IRQ_UART1_RX,
  355. .end = IRQ_UART1_RX+1,
  356. .flags = IORESOURCE_IRQ,
  357. },
  358. {
  359. .start = IRQ_UART1_ERROR,
  360. .end = IRQ_UART1_ERROR,
  361. .flags = IORESOURCE_IRQ,
  362. },
  363. {
  364. .start = CH_UART1_TX,
  365. .end = CH_UART1_TX,
  366. .flags = IORESOURCE_DMA,
  367. },
  368. {
  369. .start = CH_UART1_RX,
  370. .end = CH_UART1_RX,
  371. .flags = IORESOURCE_DMA,
  372. },
  373. };
  374. static unsigned short bfin_uart1_peripherals[] = {
  375. P_UART1_TX, P_UART1_RX, 0
  376. };
  377. static struct platform_device bfin_uart1_device = {
  378. .name = "bfin-uart",
  379. .id = 1,
  380. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  381. .resource = bfin_uart1_resources,
  382. .dev = {
  383. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  384. },
  385. };
  386. #endif
  387. #endif
  388. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  389. #ifdef CONFIG_BFIN_SIR0
  390. static struct resource bfin_sir0_resources[] = {
  391. {
  392. .start = 0xFFC00400,
  393. .end = 0xFFC004FF,
  394. .flags = IORESOURCE_MEM,
  395. },
  396. {
  397. .start = IRQ_UART0_RX,
  398. .end = IRQ_UART0_RX+1,
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. {
  402. .start = CH_UART0_RX,
  403. .end = CH_UART0_RX+1,
  404. .flags = IORESOURCE_DMA,
  405. },
  406. };
  407. static struct platform_device bfin_sir0_device = {
  408. .name = "bfin_sir",
  409. .id = 0,
  410. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  411. .resource = bfin_sir0_resources,
  412. };
  413. #endif
  414. #ifdef CONFIG_BFIN_SIR1
  415. static struct resource bfin_sir1_resources[] = {
  416. {
  417. .start = 0xFFC02000,
  418. .end = 0xFFC020FF,
  419. .flags = IORESOURCE_MEM,
  420. },
  421. {
  422. .start = IRQ_UART1_RX,
  423. .end = IRQ_UART1_RX+1,
  424. .flags = IORESOURCE_IRQ,
  425. },
  426. {
  427. .start = CH_UART1_RX,
  428. .end = CH_UART1_RX+1,
  429. .flags = IORESOURCE_DMA,
  430. },
  431. };
  432. static struct platform_device bfin_sir1_device = {
  433. .name = "bfin_sir",
  434. .id = 1,
  435. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  436. .resource = bfin_sir1_resources,
  437. };
  438. #endif
  439. #endif
  440. static struct platform_device *stamp_devices[] __initdata = {
  441. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  442. &bfin_pcmcia_cf_device,
  443. #endif
  444. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  445. &rtc_device,
  446. #endif
  447. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  448. &smc91x_device,
  449. #endif
  450. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  451. &bfin_mii_bus,
  452. &bfin_mac_device,
  453. #endif
  454. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  455. &net2272_bfin_device,
  456. #endif
  457. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  458. &bfin_spi0_device,
  459. #endif
  460. #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
  461. &bfin_fb_device,
  462. #endif
  463. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  464. #ifdef CONFIG_SERIAL_BFIN_UART0
  465. &bfin_uart0_device,
  466. #endif
  467. #ifdef CONFIG_SERIAL_BFIN_UART1
  468. &bfin_uart1_device,
  469. #endif
  470. #endif
  471. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  472. #ifdef CONFIG_BFIN_SIR0
  473. &bfin_sir0_device,
  474. #endif
  475. #ifdef CONFIG_BFIN_SIR1
  476. &bfin_sir1_device,
  477. #endif
  478. #endif
  479. };
  480. static int __init pnav_init(void)
  481. {
  482. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  483. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  484. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  485. spi_register_board_info(bfin_spi_board_info,
  486. ARRAY_SIZE(bfin_spi_board_info));
  487. #endif
  488. return 0;
  489. }
  490. arch_initcall(pnav_init);
  491. static struct platform_device *stamp_early_devices[] __initdata = {
  492. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  493. #ifdef CONFIG_SERIAL_BFIN_UART0
  494. &bfin_uart0_device,
  495. #endif
  496. #ifdef CONFIG_SERIAL_BFIN_UART1
  497. &bfin_uart1_device,
  498. #endif
  499. #endif
  500. };
  501. void __init native_machine_early_platform_add_devices(void)
  502. {
  503. printk(KERN_INFO "register early platform devices\n");
  504. early_platform_add_devices(stamp_early_devices,
  505. ARRAY_SIZE(stamp_early_devices));
  506. }
  507. void bfin_get_ether_addr(char *addr)
  508. {
  509. random_ether_addr(addr);
  510. printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
  511. }
  512. EXPORT_SYMBOL(bfin_get_ether_addr);