cm_bf537e.c 19 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2008-2009 Bluetechnix
  4. * 2005 National ICT Australia (NICTA)
  5. * Aidan Williams <aidan@nicta.com.au>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/etherdevice.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/partitions.h>
  14. #include <linux/mtd/physmap.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/spi/flash.h>
  17. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  18. #include <linux/usb/isp1362.h>
  19. #endif
  20. #include <linux/ata_platform.h>
  21. #include <linux/irq.h>
  22. #include <asm/dma.h>
  23. #include <asm/bfin5xx_spi.h>
  24. #include <asm/portmux.h>
  25. #include <asm/dpmc.h>
  26. /*
  27. * Name the Board for the /proc/cpuinfo
  28. */
  29. const char bfin_board_name[] = "Bluetechnix CM BF537E";
  30. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  31. /* all SPI peripherals info goes here */
  32. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  33. static struct mtd_partition bfin_spi_flash_partitions[] = {
  34. {
  35. .name = "bootloader(spi)",
  36. .size = 0x00020000,
  37. .offset = 0,
  38. .mask_flags = MTD_CAP_ROM
  39. }, {
  40. .name = "linux kernel(spi)",
  41. .size = 0xe0000,
  42. .offset = 0x20000
  43. }, {
  44. .name = "file system(spi)",
  45. .size = 0x700000,
  46. .offset = 0x00100000,
  47. }
  48. };
  49. static struct flash_platform_data bfin_spi_flash_data = {
  50. .name = "m25p80",
  51. .parts = bfin_spi_flash_partitions,
  52. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  53. .type = "m25p64",
  54. };
  55. /* SPI flash chip (m25p64) */
  56. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  57. .enable_dma = 0, /* use dma transfer with this chip*/
  58. .bits_per_word = 8,
  59. };
  60. #endif
  61. #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  62. /* SPI ADC chip */
  63. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  64. .enable_dma = 1, /* use dma transfer with this chip*/
  65. .bits_per_word = 16,
  66. };
  67. #endif
  68. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  69. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  70. .enable_dma = 0,
  71. .bits_per_word = 16,
  72. };
  73. #endif
  74. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  75. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  76. .enable_dma = 0,
  77. .bits_per_word = 8,
  78. };
  79. #endif
  80. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  81. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  82. {
  83. /* the modalias must be the same as spi device driver name */
  84. .modalias = "m25p80", /* Name of spi_driver for this device */
  85. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  86. .bus_num = 0, /* Framework bus number */
  87. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  88. .platform_data = &bfin_spi_flash_data,
  89. .controller_data = &spi_flash_chip_info,
  90. .mode = SPI_MODE_3,
  91. },
  92. #endif
  93. #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  94. {
  95. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  96. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  97. .bus_num = 0, /* Framework bus number */
  98. .chip_select = 1, /* Framework chip select. */
  99. .platform_data = NULL, /* No spi_driver specific config */
  100. .controller_data = &spi_adc_chip_info,
  101. },
  102. #endif
  103. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  104. {
  105. .modalias = "ad183x",
  106. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  107. .bus_num = 0,
  108. .chip_select = 4,
  109. .controller_data = &ad1836_spi_chip_info,
  110. },
  111. #endif
  112. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  113. {
  114. .modalias = "mmc_spi",
  115. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  116. .bus_num = 0,
  117. .chip_select = 1,
  118. .controller_data = &mmc_spi_chip_info,
  119. .mode = SPI_MODE_3,
  120. },
  121. #endif
  122. };
  123. /* SPI (0) */
  124. static struct resource bfin_spi0_resource[] = {
  125. [0] = {
  126. .start = SPI0_REGBASE,
  127. .end = SPI0_REGBASE + 0xFF,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. [1] = {
  131. .start = CH_SPI,
  132. .end = CH_SPI,
  133. .flags = IORESOURCE_DMA,
  134. },
  135. [2] = {
  136. .start = IRQ_SPI,
  137. .end = IRQ_SPI,
  138. .flags = IORESOURCE_IRQ,
  139. },
  140. };
  141. /* SPI controller data */
  142. static struct bfin5xx_spi_master bfin_spi0_info = {
  143. .num_chipselect = 8,
  144. .enable_dma = 1, /* master has the ability to do dma transfer */
  145. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  146. };
  147. static struct platform_device bfin_spi0_device = {
  148. .name = "bfin-spi",
  149. .id = 0, /* Bus number */
  150. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  151. .resource = bfin_spi0_resource,
  152. .dev = {
  153. .platform_data = &bfin_spi0_info, /* Passed to driver */
  154. },
  155. };
  156. #endif /* spi master and devices */
  157. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  158. static struct platform_device rtc_device = {
  159. .name = "rtc-bfin",
  160. .id = -1,
  161. };
  162. #endif
  163. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  164. static struct platform_device hitachi_fb_device = {
  165. .name = "hitachi-tx09",
  166. };
  167. #endif
  168. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  169. #include <linux/smc91x.h>
  170. static struct smc91x_platdata smc91x_info = {
  171. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  172. .leda = RPC_LED_100_10,
  173. .ledb = RPC_LED_TX_RX,
  174. };
  175. static struct resource smc91x_resources[] = {
  176. {
  177. .start = 0x20200300,
  178. .end = 0x20200300 + 16,
  179. .flags = IORESOURCE_MEM,
  180. }, {
  181. .start = IRQ_PF14,
  182. .end = IRQ_PF14,
  183. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  184. },
  185. };
  186. static struct platform_device smc91x_device = {
  187. .name = "smc91x",
  188. .id = 0,
  189. .num_resources = ARRAY_SIZE(smc91x_resources),
  190. .resource = smc91x_resources,
  191. .dev = {
  192. .platform_data = &smc91x_info,
  193. },
  194. };
  195. #endif
  196. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  197. static struct resource isp1362_hcd_resources[] = {
  198. {
  199. .start = 0x20308000,
  200. .end = 0x20308000,
  201. .flags = IORESOURCE_MEM,
  202. }, {
  203. .start = 0x20308004,
  204. .end = 0x20308004,
  205. .flags = IORESOURCE_MEM,
  206. }, {
  207. .start = IRQ_PG15,
  208. .end = IRQ_PG15,
  209. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  210. },
  211. };
  212. static struct isp1362_platform_data isp1362_priv = {
  213. .sel15Kres = 1,
  214. .clknotstop = 0,
  215. .oc_enable = 0,
  216. .int_act_high = 0,
  217. .int_edge_triggered = 0,
  218. .remote_wakeup_connected = 0,
  219. .no_power_switching = 1,
  220. .power_switching_mode = 0,
  221. };
  222. static struct platform_device isp1362_hcd_device = {
  223. .name = "isp1362-hcd",
  224. .id = 0,
  225. .dev = {
  226. .platform_data = &isp1362_priv,
  227. },
  228. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  229. .resource = isp1362_hcd_resources,
  230. };
  231. #endif
  232. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  233. static struct resource net2272_bfin_resources[] = {
  234. {
  235. .start = 0x20300000,
  236. .end = 0x20300000 + 0x100,
  237. .flags = IORESOURCE_MEM,
  238. }, {
  239. .start = IRQ_PG13,
  240. .end = IRQ_PG13,
  241. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  242. },
  243. };
  244. static struct platform_device net2272_bfin_device = {
  245. .name = "net2272",
  246. .id = -1,
  247. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  248. .resource = net2272_bfin_resources,
  249. };
  250. #endif
  251. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  252. static struct mtd_partition cm_partitions[] = {
  253. {
  254. .name = "bootloader(nor)",
  255. .size = 0x40000,
  256. .offset = 0,
  257. }, {
  258. .name = "linux kernel(nor)",
  259. .size = 0x100000,
  260. .offset = MTDPART_OFS_APPEND,
  261. }, {
  262. .name = "file system(nor)",
  263. .size = MTDPART_SIZ_FULL,
  264. .offset = MTDPART_OFS_APPEND,
  265. }
  266. };
  267. static struct physmap_flash_data cm_flash_data = {
  268. .width = 2,
  269. .parts = cm_partitions,
  270. .nr_parts = ARRAY_SIZE(cm_partitions),
  271. };
  272. static unsigned cm_flash_gpios[] = { GPIO_PF4 };
  273. static struct resource cm_flash_resource[] = {
  274. {
  275. .name = "cfi_probe",
  276. .start = 0x20000000,
  277. .end = 0x201fffff,
  278. .flags = IORESOURCE_MEM,
  279. }, {
  280. .start = (unsigned long)cm_flash_gpios,
  281. .end = ARRAY_SIZE(cm_flash_gpios),
  282. .flags = IORESOURCE_IRQ,
  283. }
  284. };
  285. static struct platform_device cm_flash_device = {
  286. .name = "gpio-addr-flash",
  287. .id = 0,
  288. .dev = {
  289. .platform_data = &cm_flash_data,
  290. },
  291. .num_resources = ARRAY_SIZE(cm_flash_resource),
  292. .resource = cm_flash_resource,
  293. };
  294. #endif
  295. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  296. #ifdef CONFIG_SERIAL_BFIN_UART0
  297. static struct resource bfin_uart0_resources[] = {
  298. {
  299. .start = UART0_THR,
  300. .end = UART0_GCTL+2,
  301. .flags = IORESOURCE_MEM,
  302. },
  303. {
  304. .start = IRQ_UART0_RX,
  305. .end = IRQ_UART0_RX+1,
  306. .flags = IORESOURCE_IRQ,
  307. },
  308. {
  309. .start = IRQ_UART0_ERROR,
  310. .end = IRQ_UART0_ERROR,
  311. .flags = IORESOURCE_IRQ,
  312. },
  313. {
  314. .start = CH_UART0_TX,
  315. .end = CH_UART0_TX,
  316. .flags = IORESOURCE_DMA,
  317. },
  318. {
  319. .start = CH_UART0_RX,
  320. .end = CH_UART0_RX,
  321. .flags = IORESOURCE_DMA,
  322. },
  323. #ifdef CONFIG_BFIN_UART0_CTSRTS
  324. {
  325. /*
  326. * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
  327. */
  328. .start = -1,
  329. .end = -1,
  330. .flags = IORESOURCE_IO,
  331. },
  332. {
  333. /*
  334. * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
  335. */
  336. .start = -1,
  337. .end = -1,
  338. .flags = IORESOURCE_IO,
  339. },
  340. #endif
  341. };
  342. static unsigned short bfin_uart0_peripherals[] = {
  343. P_UART0_TX, P_UART0_RX, 0
  344. };
  345. static struct platform_device bfin_uart0_device = {
  346. .name = "bfin-uart",
  347. .id = 0,
  348. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  349. .resource = bfin_uart0_resources,
  350. .dev = {
  351. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  352. },
  353. };
  354. #endif
  355. #ifdef CONFIG_SERIAL_BFIN_UART1
  356. static struct resource bfin_uart1_resources[] = {
  357. {
  358. .start = UART1_THR,
  359. .end = UART1_GCTL+2,
  360. .flags = IORESOURCE_MEM,
  361. },
  362. {
  363. .start = IRQ_UART1_RX,
  364. .end = IRQ_UART1_RX+1,
  365. .flags = IORESOURCE_IRQ,
  366. },
  367. {
  368. .start = IRQ_UART1_ERROR,
  369. .end = IRQ_UART1_ERROR,
  370. .flags = IORESOURCE_IRQ,
  371. },
  372. {
  373. .start = CH_UART1_TX,
  374. .end = CH_UART1_TX,
  375. .flags = IORESOURCE_DMA,
  376. },
  377. {
  378. .start = CH_UART1_RX,
  379. .end = CH_UART1_RX,
  380. .flags = IORESOURCE_DMA,
  381. },
  382. #ifdef CONFIG_BFIN_UART1_CTSRTS
  383. {
  384. /*
  385. * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
  386. */
  387. .start = -1,
  388. .end = -1,
  389. .flags = IORESOURCE_IO,
  390. },
  391. {
  392. /*
  393. * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
  394. */
  395. .start = -1,
  396. .end = -1,
  397. .flags = IORESOURCE_IO,
  398. },
  399. #endif
  400. };
  401. static unsigned short bfin_uart1_peripherals[] = {
  402. P_UART1_TX, P_UART1_RX, 0
  403. };
  404. static struct platform_device bfin_uart1_device = {
  405. .name = "bfin-uart",
  406. .id = 1,
  407. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  408. .resource = bfin_uart1_resources,
  409. .dev = {
  410. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  411. },
  412. };
  413. #endif
  414. #endif
  415. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  416. #ifdef CONFIG_BFIN_SIR0
  417. static struct resource bfin_sir0_resources[] = {
  418. {
  419. .start = 0xFFC00400,
  420. .end = 0xFFC004FF,
  421. .flags = IORESOURCE_MEM,
  422. },
  423. {
  424. .start = IRQ_UART0_RX,
  425. .end = IRQ_UART0_RX+1,
  426. .flags = IORESOURCE_IRQ,
  427. },
  428. {
  429. .start = CH_UART0_RX,
  430. .end = CH_UART0_RX+1,
  431. .flags = IORESOURCE_DMA,
  432. },
  433. };
  434. static struct platform_device bfin_sir0_device = {
  435. .name = "bfin_sir",
  436. .id = 0,
  437. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  438. .resource = bfin_sir0_resources,
  439. };
  440. #endif
  441. #ifdef CONFIG_BFIN_SIR1
  442. static struct resource bfin_sir1_resources[] = {
  443. {
  444. .start = 0xFFC02000,
  445. .end = 0xFFC020FF,
  446. .flags = IORESOURCE_MEM,
  447. },
  448. {
  449. .start = IRQ_UART1_RX,
  450. .end = IRQ_UART1_RX+1,
  451. .flags = IORESOURCE_IRQ,
  452. },
  453. {
  454. .start = CH_UART1_RX,
  455. .end = CH_UART1_RX+1,
  456. .flags = IORESOURCE_DMA,
  457. },
  458. };
  459. static struct platform_device bfin_sir1_device = {
  460. .name = "bfin_sir",
  461. .id = 1,
  462. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  463. .resource = bfin_sir1_resources,
  464. };
  465. #endif
  466. #endif
  467. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  468. static struct resource bfin_twi0_resource[] = {
  469. [0] = {
  470. .start = TWI0_REGBASE,
  471. .end = TWI0_REGBASE,
  472. .flags = IORESOURCE_MEM,
  473. },
  474. [1] = {
  475. .start = IRQ_TWI,
  476. .end = IRQ_TWI,
  477. .flags = IORESOURCE_IRQ,
  478. },
  479. };
  480. static struct platform_device i2c_bfin_twi_device = {
  481. .name = "i2c-bfin-twi",
  482. .id = 0,
  483. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  484. .resource = bfin_twi0_resource,
  485. };
  486. #endif
  487. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  488. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  489. static struct resource bfin_sport0_uart_resources[] = {
  490. {
  491. .start = SPORT0_TCR1,
  492. .end = SPORT0_MRCS3+4,
  493. .flags = IORESOURCE_MEM,
  494. },
  495. {
  496. .start = IRQ_SPORT0_RX,
  497. .end = IRQ_SPORT0_RX+1,
  498. .flags = IORESOURCE_IRQ,
  499. },
  500. {
  501. .start = IRQ_SPORT0_ERROR,
  502. .end = IRQ_SPORT0_ERROR,
  503. .flags = IORESOURCE_IRQ,
  504. },
  505. };
  506. static unsigned short bfin_sport0_peripherals[] = {
  507. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  508. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  509. };
  510. static struct platform_device bfin_sport0_uart_device = {
  511. .name = "bfin-sport-uart",
  512. .id = 0,
  513. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  514. .resource = bfin_sport0_uart_resources,
  515. .dev = {
  516. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  517. },
  518. };
  519. #endif
  520. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  521. static struct resource bfin_sport1_uart_resources[] = {
  522. {
  523. .start = SPORT1_TCR1,
  524. .end = SPORT1_MRCS3+4,
  525. .flags = IORESOURCE_MEM,
  526. },
  527. {
  528. .start = IRQ_SPORT1_RX,
  529. .end = IRQ_SPORT1_RX+1,
  530. .flags = IORESOURCE_IRQ,
  531. },
  532. {
  533. .start = IRQ_SPORT1_ERROR,
  534. .end = IRQ_SPORT1_ERROR,
  535. .flags = IORESOURCE_IRQ,
  536. },
  537. };
  538. static unsigned short bfin_sport1_peripherals[] = {
  539. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  540. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  541. };
  542. static struct platform_device bfin_sport1_uart_device = {
  543. .name = "bfin-sport-uart",
  544. .id = 1,
  545. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  546. .resource = bfin_sport1_uart_resources,
  547. .dev = {
  548. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  549. },
  550. };
  551. #endif
  552. #endif
  553. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  554. #include <linux/bfin_mac.h>
  555. static const unsigned short bfin_mac_peripherals[] = P_MII0;
  556. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  557. {
  558. .addr = 1,
  559. .irq = IRQ_MAC_PHYINT,
  560. },
  561. };
  562. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  563. .phydev_number = 1,
  564. .phydev_data = bfin_phydev_data,
  565. .phy_mode = PHY_INTERFACE_MODE_MII,
  566. .mac_peripherals = bfin_mac_peripherals,
  567. };
  568. static struct platform_device bfin_mii_bus = {
  569. .name = "bfin_mii_bus",
  570. .dev = {
  571. .platform_data = &bfin_mii_bus_data,
  572. }
  573. };
  574. static struct platform_device bfin_mac_device = {
  575. .name = "bfin_mac",
  576. .dev = {
  577. .platform_data = &bfin_mii_bus,
  578. }
  579. };
  580. #endif
  581. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  582. #define PATA_INT IRQ_PF14
  583. static struct pata_platform_info bfin_pata_platform_data = {
  584. .ioport_shift = 2,
  585. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  586. };
  587. static struct resource bfin_pata_resources[] = {
  588. {
  589. .start = 0x2030C000,
  590. .end = 0x2030C01F,
  591. .flags = IORESOURCE_MEM,
  592. },
  593. {
  594. .start = 0x2030D018,
  595. .end = 0x2030D01B,
  596. .flags = IORESOURCE_MEM,
  597. },
  598. {
  599. .start = PATA_INT,
  600. .end = PATA_INT,
  601. .flags = IORESOURCE_IRQ,
  602. },
  603. };
  604. static struct platform_device bfin_pata_device = {
  605. .name = "pata_platform",
  606. .id = -1,
  607. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  608. .resource = bfin_pata_resources,
  609. .dev = {
  610. .platform_data = &bfin_pata_platform_data,
  611. }
  612. };
  613. #endif
  614. static const unsigned int cclk_vlev_datasheet[] =
  615. {
  616. VRPAIR(VLEV_085, 250000000),
  617. VRPAIR(VLEV_090, 376000000),
  618. VRPAIR(VLEV_095, 426000000),
  619. VRPAIR(VLEV_100, 426000000),
  620. VRPAIR(VLEV_105, 476000000),
  621. VRPAIR(VLEV_110, 476000000),
  622. VRPAIR(VLEV_115, 476000000),
  623. VRPAIR(VLEV_120, 500000000),
  624. VRPAIR(VLEV_125, 533000000),
  625. VRPAIR(VLEV_130, 600000000),
  626. };
  627. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  628. .tuple_tab = cclk_vlev_datasheet,
  629. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  630. .vr_settling_time = 25 /* us */,
  631. };
  632. static struct platform_device bfin_dpmc = {
  633. .name = "bfin dpmc",
  634. .dev = {
  635. .platform_data = &bfin_dmpc_vreg_data,
  636. },
  637. };
  638. static struct platform_device *cm_bf537e_devices[] __initdata = {
  639. &bfin_dpmc,
  640. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  641. &hitachi_fb_device,
  642. #endif
  643. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  644. &rtc_device,
  645. #endif
  646. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  647. #ifdef CONFIG_SERIAL_BFIN_UART0
  648. &bfin_uart0_device,
  649. #endif
  650. #ifdef CONFIG_SERIAL_BFIN_UART1
  651. &bfin_uart1_device,
  652. #endif
  653. #endif
  654. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  655. #ifdef CONFIG_BFIN_SIR0
  656. &bfin_sir0_device,
  657. #endif
  658. #ifdef CONFIG_BFIN_SIR1
  659. &bfin_sir1_device,
  660. #endif
  661. #endif
  662. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  663. &i2c_bfin_twi_device,
  664. #endif
  665. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  666. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  667. &bfin_sport0_uart_device,
  668. #endif
  669. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  670. &bfin_sport1_uart_device,
  671. #endif
  672. #endif
  673. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  674. &isp1362_hcd_device,
  675. #endif
  676. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  677. &smc91x_device,
  678. #endif
  679. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  680. &bfin_mii_bus,
  681. &bfin_mac_device,
  682. #endif
  683. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  684. &net2272_bfin_device,
  685. #endif
  686. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  687. &bfin_spi0_device,
  688. #endif
  689. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  690. &bfin_pata_device,
  691. #endif
  692. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  693. &cm_flash_device,
  694. #endif
  695. };
  696. static int __init cm_bf537e_init(void)
  697. {
  698. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  699. platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
  700. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  701. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  702. #endif
  703. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  704. irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
  705. #endif
  706. return 0;
  707. }
  708. arch_initcall(cm_bf537e_init);
  709. static struct platform_device *cm_bf537e_early_devices[] __initdata = {
  710. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  711. #ifdef CONFIG_SERIAL_BFIN_UART0
  712. &bfin_uart0_device,
  713. #endif
  714. #ifdef CONFIG_SERIAL_BFIN_UART1
  715. &bfin_uart1_device,
  716. #endif
  717. #endif
  718. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  719. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  720. &bfin_sport0_uart_device,
  721. #endif
  722. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  723. &bfin_sport1_uart_device,
  724. #endif
  725. #endif
  726. };
  727. void __init native_machine_early_platform_add_devices(void)
  728. {
  729. printk(KERN_INFO "register early platform devices\n");
  730. early_platform_add_devices(cm_bf537e_early_devices,
  731. ARRAY_SIZE(cm_bf537e_early_devices));
  732. }
  733. void bfin_get_ether_addr(char *addr)
  734. {
  735. random_ether_addr(addr);
  736. printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
  737. }
  738. EXPORT_SYMBOL(bfin_get_ether_addr);