H8606.c 11 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2007-2008 HV Sistemas S.L.
  4. * Javier Herrero <jherrero@hvsistemas.es>
  5. * 2005 National ICT Australia (NICTA)
  6. * Aidan Williams <aidan@nicta.com.au>
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/partitions.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/flash.h>
  16. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  17. #include <linux/usb/isp1362.h>
  18. #endif
  19. #include <linux/irq.h>
  20. #include <asm/dma.h>
  21. #include <asm/bfin5xx_spi.h>
  22. #include <asm/reboot.h>
  23. #include <asm/portmux.h>
  24. /*
  25. * Name the Board for the /proc/cpuinfo
  26. */
  27. const char bfin_board_name[] = "HV Sistemas H8606";
  28. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  29. static struct platform_device rtc_device = {
  30. .name = "rtc-bfin",
  31. .id = -1,
  32. };
  33. #endif
  34. /*
  35. * Driver needs to know address, irq and flag pin.
  36. */
  37. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  38. static struct resource dm9000_resources[] = {
  39. [0] = {
  40. .start = 0x20300000,
  41. .end = 0x20300002,
  42. .flags = IORESOURCE_MEM,
  43. },
  44. [1] = {
  45. .start = 0x20300004,
  46. .end = 0x20300006,
  47. .flags = IORESOURCE_MEM,
  48. },
  49. [2] = {
  50. .start = IRQ_PF10,
  51. .end = IRQ_PF10,
  52. .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH),
  53. },
  54. };
  55. static struct platform_device dm9000_device = {
  56. .id = 0,
  57. .name = "dm9000",
  58. .resource = dm9000_resources,
  59. .num_resources = ARRAY_SIZE(dm9000_resources),
  60. };
  61. #endif
  62. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  63. #include <linux/smc91x.h>
  64. static struct smc91x_platdata smc91x_info = {
  65. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  66. .leda = RPC_LED_100_10,
  67. .ledb = RPC_LED_TX_RX,
  68. };
  69. static struct resource smc91x_resources[] = {
  70. {
  71. .name = "smc91x-regs",
  72. .start = 0x20300300,
  73. .end = 0x20300300 + 16,
  74. .flags = IORESOURCE_MEM,
  75. }, {
  76. .start = IRQ_PROG_INTB,
  77. .end = IRQ_PROG_INTB,
  78. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  79. }, {
  80. .start = IRQ_PF7,
  81. .end = IRQ_PF7,
  82. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  83. },
  84. };
  85. static struct platform_device smc91x_device = {
  86. .name = "smc91x",
  87. .id = 0,
  88. .num_resources = ARRAY_SIZE(smc91x_resources),
  89. .resource = smc91x_resources,
  90. .dev = {
  91. .platform_data = &smc91x_info,
  92. },
  93. };
  94. #endif
  95. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  96. static struct resource net2272_bfin_resources[] = {
  97. {
  98. .start = 0x20300000,
  99. .end = 0x20300000 + 0x100,
  100. .flags = IORESOURCE_MEM,
  101. }, {
  102. .start = IRQ_PF10,
  103. .end = IRQ_PF10,
  104. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  105. },
  106. };
  107. static struct platform_device net2272_bfin_device = {
  108. .name = "net2272",
  109. .id = -1,
  110. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  111. .resource = net2272_bfin_resources,
  112. };
  113. #endif
  114. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  115. /* all SPI peripherals info goes here */
  116. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  117. static struct mtd_partition bfin_spi_flash_partitions[] = {
  118. {
  119. .name = "bootloader (spi)",
  120. .size = 0x40000,
  121. .offset = 0,
  122. .mask_flags = MTD_CAP_ROM
  123. }, {
  124. .name = "fpga (spi)",
  125. .size = 0x30000,
  126. .offset = 0x40000
  127. }, {
  128. .name = "linux kernel (spi)",
  129. .size = 0x150000,
  130. .offset = 0x70000
  131. }, {
  132. .name = "jffs2 root file system (spi)",
  133. .size = 0x640000,
  134. .offset = 0x1c0000,
  135. }
  136. };
  137. static struct flash_platform_data bfin_spi_flash_data = {
  138. .name = "m25p80",
  139. .parts = bfin_spi_flash_partitions,
  140. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  141. .type = "m25p64",
  142. };
  143. /* SPI flash chip (m25p64) */
  144. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  145. .enable_dma = 0, /* use dma transfer with this chip*/
  146. .bits_per_word = 8,
  147. };
  148. #endif
  149. #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  150. /* SPI ADC chip */
  151. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  152. .enable_dma = 1, /* use dma transfer with this chip*/
  153. .bits_per_word = 16,
  154. };
  155. #endif
  156. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  157. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  158. .enable_dma = 0,
  159. .bits_per_word = 16,
  160. };
  161. #endif
  162. /* Notice: for blackfin, the speed_hz is the value of register
  163. * SPI_BAUD, not the real baudrate */
  164. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  165. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  166. {
  167. /* the modalias must be the same as spi device driver name */
  168. .modalias = "m25p80", /* Name of spi_driver for this device */
  169. /* this value is the baudrate divisor */
  170. .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
  171. .bus_num = 0, /* Framework bus number */
  172. .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
  173. .platform_data = &bfin_spi_flash_data,
  174. .controller_data = &spi_flash_chip_info,
  175. .mode = SPI_MODE_3,
  176. },
  177. #endif
  178. #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  179. {
  180. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  181. .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */
  182. .bus_num = 1, /* Framework bus number */
  183. .chip_select = 1, /* Framework chip select. */
  184. .platform_data = NULL, /* No spi_driver specific config */
  185. .controller_data = &spi_adc_chip_info,
  186. },
  187. #endif
  188. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  189. {
  190. .modalias = "ad183x",
  191. .max_speed_hz = 16,
  192. .bus_num = 1,
  193. .chip_select = 4,
  194. .controller_data = &ad1836_spi_chip_info,
  195. },
  196. #endif
  197. };
  198. /* SPI (0) */
  199. static struct resource bfin_spi0_resource[] = {
  200. [0] = {
  201. .start = SPI0_REGBASE,
  202. .end = SPI0_REGBASE + 0xFF,
  203. .flags = IORESOURCE_MEM,
  204. },
  205. [1] = {
  206. .start = CH_SPI,
  207. .end = CH_SPI,
  208. .flags = IORESOURCE_DMA,
  209. },
  210. [2] = {
  211. .start = IRQ_SPI,
  212. .end = IRQ_SPI,
  213. .flags = IORESOURCE_IRQ,
  214. }
  215. };
  216. /* SPI controller data */
  217. static struct bfin5xx_spi_master bfin_spi0_info = {
  218. .num_chipselect = 8,
  219. .enable_dma = 1, /* master has the ability to do dma transfer */
  220. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  221. };
  222. static struct platform_device bfin_spi0_device = {
  223. .name = "bfin-spi",
  224. .id = 0, /* Bus number */
  225. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  226. .resource = bfin_spi0_resource,
  227. .dev = {
  228. .platform_data = &bfin_spi0_info, /* Passed to driver */
  229. },
  230. };
  231. #endif /* spi master and devices */
  232. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  233. #ifdef CONFIG_SERIAL_BFIN_UART0
  234. static struct resource bfin_uart0_resources[] = {
  235. {
  236. .start = BFIN_UART_THR,
  237. .end = BFIN_UART_GCTL+2,
  238. .flags = IORESOURCE_MEM,
  239. },
  240. {
  241. .start = IRQ_UART0_RX,
  242. .end = IRQ_UART0_RX + 1,
  243. .flags = IORESOURCE_IRQ,
  244. },
  245. {
  246. .start = IRQ_UART0_ERROR,
  247. .end = IRQ_UART0_ERROR,
  248. .flags = IORESOURCE_IRQ,
  249. },
  250. {
  251. .start = CH_UART0_TX,
  252. .end = CH_UART0_TX,
  253. .flags = IORESOURCE_DMA,
  254. },
  255. {
  256. .start = CH_UART0_RX,
  257. .end = CH_UART0_RX,
  258. .flags = IORESOURCE_DMA,
  259. },
  260. };
  261. static unsigned short bfin_uart0_peripherals[] = {
  262. P_UART0_TX, P_UART0_RX, 0
  263. };
  264. static struct platform_device bfin_uart0_device = {
  265. .name = "bfin-uart",
  266. .id = 0,
  267. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  268. .resource = bfin_uart0_resources,
  269. .dev = {
  270. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  271. },
  272. };
  273. #endif
  274. #endif
  275. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  276. #ifdef CONFIG_BFIN_SIR0
  277. static struct resource bfin_sir0_resources[] = {
  278. {
  279. .start = 0xFFC00400,
  280. .end = 0xFFC004FF,
  281. .flags = IORESOURCE_MEM,
  282. },
  283. {
  284. .start = IRQ_UART0_RX,
  285. .end = IRQ_UART0_RX+1,
  286. .flags = IORESOURCE_IRQ,
  287. },
  288. {
  289. .start = CH_UART0_RX,
  290. .end = CH_UART0_RX+1,
  291. .flags = IORESOURCE_DMA,
  292. },
  293. };
  294. static struct platform_device bfin_sir0_device = {
  295. .name = "bfin_sir",
  296. .id = 0,
  297. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  298. .resource = bfin_sir0_resources,
  299. };
  300. #endif
  301. #endif
  302. #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  303. #include <linux/serial_8250.h>
  304. #include <linux/serial.h>
  305. /*
  306. * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
  307. * running at half system clock, both with interrupt output or-ed to PF8. Change to
  308. * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
  309. */
  310. static struct plat_serial8250_port serial8250_platform_data [] = {
  311. {
  312. .membase = (void *)0x20200000,
  313. .mapbase = 0x20200000,
  314. .irq = IRQ_PF8,
  315. .irqflags = IRQF_TRIGGER_HIGH,
  316. .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
  317. .iotype = UPIO_MEM,
  318. .regshift = 1,
  319. .uartclk = 66666667,
  320. }, {
  321. .membase = (void *)0x20200010,
  322. .mapbase = 0x20200010,
  323. .irq = IRQ_PF8,
  324. .irqflags = IRQF_TRIGGER_HIGH,
  325. .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
  326. .iotype = UPIO_MEM,
  327. .regshift = 1,
  328. .uartclk = 66666667,
  329. }, {
  330. }
  331. };
  332. static struct platform_device serial8250_device = {
  333. .id = PLAT8250_DEV_PLATFORM,
  334. .name = "serial8250",
  335. .dev = {
  336. .platform_data = serial8250_platform_data,
  337. },
  338. };
  339. #endif
  340. #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
  341. /*
  342. * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
  343. * interrupt output wired to PF9. Change to suit different FPGA configuration
  344. */
  345. static struct resource opencores_kbd_resources[] = {
  346. [0] = {
  347. .start = 0x20200030,
  348. .end = 0x20300030 + 2,
  349. .flags = IORESOURCE_MEM,
  350. },
  351. [1] = {
  352. .start = IRQ_PF9,
  353. .end = IRQ_PF9,
  354. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  355. },
  356. };
  357. static struct platform_device opencores_kbd_device = {
  358. .id = -1,
  359. .name = "opencores-kbd",
  360. .resource = opencores_kbd_resources,
  361. .num_resources = ARRAY_SIZE(opencores_kbd_resources),
  362. };
  363. #endif
  364. static struct platform_device *h8606_devices[] __initdata = {
  365. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  366. &rtc_device,
  367. #endif
  368. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  369. &dm9000_device,
  370. #endif
  371. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  372. &smc91x_device,
  373. #endif
  374. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  375. &net2272_bfin_device,
  376. #endif
  377. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  378. &bfin_spi0_device,
  379. #endif
  380. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  381. #ifdef CONFIG_SERIAL_BFIN_UART0
  382. &bfin_uart0_device,
  383. #endif
  384. #endif
  385. #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  386. &serial8250_device,
  387. #endif
  388. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  389. #ifdef CONFIG_BFIN_SIR0
  390. &bfin_sir0_device,
  391. #endif
  392. #endif
  393. #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
  394. &opencores_kbd_device,
  395. #endif
  396. };
  397. static int __init H8606_init(void)
  398. {
  399. printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
  400. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  401. platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
  402. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  403. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  404. #endif
  405. return 0;
  406. }
  407. arch_initcall(H8606_init);
  408. static struct platform_device *H8606_early_devices[] __initdata = {
  409. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  410. #ifdef CONFIG_SERIAL_BFIN_UART0
  411. &bfin_uart0_device,
  412. #endif
  413. #endif
  414. };
  415. void __init native_machine_early_platform_add_devices(void)
  416. {
  417. printk(KERN_INFO "register early platform devices\n");
  418. early_platform_add_devices(H8606_early_devices,
  419. ARRAY_SIZE(H8606_early_devices));
  420. }