dev-spi.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. /* linux/arch/arm/mach-s5p6442/dev-spi.c
  2. *
  3. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  4. * Jaswinder Singh <jassi.brar@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/gpio.h>
  13. #include <mach/dma.h>
  14. #include <mach/map.h>
  15. #include <mach/irqs.h>
  16. #include <mach/spi-clocks.h>
  17. #include <plat/s3c64xx-spi.h>
  18. #include <plat/gpio-cfg.h>
  19. static char *spi_src_clks[] = {
  20. [S5P6442_SPI_SRCCLK_PCLK] = "pclk",
  21. [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
  22. };
  23. /* SPI Controller platform_devices */
  24. /* Since we emulate multi-cs capability, we do not touch the CS.
  25. * The emulated CS is toggled by board specific mechanism, as it can
  26. * be either some immediate GPIO or some signal out of some other
  27. * chip in between ... or some yet another way.
  28. * We simply do not assume anything about CS.
  29. */
  30. static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
  31. {
  32. switch (pdev->id) {
  33. case 0:
  34. s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
  35. s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
  36. s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
  37. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  38. break;
  39. default:
  40. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  41. return -EINVAL;
  42. }
  43. return 0;
  44. }
  45. static struct resource s5p6442_spi0_resource[] = {
  46. [0] = {
  47. .start = S5P6442_PA_SPI,
  48. .end = S5P6442_PA_SPI + 0x100 - 1,
  49. .flags = IORESOURCE_MEM,
  50. },
  51. [1] = {
  52. .start = DMACH_SPI0_TX,
  53. .end = DMACH_SPI0_TX,
  54. .flags = IORESOURCE_DMA,
  55. },
  56. [2] = {
  57. .start = DMACH_SPI0_RX,
  58. .end = DMACH_SPI0_RX,
  59. .flags = IORESOURCE_DMA,
  60. },
  61. [3] = {
  62. .start = IRQ_SPI0,
  63. .end = IRQ_SPI0,
  64. .flags = IORESOURCE_IRQ,
  65. },
  66. };
  67. static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
  68. .cfg_gpio = s5p6442_spi_cfg_gpio,
  69. .fifo_lvl_mask = 0x1ff,
  70. .rx_lvl_offset = 15,
  71. };
  72. static u64 spi_dmamask = DMA_BIT_MASK(32);
  73. struct platform_device s5p6442_device_spi = {
  74. .name = "s3c64xx-spi",
  75. .id = 0,
  76. .num_resources = ARRAY_SIZE(s5p6442_spi0_resource),
  77. .resource = s5p6442_spi0_resource,
  78. .dev = {
  79. .dma_mask = &spi_dmamask,
  80. .coherent_dma_mask = DMA_BIT_MASK(32),
  81. .platform_data = &s5p6442_spi0_pdata,
  82. },
  83. };
  84. void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  85. {
  86. struct s3c64xx_spi_info *pd;
  87. /* Reject invalid configuration */
  88. if (!num_cs || src_clk_nr < 0
  89. || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
  90. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  91. return;
  92. }
  93. switch (cntrlr) {
  94. case 0:
  95. pd = &s5p6442_spi0_pdata;
  96. break;
  97. default:
  98. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  99. __func__, cntrlr);
  100. return;
  101. }
  102. pd->num_cs = num_cs;
  103. pd->src_clk_nr = src_clk_nr;
  104. pd->src_clk_name = spi_src_clks[src_clk_nr];
  105. }