s3c2442.c 4.2 KB

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  1. /* linux/arch/arm/mach-s3c2442/s3c2442.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C2442 core and lock support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/list.h>
  27. #include <linux/errno.h>
  28. #include <linux/err.h>
  29. #include <linux/device.h>
  30. #include <linux/sysdev.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/ioport.h>
  33. #include <linux/mutex.h>
  34. #include <linux/gpio.h>
  35. #include <linux/clk.h>
  36. #include <linux/io.h>
  37. #include <mach/hardware.h>
  38. #include <asm/atomic.h>
  39. #include <asm/irq.h>
  40. #include <mach/regs-clock.h>
  41. #include <plat/clock.h>
  42. #include <plat/cpu.h>
  43. #include <plat/s3c244x.h>
  44. #include <plat/gpio-core.h>
  45. #include <plat/gpio-cfg.h>
  46. #include <plat/gpio-cfg-helpers.h>
  47. /* S3C2442 extended clock support */
  48. static unsigned long s3c2442_camif_upll_round(struct clk *clk,
  49. unsigned long rate)
  50. {
  51. unsigned long parent_rate = clk_get_rate(clk->parent);
  52. int div;
  53. if (rate > parent_rate)
  54. return parent_rate;
  55. div = parent_rate / rate;
  56. if (div == 3)
  57. return parent_rate / 3;
  58. /* note, we remove the +/- 1 calculations for the divisor */
  59. div /= 2;
  60. if (div < 1)
  61. div = 1;
  62. else if (div > 16)
  63. div = 16;
  64. return parent_rate / (div * 2);
  65. }
  66. static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
  67. {
  68. unsigned long parent_rate = clk_get_rate(clk->parent);
  69. unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
  70. rate = s3c2442_camif_upll_round(clk, rate);
  71. camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
  72. if (rate == parent_rate) {
  73. camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
  74. } else if ((parent_rate / rate) == 3) {
  75. camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  76. camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
  77. } else {
  78. camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
  79. camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  80. camdivn |= (((parent_rate / rate) / 2) - 1);
  81. }
  82. __raw_writel(camdivn, S3C2440_CAMDIVN);
  83. return 0;
  84. }
  85. /* Extra S3C2442 clocks */
  86. static struct clk s3c2442_clk_cam = {
  87. .name = "camif",
  88. .id = -1,
  89. .enable = s3c2410_clkcon_enable,
  90. .ctrlbit = S3C2440_CLKCON_CAMERA,
  91. };
  92. static struct clk s3c2442_clk_cam_upll = {
  93. .name = "camif-upll",
  94. .id = -1,
  95. .ops = &(struct clk_ops) {
  96. .set_rate = s3c2442_camif_upll_setrate,
  97. .round_rate = s3c2442_camif_upll_round,
  98. },
  99. };
  100. static int s3c2442_clk_add(struct sys_device *sysdev)
  101. {
  102. struct clk *clock_upll;
  103. struct clk *clock_h;
  104. struct clk *clock_p;
  105. clock_p = clk_get(NULL, "pclk");
  106. clock_h = clk_get(NULL, "hclk");
  107. clock_upll = clk_get(NULL, "upll");
  108. if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
  109. printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
  110. return -EINVAL;
  111. }
  112. s3c2442_clk_cam.parent = clock_h;
  113. s3c2442_clk_cam_upll.parent = clock_upll;
  114. s3c24xx_register_clock(&s3c2442_clk_cam);
  115. s3c24xx_register_clock(&s3c2442_clk_cam_upll);
  116. clk_disable(&s3c2442_clk_cam);
  117. return 0;
  118. }
  119. static struct sysdev_driver s3c2442_clk_driver = {
  120. .add = s3c2442_clk_add,
  121. };
  122. static __init int s3c2442_clk_init(void)
  123. {
  124. return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
  125. }
  126. arch_initcall(s3c2442_clk_init);
  127. static struct sys_device s3c2442_sysdev = {
  128. .cls = &s3c2442_sysclass,
  129. };
  130. int __init s3c2442_init(void)
  131. {
  132. printk("S3C2442: Initialising architecture\n");
  133. return sysdev_register(&s3c2442_sysdev);
  134. }
  135. void __init s3c2442_map_io(void)
  136. {
  137. s3c244x_map_io();
  138. s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
  139. s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
  140. }